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| | * | | avr32: delete non generic board hammerheadAndreas Bießmann2015-06-101-4/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | | avr32: delete non generic board favr-32-ezkitAndreas Bießmann2015-06-101-4/+0
| | |/ / | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | tegra: Replace 'Norrin' with 'Nyan-big' and fix typoSimon Glass2015-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the rename the MAINTAINER file was not updated. Fix it and the 'Chrombook' typo in Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Allow board-specific initSimon Glass2015-06-092-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a hook to allows boards to add their own init to board_init(). Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Add missing tegra124 peripheralsSimon Glass2015-06-092-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some missing entries in the tables. Add them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Introduce SRAM repair on tegra124Simon Glass2015-06-092-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required in order to avoid instability when running from caches after the kernel starts. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: clock: Adjust PLL access to avoid a warningSimon Glass2015-06-091-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A harmless but confusing warning is displayed when looking up the DisplayPort PLL. Correct this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: clock: Support enabling external clocksSimon Glass2015-06-092-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a simple function to enable external clocks. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-bigSimon Glass2015-06-091-0/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the EC and keyboard, using the SPI bus. The EC driver requires a particular format and a deactivation delay. Also U-Boot does not support interrupts. For now, adjust the device tree to comply. At some point we should tidy this up to support interrupts and make tegra and exynos use the same setup. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-06-0815-6/+304
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| | * imx: drop warning: unused variable 'max_freq'Stefano Babic2015-06-081-1/+2
| | | | | | | | | | | | | | | | | | | | | max_freq in print_cpuinfo is used only with imx6. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * colibri_vf: Enable board specific USB initialisation for USB pen gpioSanchayan Maity2015-06-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IOMUX for the pad used as USB pen. This needs to be driven low for the Iris and Viola boards where it is pulled up high by default. This is required for the USB host functionality to work on these boards. Use the board specific weak initialisation function, to drive the pin low which would be called on "usb start". Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| | * vf610: dts: Add device tree supportBhuvanchandra DV2015-06-085-0/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree files for Freescale Vybrid platform and Toradex Colibri VF50, VF61 modules. Device tree files are taken from upstream Kernel. Removed the stuff which are not used/supported yet in U-Boot. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| | * arm: vf610: Add iomux support for DSPIBhuvanchandra DV2015-06-081-0/+9
| | | | | | | | | | | | | | | | | | Add iomux definitions for DSPI second instance. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| | * arm: vf610: Add clock support for DSPIBhuvanchandra DV2015-06-083-0/+12
| | | | | | | | | | | | Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| | * colibri_vf: Add pinmux entries for GPIOsBhuvanchandra DV2015-06-081-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs. Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| | * dm: gpio: vf610: Add GPIO driver supportBhuvanchandra DV2015-06-084-0/+66
| | | | | | | | | | | | | | | | | | Add GPIO driver support to Freescale VF610 Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| | * mxs: Do not disable bo detection when DC-DC is already enabledStefan Wahren2015-06-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case the DC-DC is already enabled mxs_enable_4p2_dcdc_input() returns without reenabling brown out detection. So fix this issue by moving the return before brown out deactivation. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Marek Vasut <marex@denx.de>
| | * Revert "imx: drop warning: unused variable 'max_freq'"Stefano Babic2015-05-281-2/+1
| | | | | | | | | | | | | | | | | | This reverts commit a0117a5e416629932becf079589f5e1859eab90a. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * imx: drop warning: unused variable 'max_freq'Stefano Babic2015-05-271-1/+2
| | | | | | | | | | | | | | | | | | | | | max_freq in print_cpuinfo is used only with imx6. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | Merge git://git.denx.de/u-boot-sunxiTom Rini2015-06-0668-1105/+1785
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| | * | sunxi: Add a proper dts file for the ga10h a33 based tabletHans de Goede2015-06-052-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add and use a proper dts for the ga10h a33 based tablet, as submitted upstream. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * | sunxi: Sync dts files with the linux kernelHans de Goede2015-06-0465-1102/+1506
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2 , this gives us a proper dtsi file for the A33 rather then abusing sun8i-a23.dtsi for this. And this replaces our minimal (dummy) sun7i-a20-mk808c and sun8i-a33-astar-mid756 dts files with proper ones. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * | sunxi: Add new Mele_A1000G_quad defconfigHans de Goede2015-06-042-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been using the same defconfig (and dts on the kernel side) for both models. Unfortunately this does not work for the otg controller, on the M9 this is routed to a micro-usb connector on the outside, while as on the A1000G-quad it is connected to an usb to sata bridge. This commit adds a new defconfig for the Mele-A1000G-quad to allow using different otg controller settings on the 2 boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| | * | sunxi: usb_phy: Swap check for disconnect thresholdHans de Goede2015-06-041-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit the code for determining the disconnect threshold was checking for sun4i or sun6i assuming that those where the exception and that newer SoCs use a disconnect threshold of 2 like sun7i does. But it turns out that newer SoCs actually use a disconnect threshold of 3 and sun5i and sun7i are the exceptions, so check for those instead. Here are the settings from the various Allwinner SDK sources: sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); Note this commit makes no functional changes for sun4i - sun7i, and changes the disconnect threshold for sun8i to match what Allwinner uses. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | Merge git://git.denx.de/u-boot-dmTom Rini2015-06-055-80/+104
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| | * | | sandbox: Compile test device tree when CONFIG_UT_DM is definedSimon Glass2015-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A conflict between the PMIC and unit test work means that the sandbox test device tree file is no-longer built. Fix this. Series-to: u-boot Series-cc: joe, prz Change-Id: I6616428e05713e5306f848e7dd0a645dedf0934e Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | sandbox: dts: Add the real-time-clock test nodes back inSimon Glass2015-06-041-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These were lost when the PMIC series was applied. Add them back so that the tests pass again. Reported-by: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| | * | | sandbox: dts: Sort the sandbox.dts fileSimon Glass2015-06-041-52/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sort this by node name for easier browsing. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | sandbox: dts: Sort the test.dts file a littleSimon Glass2015-06-041-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some core test nodes near the beginning of the file which should be grouped together. But for other nodes, let's sort them. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| | * | | sandbox: Tidy up terminal restoreSimon Glass2015-06-042-3/+7
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason 'u-boot -D' does not restore the terminal correctly when the 'reset' command is used. Call the terminal restore function explicitly in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-042-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: baytrail: pci region 3 is not always mapped to end of ramAndrew Bradford2015-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF and additional SDRAM is mapped from 0x100000000 and up. There is a physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses. Because of this, PCI region 3 should only try to use up to the amount of SDRAM or 0x80000000, which ever is less. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: qemu: Implement PIRQ routingBin Meng2015-06-044-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethernet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: coreboot: Control I/O port 0xb2 writing via device treeBin Meng2015-06-042-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes U-Boot to hang on QEMU q35 target. We introduce a config option in the device tree "u-boot,no-apm-finalize" under /config node if we don't want to do that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: qemu: Create separate i440fx and q35 device treesBin Meng2015-06-043-2/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although the two qemu-x86 targets (i440fx and q35) share a lot in common, they still have something that cannot easily handled in one single device tree). Split to create two dedicated device tree files and make the i440fx be the default build target. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: coreboot: Fix cosmetic issuesBin Meng2015-06-042-25/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSPBin Meng2015-06-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: qemu: Adjust VGA initializationBin Meng2015-06-042-19/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As VGA option rom needs to run at C segment, although QEMU PAM emulation seems to only guard E/F segments, for correctness, move VGA initialization after PAM decode C/D/E/F segments. Also since we already tested QEMU targets to differentiate I440FX and Q35 platforms, change to locate the VGA device via hardcoded b.d.f instead of dynamic search for its vendor id & device id pair. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: qemu: Enable legacy IDE I/O ports decodeBin Meng2015-06-043-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix driver does sanity check to see whether legacy ports decode is turned on. To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: qemu: Turn on legacy segments decodeBin Meng2015-06-042-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: fsp_support: Correct high mem comment typoAndrew Bradford2015-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | High mem starts at 4 GiB. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: Do sanity test on pirq table before writingBin Meng2015-06-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If pirq_routing_table points to NULL, that means U-Boot fails to generate the table before in create_pirq_routing_table(), so we test it against NULL before actually writing it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: quark: Implement PIRQ routingBin Meng2015-06-044-15/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: Refactor PIRQ routing supportBin Meng2015-06-048-300/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: qemu: Add graphics supportBin Meng2015-06-041-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that QEMU x86 emulated graphic card has a built-in option ROM which can be run perfectly with native mode by U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video KconfigBin Meng2015-06-041-141/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE are not x86-specific, so move them to drivers/video/Kconfig and make them depend on VIDEO_VESA driver. Some cosmetic fixes are applied to the Kconfig help text as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | x86: Make QEMU the default vendorBin Meng2015-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have QEMU support, make it the default vendor in the 'make menuconfig' screen. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | | x86: Support QEMU x86 targetsBin Meng2015-06-0412-1/+259
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces the initial U-Boot support for QEMU x86 targets. U-Boot can boot from coreboot as a payload, or directly without coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig https://patchwork.ozlabs.org/patch/479745/
* | | armv7: better comment in start.SPavel Machek2015-07-071-4/+3
|/ / | | | | | | | | | | | | Fix big/small letters in comment. Signed-off-by: Pavel Machek <pavel@denx.de> Tested-by: Marek Vasut <marex@denx.de>
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