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* x86: Probe pinctrl driver in cpu_init_r()Bin Meng2016-06-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | At present pinctrl driver gets probed in ich6_gpio driver's probe routine, which has two issues: - Pin's PADs only gets configured when GPIO driver is probed, which is not done by default. This leaves the board in a partially functional state as we must initialize PADs correctly to get perepherals fully working. - The probe routine of pinctrl driver is called multiple times, as normally there are multiple GPIO controllers. It should really be called just once. Move the call to syscon_get_by_driver_data() from ich6_gpio driver to cpu_init_r(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com>
* x86: baytrail: acpi: Fix I/O APIC ID in the MADT tableBin Meng2016-05-301-1/+1
| | | | | | | | So far this is hardcoded to 2, but it should really be read from the I/O APIC register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: quark: Generate ACPI FADT/MADT tablesBin Meng2016-05-302-0/+164
| | | | | | | Generate quark platform-specific FADT/MADT tables. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: broadwell: Correct I/O APIC IDBin Meng2016-05-231-1/+2
| | | | | | | | | Currently ID 2 is assgined to broadwell I/O APIC, however per chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change I/O APIC ID to 4 to avoid conflict. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: quark: Assign a unique I/O APIC IDBin Meng2016-05-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | After power-on, both LAPIC and I/O APIC appear with the same APIC ID zero, which creates an ID conflict. When generating MP table, U-Boot reports zero as the LAPIC ID in the processor entry, and zero as the I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment entries. Such MP table confuses Linux kernel and finally a kernel panic is seen during boot: BUG: unable to handle kernel paging request at ffff9000 IP: [<c101d462>] native_io_apic_write+0x22/0x30 *pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000 Oops: 0002 [#1] Modules linked in: Pid: 1, comm: swapper Tainted: G W 3.8.7 #3 intel galileo/galileo EIP: 0060:[<c101d462>] EFLAGS: 00010086 CPU: 0 EIP is at native_io_apic_write+0x22/0x30 ... Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Call lapic_setup() in interrupt_init()Bin Meng2016-05-233-7/+5
| | | | | | | Let's configure LAPIC in a common place - interrupt_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Remove SMP limitation in lapic_setup()Bin Meng2016-05-231-6/+1
| | | | | | | | | At present LAPIC is enabled and configured as virtual wire mode in lapic_setup() only when CONFIG_SMP is on. This limitation is however not necessary as for uniprocessor this is still needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Don't touch IA32_APIC_BASE MSR on Intel QuarkBin Meng2016-05-231-12/+16
| | | | | | | | | | | Intel Quark processor core provides an integrated Local APIC but does not support the IA32_APIC_BASE MSR. As a result, the Local APIC is always globally enabled and the Local APIC base address is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE MSR causes a general protection fault. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Reserve configuration tables in high memoryBin Meng2016-05-231-3/+8
| | | | | | | When SeaBIOS is on, reserve configuration tables in reserve_arch(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Unify reserve_arch() for all x86 boardsBin Meng2016-05-235-27/+12
| | | | | | | | Instead of asking each platform to provide reserve_arch(), supply it in arch/x86/cpu/cpu.c in a unified way. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Fix up PIRQ routing table checksum earlierBin Meng2016-05-231-0/+4
| | | | | | | | | | | | | | | | PIRQ routing table checksum is fixed up in copy_pirq_routing_table(), which is fine if we only write the configuration table once. But with the SeaBIOS case, when we write the table for the second time, the checksum will be fixed up to zero per the checksum algorithm, which is caused by the checksum field not being zero before fix up, since the checksum has already been calculated in the first run. To fix this, move the checksum fixup to create_pirq_routing_table(), so that copy_pirq_routing_table() only does what its function name suggests: copy the table to somewhere else. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Call board_final_cleanup() in last_stage_init()Bin Meng2016-05-232-9/+21
| | | | | | | | | | | At present board_final_cleanup() is called before booting a Linux kernel. This actually needs to be done before booting anything, like SeaBIOS, VxWorks or Windows. Move the call to last_stage_init() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: qemu: rename qemu/acpi_table.cMiao Yan2016-05-232-2/+1
| | | | | | | | Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved to qfw core, this file only contains code for installing e820 table. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: bring ACPI generation code into qfw coreMiao Yan2016-05-231-209/+0
| | | | | | | | Loading ACPI table from QEMU's fw_cfg interface is not x86 specific (ARM64 may also make use of it). So move the code to common place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan2016-05-234-4/+4
| | | | | | | Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: add comment about qfw register endiannessMiao Yan2016-05-231-1/+8
| | | | | | | This patch adds some comments about qfw register endianness for clarity. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: move x86 specific operations out of qfw coreMiao Yan2016-05-231-1/+38
| | | | | | | | | | | The original implementation of qfw includes several x86 specific operations, like directly calling outb/inb and using some inline assembly code which prevents it being ported to other architectures. This patch adds callback functions and moves those to arch/x86/ Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: split qfw command interface and qfw coreMiao Yan2016-05-233-3/+6
| | | | | | | | | | | | This patch splits qfw command interface and qfw core function into two files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core. Now when qfw command interface is enabled, it will automatically select qfw core. This patch also makes the ACPI table generation select CONFIG_QFW. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: remove qemu_fwcfg_free_files()Miao Yan2016-05-231-2/+11
| | | | | | | | | | | This patch is part of the qfw refactor work. The qemu_fwcfg_free_files() function is only used in error handling in ACPI table generation, let's not make this a core function and move it to the right place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: fix ACPI Kconfig optionsMiao Yan2016-05-231-1/+1
| | | | | | | | | | | | | | | CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether to load ACPI table from QEMU's fw_cfg interface. But with commit "697ec431469ce0a4c2fc2c02d8685d907491af84 x86: qemu: Drop our own ACPI implementation", there is only one way to support ACPI table for QEMU targets which is the fw_cfg interface. Having two Kconfig options for this purpose is not necessary any more, so this patch consolidates the two. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: Move qfw command over to cmd and add Kconfig entryTom Rini2016-05-236-574/+248
| | | | | | | | | | - Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into cmd/qemu_fw_cfg.c - Move arch/x86/include/asm/fw_cfg.h to include/qemu_fw_cfg.h - Rename ACPI table portion to arch/x86/cpu/qemu/acpi_table.c Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: baytrail: Generate ACPI FADT/MADT tablesBin Meng2016-05-232-0/+164
| | | | | | | FADT/MADT tables are platform specific. Generate them for BayTrail. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: irq: Enable SCI on IRQ9Bin Meng2016-05-231-0/+22
| | | | | | | | | | By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* x86: irq: Reserve IRQ9 for ACPI in PIC modeBin Meng2016-05-231-0/+5
| | | | | | | | | | Reserve IRQ9 which is to be used as SCI interrupt number for ACPI in PIC mode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Drop asm/acpi.hBin Meng2016-05-233-3/+0
| | | | | | | | | Remove asm/acpi.h which is never used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: Rename disk uclass to ahciSimon Glass2016-05-174-4/+4
| | | | | | | | This started as 'ahci' and was renamed to 'disk' during code review. But it seems that this is too generic. Now that we have a 'blk' uclass, we can use that as the generic piece, and revert to ahci for this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Correct typo of Miao Yan's email addressBin Meng2016-04-221-1/+1
| | | | | | Miao Yan's email address is wrong in fw_cfg.c. Fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: Drop our own ACPI implementationBin Meng2016-04-228-890/+0
| | | | | | | | | | | | Our own ACPI implementation (when CONFIG_QEMU_ACPI_TABLE is not set) does not build anymore after x86 has been fully converted to DM PCI. Instead of trying to fix the build errors, given we now have the ACPI support via QEMU's fw_cfg interface, which is a more reliable way to generate correct ACPI tables than by ourselves, hence drop our own ACPI implementation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: x86: Drop command-line code when CONFIG_CMDLINE is disabledSimon Glass2016-03-221-0/+4
| | | | | | | | Update the link script to drop this code when not needed. This is only done for two architectures at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* x86: Support a chained-boot development flowSimon Glass2016-03-171-0/+80
| | | | | | | | | | | | | | | | | | Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI without any 16-bit init. This can help during development by allowing U-Boot to avoid doing all the init required by the platform. U-Boot expects its GDT to be set up correctly by its 16-bit code. If coreboot doesn't do this (because it hasn't run the payload setup code yet) then this won't happen. In this case we cannot rely on the GDT settings. U-Boot will hang or crash if these are wrong. Provide a development-only option to set up the GDT correctly. This is just a hack so you can jump to U-Boot from any stage of coreboot, not just at the end. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert to use the common SDRAM codeSimon Glass2016-03-171-311/+83
| | | | | | | Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add common SDRAM-init codeSimon Glass2016-03-172-0/+272
| | | | | | | | | The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common PCH code into a common placeSimon Glass2016-03-174-31/+43
| | | | | | | | The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a function to set the IOAPIC IDSimon Glass2016-03-171-0/+16
| | | | | | | Add a function to set the ID in the IOAPIC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add support for high-speed I/O lane with MESimon Glass2016-03-172-0/+58
| | | | | | | | Provide a way to determine the HSIO (high-speed I/O) version supported by the Intel Management Engine (ME) implementation on the platform. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add support for SDRAM setupSimon Glass2016-03-172-0/+308
| | | | | | | | | Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add power-control supportSimon Glass2016-03-172-0/+91
| | | | | | | | | | Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add reference code supportSimon Glass2016-03-172-0/+114
| | | | | | | | Broadwell needs a special binary blob to set up the PCH. Add code to run this on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add an LPC driverSimon Glass2016-03-172-0/+78
| | | | | | | | Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a northbridge driverSimon Glass2016-03-172-0/+60
| | | | | | | | Add a driver for the broadwell northbridge. This sets up the location of several blocks of registers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a SATA driverSimon Glass2016-03-172-0/+270
| | | | | | | | Add a SATA driver for broadwell. This supports connecting an SSD and the usual U-Boot commands to read and write data. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-172-0/+279
| | | | | | | | | | | GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a PCH driverSimon Glass2016-03-173-0/+686
| | | | | | | Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add basic support for broadwellSimon Glass2016-03-174-0/+799
| | | | | | | | This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update microcode for secondary CPUsSimon Glass2016-03-173-2/+7
| | | | | | | | Each CPU needs to have its microcode loaded. Add support for this so that all CPUs will have the same version. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-171-1/+2
| | | | | | | | Enable the microcode feature so that the microcode version is shown with the 'cpu detail' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Record the CPU details when starting each coreSimon Glass2016-03-172-1/+11
| | | | | | | | As each core starts up, record its microcode version and CPU ID so these can be presented with the 'cpu detail' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-171-26/+1
| | | | | | | | At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-176-35/+25
| | | | | | | | | | Some of the Intel ME code is common to several Intel CPUs. Move it into a common location. Add a header file for report_platform.c also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598372/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-172-4/+4
| | | | | | | This same name is used in USB. Add a prefix to distinguish it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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