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| * powerpc/85xx:Make debug exception vector accessiblePrabhakar Kushwaha2012-07-062-6/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR + IVOR15) to have valid and fetchable OP code. 1) While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to fetch an instruction from the debug exception vector (IVPR + IVOR15); since now we are in AS=0, the application needs to ensure the proper TLB configuration to have (IVOR + IVOR15) accessible from AS=0 also. Create a temporary TLB in AS0 to make sure debug exception verctor is accessible on debug exception. 2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/85xx:Fix MSR[DE] bit in MSR to support debuggerPrabhakar Kushwaha2012-07-062-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always. Where MSR = Machine State register Make sure of MSR[DE] bit is set uniformaly across the different execution address space i.e. AS0 and AS1. Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor SupportPrabhakar Kushwaha2012-07-062-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc83xx: fix copyright string in serdes.cTimur Tabi2012-07-031-1/+1
|/ | | | | | | | The misspelling of "semiconductor" causes some internal copyright analysis tools to complain. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC8xxx: Define cache ops for USBMarek Vasut2012-06-076-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch conditionally defines flush_dcache_range() and invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining, resulting in the following output: $ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS Configuring for MPC8572DS board... make: *** [u-boot] Error 1 powerpc-linux-gnu-size: './u-boot': No such file e1000.c: In function ‘e1000_initialize’: e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default] tsec.c: In function ‘tsec_initialize’: tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default] drivers/usb/host/libusb_host.o: In function `ehci_td_buffer': /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range' drivers/usb/host/libusb_host.o: In function `ehci_submit_async': /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range' make: *** [u-boot] Error 1 --------------------- SUMMARY ---------------------------- Boards compiled: 1 Boards with errors: 1 ( MPC8572DS ) ---------------------------------------------------------- Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Anatolij Gustschin <agust@denx.de>
* net: cosmetic: Un-typedef Ethernet_tJoe Hershberger2012-05-231-9/+8
| | | | | | | Separate the Ethernet header from the 802 header. Base the size constants on the structs. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Encapsulate CDP packet identificationJoe Hershberger2012-05-231-1/+1
| | | | | | Checking for CDP packets should be encapsulated, not copied code. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc8260/ether_scc.c: Fix compile warningJoe Hershberger2012-05-221-1/+1
| | | | | | | | Fix this: ether_scc.c: In function 'mpc82xx_scc_enet_initialize': ether_scc.c:377:14: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc85xx/ether_fcc.c: Fix compile warningJoe Hershberger2012-05-221-1/+1
| | | | | | | | Fix this: ether_fcc.c: In function 'fec_initialize': ether_fcc.c:453:15: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc8260/ether_fcc.c: Fix compile warningJoe Hershberger2012-05-221-1/+1
| | | | | | | | Fix this: ether_fcc.c: In function 'fec_initialize': ether_fcc.c:390:15: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc8220/fec.c: Fix compile warningJoe Hershberger2012-05-221-3/+2
| | | | | | | | | | | Fix this: fec.c: In function 'mpc8220_fec_recv': fec.c:791:9: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type include/net.h:438:13: note: expected 'uchar *' but argument is of type 'volatile uchar *' fec.c: In function 'mpc8220_fec_initialize': fec.c:839:12: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* MPC8xx: fix "Remove volatile from net API" aftermathWolfgang Denk2012-05-222-5/+5
| | | | | | | | | | | | | | | | | Commit db288a9 "net: Remove volatile from net API" caused a number of build warnings: fec.c: In function 'fec_initialize': fec.c:183:13: warning: assignment from incompatible pointer type [enabled by default] fec.c: In function 'fec_recv': fec.c:284:5: warning: passing argument 1 of 'NetReceive' discards 'volatile' qualifier from pointer target type [enabled by default] /home/wd/git/u-boot/work/include/net.h:433:13: note: expected 'uchar *' but argument is of type 'volatile uchar *' scc.c: In function 'scc_initialize': scc.c:85:14: warning: assignment from incompatible pointer type [enabled by default] Fix these. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
* powerpc/85xx: fix NAND boot linker scripts for -fpicScott Wood2012-05-182-3/+6
| | | | | | | | GOT is now handled the way the main u-boot.lds does it. Without this, the boot hangs when built with newer GCC (since 4.6). Older toolchains hid the issue by converting -fpic to -fPIC. Signed-off-by: Scott Wood <scottwood@freescale.com>
* powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSRTimur Tabi2012-04-241-2/+6
| | | | | | | The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but that register does not exist on e500v1. Signed-off-by: Timur Tabi <timur@freescale.com>
* powerpc/corenet_ds: Slave core in holdoff when boot from SRIOLiu Gang2012-04-242-0/+128
| | | | | | | | | | | | | | | | | | When boot from SRIO, slave's core can be in holdoff after powered on for some specific requirements. Master can release the slave's core at the right time by SRIO interface. Master needs to: 1. Set outbound SRIO windows in order to configure slave's registers for the core's releasing. 2. Check the SRIO port status when release slave core, if no errors, will implement the process of the slave core's releasing. Slave needs to: 1. Set all the cores in holdoff by RCW. 2. Be powered on before master's boot. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Slave reads ENV from master when boot from SRIOLiu Gang2012-04-241-0/+17
| | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's ENV can be stored in master's memory space, then slave can fetch the ENV through SRIO interface. NOTE: Because the slave can not erase, write master's NOR flash by SRIO interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. Master needs to: 1. Put the slave's ENV into it's own memory space. 2. Set an inbound SRIO window covered slave's ENV stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode and ENV from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Slave uploads ucode when boot from SRIOLiu Gang2012-04-241-4/+21
| | | | | | | | | | | | | | | | | When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman. Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Master module for boot from SRIOLiu Gang2012-04-242-2/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/85xx:Fix lds for nand boot debug infoPrabhakar Kushwaha2012-04-241-2/+2
| | | | | | | | | | | | | | | | | | Currently "u-boot", the elf file generated via u-boot-nand.lds does not contain required debug information i.e. .debug_{line, info, abbrev, aranges, ranges} into their respective _global_ sections. The original ld script line arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg)) is not entirely correct because the start.o file is already processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will not process start.o again for bootpg. So Fix u-boot-nand.lds to generate these debug information. Signed-off-by: Anmol Paralkar <b07584@freescale.com> Signed-off-by: John Russo <John.Russo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Avoid vector table compilation for nand_splPrabhakar Kushwaha2012-04-241-0/+6
| | | | | | | | NAND SPL code never compile the vector table. So no need to setup interrupt vector table for NAND SPL. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Fix IVORs addr after vector table relocationPrabhakar Kushwaha2012-04-241-0/+33
| | | | | | | | | | | After relocation of vector table in SDRAM's lower address, IVORs value should be updated with new handler addresses. As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs are updated with 0x100, 0x200,....f00 hard-coded values. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Avoid hardcoded vector address for IVORsPrabhakar Kushwaha2012-04-241-31/+34
| | | | | | | | | | | | For e500 and e500v2 architecturees processor IVPR address should be alinged on 64K boundary. in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be 64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may not point to an exception handler. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* usb: replace wait_ms() with mdelay()Mike Frysinger2012-03-192-6/+6
| | | | | | | | | | | | | | | | | | | | | | | Common code has a mdelay() func, so use that instead of the usb-specific wait_ms() func. This also fixes the build errors: ohci-hcd.c: In function 'submit_common_msg': /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1519:9: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1816:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1827:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1844:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1563:11: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1583:9: sorry, unimplemented: called from here make[1]: *** [ohci-hcd.o] Error 1 Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Marek Vasut <marex@denx.de>
* powerpc/8xxx:Add MPH controller support in USB device-tree fixupramneek mehresh2012-02-151-10/+19
| | | | | | | | Add support for fixing usb mode and phy type for MPH(Multi Port Host) USB controllers in device-tree nodes. Required for socs like P3060, P5020, etc having MPH USB controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc/8xxx: Cleanup USB device-tree fixupramneek mehresh2012-02-151-6/+12
| | | | | | | | | Some code cleanup done for USB device-tree fixup: - handling error value returned from fdt_fixup_usb_mode_phy_type() - using ARRAY_SIZE macro - using snprintf instead of sprintf Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* fsl_lbc: add printout of LCRR and LBCR to local bus regsPaul Gortmaker2012-01-131-0/+2
| | | | | | | | It can be handy to have these in the output when trying to debug odd behaviour. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sataJerry Huang2011-12-121-1/+10
| | | | | | | | | | | | In the current u-boot code, the value of these fields are the reserved value (0b100), through the signal integrity measurement on freescale's board with these reserved setting, the signal eye is out of the recommended spec for non-transition amplitude at 500mV nominal. According to the errata for MPC8379E, we should make a change to the recommended setting from essentially nothing at this time to 0b001 for SATA. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2011-12-071-6/+3
|\ | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc83xx: powerpc/83xx: fix sdram initialization for keymile boards powerpc/mpc83xx: cleanup makefile for mpc83xx
| * powerpc/mpc83xx: cleanup makefile for mpc83xxYork Sun2011-11-111-6/+3
| | | | | | | | | | | | | | | | Remove symbolic link generated by compiling. Fix makefile for out-of-tree compiling error. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | ppc4xx: Remove usbdev.cStefan Roese2011-12-075-274/+0
| | | | | | | | | | | | | | As this "driver" doesn't seem to be really used, let's remove it completely. Signed-off-by: Stefan Roese <sr@denx.de>
* | arch/powerpc/cpu/mpc86xx/cpu.c: Fix GCC 4.6 build warningWolfgang Denk2011-12-021-3/+0
| | | | | | | | | | | | | | | | | | | | | | Fix: cpu.c: In function 'checkcpu': cpu.c:51:7: warning: variable 'ver' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Kumar Gala <galak@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* | arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warningKumar Gala2011-11-291-2/+1
| | | | | | | | | | | | | | | | | | Fix: interactive.c: In function 'fsl_ddr_interactive': interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc85xx: support board-specific reset functionIra W. Snyder2011-11-291-1/+16
| | | | | | | | | | | | | | | | | | This is useful for boards which cannot be reset in the usual way for the 85xx CPU. An example is a board which can only be reset by a hardware watchdog. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: verify the localbus device tree address before booting the OSTimur Tabi2011-11-291-9/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The localbus controller node in the device tree is typically a root node, even though the controller is part of CCSR. If we were to put the lbc node under the SOC node, then the 'ranges' property in the lbc node would translate through the 'ranges' property of the parent SOC node, and we don't want that. Since the lbc is a separate node, it's possible for the 'reg' property to be wrong. This happened with the original version of p1022ds.dts, which used a 32-bit value in the 'reg' address, instead of a 36-bit address. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc8xxx: update module_type values from JEDEC DDR3 SPD SpecificationIra W. Snyder2011-11-291-0/+7
| | | | | | | | | | | | | | | | | | | | Newer JEDEC DDR3 SPD Specifications define several additional values for the DDR3 module_type field which were undefined when this code was written. Update the code to handle the newer module types. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: clean up and document the QE/FMAN microcode macrosTimur Tabi2011-11-292-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several macros are used to identify and locate the microcode binary image that U-boot needs to upload to the QE or Fman. Both the QE and the Fman use the QE Firmware binary format to package their respective microcode data, which is why the same macros are used for both. A given SOC will only have a QE or an Fman, so this is safe. Unfortunately, the current macro definition and usage has inconsistencies. For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address of NAND. There's no way to know by looking at a variable how it's supposed to be used. In the future, the code which uploads QE firmware and Fman firmware will be merged. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: always implement the work-around for Erratum SATA_A001Timur Tabi2011-11-291-4/+33
| | | | | | | | | | | | | | | | | | | | On the P1022/P1013, the work-around for erratum SATA_A001 was implemented only if U-Boot initializes SATA, but SATA is not initialized by default. So move the work-around to the CPU initialization function, so that it's always executed on the SOCs that need it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Add workaround for erratum A-003474York Sun2011-11-292-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A-003474: Internal DDR calibration circuit is not supported Impact: Experience shows no significant benefit to device operation with auto-calibration enabled versus it disabled. To ensure consistent timing results, Freescale recommends this feature be disabled in future customer products. There should be no impact to parts that are already operating in the field. Workaround: Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following: 1. Write a value of 0x0000_0015 to the register at offset CCSRBAR + DDR OFFSET + 0xf30 2. Write a value of 0x2400_0000 to the register at offset CCSRBAR + DDR OFFSET + 0xf54 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: fixup flexcan device tree clock-frequencyJia Hongtao2011-11-291-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the fixup matchable with dts and kernel. Update the compatible from "fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq" property to "clock-frequency". We also change flexcan frequency from CCB-clock to CCB-clock/2 according to P1010 spec. We now keep the old interfaces to make previous kernel work. They should be removed in the future. Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Add workaround for erratum CPU-A003999Kumar Gala2011-11-293-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc83xx: spd_sdram - fix gcc 4.6 compiler warningKim Phillips2011-11-161-2/+1
| | | | | | | | | | | | | | | | Configuring for sbc8349 board... spd_sdram.c: In function 'spd_sdram': spd_sdram.c:152:41: warning: variable 'trfc_high' set but not used [-Wunused-but-set-variable] Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | iop480_uart.c: Fix GCC 4.6 build warningsStefan Roese2011-11-161-2/+1
| | | | | | | | | | | | | | | | Fix: iop480_uart.c: In function 'serial_init': iop480_uart.c:137:16: warning: variable 'val' set but not used [-Wunused-but-set-variable] Signed-off-by: Stefan Roese <sr@denx.de>
* | 40x_spd_sdram.c: Fix GCC 4.6 build warningsStefan Roese2011-11-161-10/+10
| | | | | | | | | | | | | | | | | | | | Fix: 40x_spd_sdram.c: In function 'spd_sdram': 40x_spd_sdram.c:137:6: warning: variable 'sdram0_b3cr' set but not used [-Wunused-but-set-variable] 40x_spd_sdram.c:136:6: warning: variable 'sdram0_b2cr' set but not used [-Wunused-but-set-variable] 40x_spd_sdram.c:129:6: warning: variable 'sdram0_ecccfg' set but not used [-Wunused-but-set-variable] Signed-off-by: Stefan Roese <sr@denx.de>
* | 44x_spd_ddr2.c: Fix GCC 4.6 build warningsStefan Roese2011-11-161-31/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 44x_spd_ddr2.c: In function 'initdram': 44x_spd_ddr2.c:450:17: warning: variable 'dimm_spd' set but not used [-Wunused-but-set-variable] 44x_spd_ddr2.c: In function 'program_copt1': 44x_spd_ddr2.c:1003:16: warning: variable 'ddrtype' set but not used [-Wunused-but-set-variable] 44x_spd_ddr2.c: In function 'DQS_calibration_process': 44x_spd_ddr2.c:2498:7: warning: variable 'window_found' set but not used [-Wunused-but-set-variable] 44x_spd_ddr2.c:2497:16: warning: variable 'end_rffd' set but not used [-Wunused-but-set-variable] 44x_spd_ddr2.c:2496:16: warning: variable 'end_rqfd' set but not used [-Wunused-but-set-variable] 44x_spd_ddr2.c:2495:16: warning: variable 'begin_rffd' set but not used [-Wunused-but-set-variable] 44x_spd_ddr2.c:2494:16: warning: variable 'begin_rqfd' set but not used [-Wunused-but-set-variable] 44x_spd_ddr2.c:2493:7: warning: variable 'min_end' set but not used [-Wunused-but-set-variable] Signed-off-by: Stefan Roese <sr@denx.de>
* | 44x_spd_ddr.c: Fix GCC 4.6 build warningsStefan Roese2011-11-161-4/+0
| | | | | | | | | | | | | | | | | | Fix: 44x_spd_ddr.c: In function 'program_cfg0': 44x_spd_ddr.c:384:16: warning: variable 'dimm_64bit' set but not used [-Wunused-but-set-variable] 44x_spd_ddr.c:383:16: warning: variable 'dimm_32bit' set but not used [-Wunused-but-set-variable] Signed-off-by: Stefan Roese <sr@denx.de>
* | cmd_ecctest.c: Fix GCC 4.6 build warningsStefan Roese2011-11-161-6/+3
| | | | | | | | | | | | | | | | | | | | Fix: cmd_ecctest.c: In function 'inject_ecc_error': cmd_ecctest.c:116:6: warning: variable 'val' set but not used [-Wunused-but-set-variable] cmd_ecctest.c: In function 'rewrite_ecc_parity': cmd_ecctest.c:154:6: warning: variable 'val' set but not used [-Wunused-but-set-variable] Signed-off-by: Stefan Roese <sr@denx.de>
* | 4xx_ibm_ddr2_autocalib.c: Fix GCC 4.6 build warningsStefan Roese2011-11-161-6/+9
| | | | | | | | | | | | | | | | | | | | Fix: 4xx_ibm_ddr2_autocalib.c: In function 'get_membase': 4xx_ibm_ddr2_autocalib.c:157:8: warning: variable 'bxcf' set but not used [-Wunused-but-set-variable] 4xx_ibm_ddr2_autocalib.c: In function 'DQS_calibration_methodB': 4xx_ibm_ddr2_autocalib.c:722:8: warning: variable 'rffd' set but not used [-Wunused-but-set-variable] Signed-off-by: Stefan Roese <sr@denx.de>
* | 4xx_pcie.c: Fix GCC 4.6 build warningsStefan Roese2011-11-161-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix: 4xx_pcie.c: In function 'pcie_read_config': 4xx_pcie.c:230:6: warning: variable 'address' set but not used [-Wunused-but-set-variable] 4xx_pcie.c: In function 'pcie_write_config': 4xx_pcie.c:290:6: warning: variable 'address' set but not used [-Wunused-but-set-variable] 4xx_pcie.c: In function 'ppc4xx_setup_pcie_rootpoint': 4xx_pcie.c:1066:17: warning: variable 'rmbase' set but not used [-Wunused-but-set-variable] Signed-off-by: Stefan Roese <sr@denx.de>
* | usb_ohci.c: Fix GCC 4.6 build warningsStefan Roese2011-11-161-2/+1
| | | | | | | | | | | | | | | | Fix: usb_ohci.c: In function 'dl_transfer_length': usb_ohci.c:756:8: warning: variable 'tdINFO' set but not used [-Wunused-but-set-variable] Signed-off-by: Stefan Roese <sr@denx.de>
* | arch/powerpc/cpu/mpc512x/i2c.c: Fix GCC 4.6 warningsAnatolij Gustschin2011-11-161-2/+1
| | | | | | | | | | | | | | | | | | Fix: i2c.c: In function 'wait_for_bb': i2c.c:81:16: warning: variable 'temp' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin <agust@denx.de>
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