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* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-03-1023-88/+1158
|\ | | | | | | | | | | | | Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>
| * apalis/colibri_t30: fix MMC/SD card detect GPIOsMarcel Ziswiler2015-03-042-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the MMC/SD card detect GPIOs for Apalis T30 which got broken by the following commit: 2b2b50bc8748 "dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOs" While at it also re-add the comments describing which particular Apalis/Colibri pins those GPIOs are on. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * dm: tegra: dts: add aliases for spi on apalis_t30Marcel Ziswiler2015-03-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | All boards with a SPI interface have a suitable spi alias except Apalis T30. Add these missing aliases just as the following commit did for the others: d2f60f93325a "dm: tegra: dts: Add aliases for spi on tegra30 boards" Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinmux: add Tegra210 supportStephen Warren2015-03-042-0/+611
| | | | | | | | | | | | | | This patch incorporates a few fixes from Tom Warren <twarren@nvidia.com>. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinmux: support Tegra210's e_io_hv pin optionStephen Warren2015-03-042-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra210 has a per-pin option named e_io_hv, which indicates that the pin's input path should be configured to be 3.3v-tolerant. Add support for this. Note that this is very similar to previous chip's rcv_sel option. However, since the Tegra TRM names this option differently for the different chips, we support the new name so that the code exactly matches the naming in the TRM, to avoid confusion. This patch incorporates a few fixes from Tom Warren <twarren@nvidia.com>. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinmux: account for different drivegroup base registersStephen Warren2015-03-045-1/+5
| | | | | | | | | | | | | | | | Tegra210 starts its drive group registers at a different offset from the APB MISC register block that other SoCs. Update the code to handle this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinmux: support hsm/schmitt on pinsStephen Warren2015-03-042-4/+72
| | | | | | | | | | | | | | | | | | T210 support HSM and Schmitt options in the pinmux register (previous chips placed these options in the drive group register). Update the code to handle this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinmux: partially handle varying register layoutsStephen Warren2015-03-041-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Tegra210 moves some bits around in the pinmux registers. Update the code to handle this. This doesn't attempt to address the issues with the group-to-group varying drive group register layout mentioned earlier. This patch handles the SoC-to-SoC differences in the mux register layout. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinmux: move some type definitionsStephen Warren2015-03-042-44/+44
| | | | | | | | | | | | | | | | | | On some future SoCs, some per-drive-group features became per-pin features. Move all type definitions early in the header so they can be enabled irrespective of the setting of TEGRA_PMX_SOC_HAS_DRVGRPS. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinmux: handle feature removal on newer SoCsStephen Warren2015-03-045-0/+45
| | | | | | | | | | | | | | | | On some future SoCs, some of the per-drive-group features no longer exist. Add some ifdefs to support this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinmux: simplify some definesStephen Warren2015-03-045-32/+73
| | | | | | | | | | | | | | | | | | | | Future SoCs have a slightly different combination of pinmux options per pin. This will be simpler to handle if we simply have one define per option, rather than grouping various options together, in combinations that don't align with future chips. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: pinmux: add note re: drive group field definesStephen Warren2015-03-041-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's drive group registers have a remarkably inconsistent layout. The current U-Boot driver doesn't take this into account at all. Add a comment to describe the issue, so at least anyone debugging the driver will be aware of this. To solve this, we'd need to add a per-drive-group data structure describing the layout for the individual register. Since we don't set up too many drive groups in U-Boot at present, this hopefully isn't causing too much practical issue. Still, we probably need to fix this sometime. Wth Tegra210, the register layout becomes almost entirely consistent, so this problem partially solves itself over time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: add function to clear pinmux CLAMPING bitStephen Warren2015-03-042-5/+10
| | | | | | | | | | | | | | | | This is needed to correctly apply the new Jetson TK1 pinmux config. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: support running in non-secure modeStephen Warren2015-03-043-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the CPU is in non-secure (NS) mode (when running U-Boot under a secure monitor), certain actions cannot be taken, since they would need to write to secure-only registers. One example is configuring the ARM architectural timer's CNTFRQ register. We could support this in one of two ways: 1) Compile twice, once for secure mode (in which case anything goes) and once for non-secure mode (in which case certain actions are disabled). This complicates things, since everyone needs to keep track of different U-Boot binaries for different situations. 2) Detect NS mode at run-time, and optionally skip any impossible actions. This has the advantage of a single U-Boot binary working in all cases. (2) is not possible on ARM in general, since there's no architectural way to detect secure-vs-non-secure. However, there is a Tegra-specific way to detect this. This patches uses that feature to detect secure vs. NS mode on Tegra, and uses that to: * Skip the ARM arch timer initialization. * Set/clear an environment variable so that boot scripts can take different action depending on which mode the CPU is in. This might be something like: if CPU is secure: load secure monitor code into RAM. boot secure monitor. secure monitor will restart (a new copy of) U-Boot in NS mode. else: execute normal boot process Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: support large RAM sizesStephen Warren2015-03-041-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some systems have so much RAM that the end of RAM is beyond 4GB. An example would be a Tegra124 system (where RAM starts at 2GB physical) that has more than 2GB of RAM. In this case, we want gd->ram_size to represent the actual RAM size, so that the actual RAM size is passed to the OS. This is useful if the OS implements LPAE, and can actually use the "extra" RAM. However, we can't use get_ram_size() to verify the actual amount of RAM present on such systems, since some of the RAM can't be accesses, which confuses that function. Avoid calling get_ram_size() when the RAM size is too large for it to work correctly. It's never actually needed anyway, since there's no reason for the BCT to report the wrong RAM size. In systems with >=4GB RAM, we still need to clip the reported RAM size since U-Boot uses a 32-bit variable to represent the RAM size in bytes. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: fix variable naming in query_sdram_size()Stephen Warren2015-03-041-8/+9
| | | | | | | | | | | | | | | | | | | | size_mb is used to hold a value that's sometimes KB, sometimes MB, and sometimes bytes. Use separate correctly named variables to avoid confusion here. Also fix indentation of a conditional statement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: HYP/non-sec: relocation before enable secondary coresPeng Fan2015-03-011-1/+8
| | | | | | | | | | | | | | | | | | | | If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined, smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr( _smp_pen), before code is relocated to secure ram. So need relocation to secure ram before enable secondary cores. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
| * edminiv2: switch to SPLAlbert ARIBAUD2015-02-255-2/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ED Mini V2 is based on Orion 5x which boots at fixed address 0xFFFF0000 in NOR Flash. Place SPL there, and switch U-Boot from .bin to .img format, stored in NOR Flash at 0xFFF90000. Note: this patch was tested on HW and works, i.e. it boots U-Boot properly, but SPL console output currently does not appear, due to GD being trashed by arch/arm/lib/spl.c. This trashing is soon to be removed, and then ED Mini V2 SPL console output will become visible. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * edminiv2: fix PCIE IO base address typoAlbert ARIBAUD2015-02-251-1/+1
| | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-02-24391-1782/+4502
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| * | arm: Show relocated PC/LR in the register dumpSimon Glass2015-02-031-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we don't know the relocation address, the raw values are not very useful. Show the pre-relocation values as well as these can be looked up in System.map, etc. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | Errata/ARM57: Add basic constructs to handle and apply A57 specific erratasBhupesh Sharma2015-01-312-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic constructs in the ARMv8 u-boot code to handle and apply Cortex-A57 specific erratas. As and example, the framework showcases how erratas 833069, 826974 and 828024 can be handled and applied. Later on this framework can be extended to include other erratas. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* | | armv8/vexpress64: make multientry conditionalLinus Walleij2015-03-094-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | ARM: PSCI: Rework the DT handler slightlyTom Rini2015-03-094-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way the PSCI DT update happens currently means we pull in <asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in <asm/io.h> for some non-PSCI related things that header needs to deal with. To fix this, we rework the hook slightly. A good portion of arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI is needed on ARMv8 we can re-use this by and large. So rename the current hook to psci_update_dt(), move the prototype to <asm/psci.h> and add an #ifdef that will make re-use later easier. Reported-by: York Sun <yorksun@freescale.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: York Sun <yorksun@freescale.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: York Sun <yorksun@freescale.com>
* | | arm: relocation: clear .bss section with arch memset if definedPrzemyslaw Marczak2015-03-091-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY, will highly increase the memset/memcpy performance. This is able thanks to the ARM multiple register instructions. Unfortunatelly the relocation is done without the cache enabled, so it takes some time, but zeroing the BSS memory takes much more longer, especially for the configs with big static buffers. A quick test confirms, that the boot time improvement after using the arch memcpy for relocation has no significant meaning. The same test confirms that enable the memset for zeroing BSS, reduces the boot time. So this patch enables the arch memset for zeroing the BSS after the relocation process. For ARM boards, this can be enabled in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'. This was tested on Trats2. A quick test with trace. Boot time from start to main_loop() entry: - ~1384ms - before this change - ~888ms - after this change Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
* | | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-03-055-1/+196
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| * | | dt: socfpga: Import and enable Arria V DK DTSMarek Vasut2015-03-043-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
| * | | dt: socfpga: Import and enable Cyclone V DK DTSMarek Vasut2015-03-042-1/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import DTS for Cyclone V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
| * | | arm: socfpga: Add Altera Arria V DK supportMarek Vasut2015-03-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Altera Arria V development kit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-03-051-0/+20
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| * | | | SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.gaurav rana2015-03-051-0/+20
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | omap: gpmc: 'nandecc sw' can use HAM1 or BCH8Ash Charles2015-03-051-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'nandecc sw' command selects a software-based error correction algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their software-based correction algorithm. Allow a user to be specific e.g. # nandecc sw <hamming|bch8> where 'hamming' is still the default. Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set to a hardware-based ECC scheme---a little strange when the user has requested 'sw' ECC. Signed-off-by: Ash Charles <ashcharles@gmail.com>
* | | | Adding Support for BAV335x boardsGilles Gameiro2015-03-051-0/+14
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* | | | omap3: add support for QUIPOS Cairo board.Albert ARIBAUD \(3ADEV\)2015-03-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends OMAP3 support for AM/DM37xx and introduces the AM3703-based Quipos Cairo board. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | arm: pxa: introducing cpuinfo display for marvell pxa270mMarcel Ziswiler2015-03-051-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to table 2-3 on page 87 of Marvell's latest PXA270 Specification Update Rev. I from 2010.04.19 [1] there exists a breed of chips with a new CPU ID for PXA270M A1 stepping which our latest Colibri PXA270 V2.4A modules actually have assembled. This patch helps in correctly identifying those chips upon boot as well which then looks as follows: CPU: Marvell PXA27xM rev. A1 [1] http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf Acked-by: Marek Vasut <marex@denx.de>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-03-0515-2/+224
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| * | | | mx5: fix get_reset_causeStefano Babic2015-03-051-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit d9f43c8f5c1d7ed27c99a06be85a4bb64b2c73fb sets get_reset_cause() as static, but this conflicts with mx5 where its prototype is in sys_proto.h. Drop it from sys_proto.h and drop print_cpuinfo from mx53_loco, factorizing the call for this board. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <jason.hui@linaro.org>
| * | | | imx6: Added DEK blob generator commandRaul Cardenas2015-03-024-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Data Encryption Key(DEK) Blob Protocol which provides a method for protecting a DEK for non-secure memory storage. SEC block protects data in a data structure called a Secret Key Blob, which provides both confidentiality and integrity protection. Every time the blob encapsulation is executed, a AES-256 key is randomly generated to encrypt the DEK. This key is encrypted with the OTP Secret key from SoC. The resulting blob consists of the encrypted AES-256 key, the encrypted DEK, and a 16-bit MAC. During decapsulation, the reverse process is performed to get back the original DEK. A caveat to the blob decapsulation process, is that the DEK is decrypted in secure-memory and can only be read by FSL SEC HW. The DEK is used to decrypt data during encrypted boot. Commands added -------------- dek_blob - encapsulating DEK as a cryptgraphic blob Commands Syntax --------------- dek_blob src dst len Encapsulate and create blob of a len-bits DEK at address src and store the result at address dst. Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com> Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
| * | | | mx35: Fix boot hang by avoiding vector relocationFabio Estevam2015-03-022-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx35 does not boot anymore. Add a specific relocate_vectors macro that skips the vector relocation, as the i.MX35 SoC does not provide RAM at the high vectors address (0xFFFF0000), and (0x00000000) maps to ROM. This allows mx35 to boot again. Cc: Sebastian Priebe <sebastian.priebe@cadcon.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de>
| * | | | mx31: Fix boot hang by avoiding vector relocationFabio Estevam2015-03-022-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx31 does not boot anymore. Add a specific relocate_vectors macro that skips the vector relocation, as the i.MX31 SoC does not provide RAM at the high vectors address (0xFFFF0000), and (0x00000000) maps to ROM. This allows mx31 to boot again. Cc: Anatolij Gustschin <agust@denx.de> Cc: Magnus Lilja <lilja.magnus@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-02348-4702/+1630
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| * | | | | warp: Add initial WaRP Board supportOtavio Salvador2015-02-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The WaRP Board is a Wearable Reference Plaform. The board features: - Freescale i.MX6 SoloLite processor with 512MB of RAM - Freescale FXOS8700CQ 6-axis Xtrinsic sensor - Freescale Kinetis KL16 MCU - Freescale Xtrinsic MMA955xL intelligent motion sensing platform The board implements a hybrid architecture to address the evolving needs of the wearables market. The platform consists of a main board and an example daughtercard with the ability to add additional daughtercards for different usage models. For more information about the project, visit: http://www.warpboard.org/ Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | | | imx: mx6sl: Extend USDHC SD2 pins to support 8-wire useOtavio Salvador2015-02-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DATA[4-7] and RST pin definitions. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * | | | | imx:mx6sl add I2c pad settingsPeng Fan2015-02-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few pad settings are I2C1 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | | | ARM: i.MX: provide access to reset cause through get_imx_reset_cause()Eric Nelson2015-02-172-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | | | | ARM: imx6 Add WDOG3 for i.MX6SXPeng Fan2015-02-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are three wdogs for i.MX 6SoloX. Add wdog3 support in function imx_set_wdog_powerdown. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | | | ARM: imx6: disable bandgap self-bias after bootPeng Fan2015-02-172-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* | | | | | ti: armv7: Move SPL SDRAM init to the right place, drop unused CONFIG_SPL_STACKSimon Glass2015-03-043-9/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently in some cases SDRAM init requires global_data to be available and soon this will not be available prior to board_init_f(). Adjust the code paths in these cases to be correct. In some cases we had the SPL stack be in DDR as we might have large stacks (due to Falcon Mode + Environment). In these cases switch to CONFIG_SPL_STACK_R. In other cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also in SRAM) so drop those lines. Signed-off-by: Simon Glass <sjg@chromium.org> Tested on Beagleboard, Beagleboard xM Tested-by: Matt Porter <mporter@konsulko.com> Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | | | arm: spl: Allow board_init_r() to run with a larger stackSimon Glass2015-03-041-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present SPL uses a single stack, either CONFIG_SPL_STACK or CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and environment) require a lot of stack, some boards set CONFIG_SPL_STACK to point into SDRAM. They then set up SDRAM very early, before board_init_f(), so that the larger stack can be used. This is an abuse of lowlevel_init(). That function should only be used for essential start-up code which cannot be delayed. An example of a valid use is when only part of the SPL code is visible/executable, and the SoC must be set up so that board_init_f() can be reached. It should not be used for SDRAM init, console init, etc. Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new address before board_init_r() is called in SPL. The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README. Signed-off-by: Simon Glass <sjg@chromium.org> For version 1: Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Bo Shen <voice.shen@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
* | | | | | dm: tegra: Enable driver model in SPL and adjust the GPIO driverSimon Glass2015-03-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the full driver model GPIO and serial drivers in SPL now that these are supported. Since device tree is not available they will use platform data. Remove the special SPL GPIO function as it is no longer needed. This is all in one commit to maintain bisectability. Signed-off-by: Simon Glass <sjg@chromium.org>
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