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* Tegra: I2C: Add T114 clock support to tegra_i2c driverTom Warren2013-03-141-0/+6
| | | | | | | | | | | | | T114 has a slightly different I2C clock, with a new (extra) divisor in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C clock is 100KHz +/- 3Hz on my Saleae Logic analyzer. Added a new entry in compat_names for T114 I2C since it differs from the previous Tegra SoCs. A flag is set when T114 I2C HW is found so new features like the extra clock divisor can be used. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
* Tegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to workTom Warren2013-03-141-0/+1
| | | | | | | | | I2C driver can now probe dev 0 (PWR_I2C, where the PMU, etc. lives). This is needed so that the SDIO slot power can be brought up for the MMC driver, so it has to precede those commits. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: usb: move [start|stop]_port into ehci_hcd_[init|stop]Lucas Stach2013-03-141-19/+0
| | | | | | | | | | The ehci_hcd entry points were just calling into the Tegra USB functions. Now that they are in the same file we can just move over the implementation. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: move implementation into right directoryLucas Stach2013-03-145-557/+2
| | | | | | | | | | | | | | | | This moves the Tegra USB implementation into the drivers/usb/host directory. Note that this merges the old /arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code changes, just moving stuff around. v2: While at it also move some defines and the usb.h header file to make usb driver usable for Tegra30. NOTE: A lot more work is required to properly init the PHYs and PLL_U on Tegra30, this is just to make porting easier and it does no harm here. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: various small cleanupsLucas Stach2013-03-142-15/+1
| | | | | | | | | Remove unneeded headers, function prototype and stale comment, that doesn't match the actual codebase anymore. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: move controller init into start_portLucas Stach2013-03-141-28/+29
| | | | | | | | | | | There is no need to init a USB controller before the upper layers indicate that they are actually going to use it. board_usb_init now only parses the device tree and sets up the common pll. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: remove unneeded function parameterLucas Stach2013-03-141-4/+2
| | | | | | | | Just a dead parameter, never actually used. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: make controller init functions more self containedLucas Stach2013-03-141-12/+12
| | | | | | | | | | | | | There is no need to pass around all those parameters. The init functions are able to easily extract all the needed setup info on their own. This allows to move out the controller init into ehci_hcd_init later on, without having to save away global state for later use and thus bloating the file global state. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: set USB_PORTS_MAX to correct valueLucas Stach2013-03-141-1/+1
| | | | | | | | Both Tegra20 and Tegra30 have a max of 3 USB controllers. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Refactor linker-generated arraysAlbert ARIBAUD2013-03-124-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Refactor linker-generated array code so that symbols which were previously linker-generated are now compiler- generated. This causes relocation records of type R_ARM_ABS32 to become R_ARM_RELATIVE, which makes code which uses LGA able to run before relocation as well as after. Note: this affects more than ARM targets, as linker- lists span possibly all target architectures, notably PowerPC. Conflicts: arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds arch/arm/cpu/armv7/omap-common/u-boot-spl.lds board/ait/cam_enc_4xx/u-boot-spl.lds board/davinci/da8xxevm/u-boot-spl-da850evm.lds board/davinci/da8xxevm/u-boot-spl-hawk.lds board/vpac270/u-boot-spl.lds Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: make __bss_start and __bss_end__ compiler-generatedAlbert ARIBAUD2013-03-124-6/+58
| | | | | | | | | | | | | Turn __bss_start and __bss_end__ from linker-generated to compiler-generated symbols, causing relocations for these symbols to change type, from R_ARM_ABS32 to R_ARM_RELATIVE. This should have no functional impact, as it affects references to __bss_start and __bss_end__ only before relocation, and no such references are done. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Remove linker lists (LGAs) from SPL linker scriptsAlbert ARIBAUD2013-03-125-16/+160
| | | | | | | | | | | | Many SPL linker scripts needlessly include linker lists (aka LGAs). Remove them whenever possible; keep it only in the seven am335x_evm variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot), where there is actual content in output section .u_boot_list. This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets byte-identical. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: omap: map u_boot_lists section to .sramAlbert ARIBAUD2013-03-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Output section .u_boot_list was left unmapped in u-boot-spl.lds for omap-common, causing the location counter to roll back to bteween .rodata and .data, making __image_copy_end and _end symbols wrong. Mapping output section .u_boot_list to memory .sram fixes these symbols' mapping. This modifies the SPL binary but has no functional impact, as __image_copy_end and _end are never used in SPLs and u_boot_list is empty for all 29 boards affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3 omap3_beagle am3517_crane igep0032 mt_ventoux pcm051 am3517_evm omap3_evm_quick_mmc am335x_evm_uart2 am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand omap3_overo igep0020 am335x_evm omap4_panda omap5_evm am335x_evm_uart4 devkit8000 tricorder mcx twister omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand). Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-122-21/+15
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| * ARM: sam9x5: fix ethernet pins in MII modeJesse Gilles2013-03-121-8/+8
| | | | | | | | | | | | | | Fix pin setting in MII mode Signed-off-by: Jesse Gilles <jgilles@multitech.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: at91sam9x5: Using CPU string directlyBo Shen2013-03-122-13/+7
| | | | | | | | | | | | | | As the CPU name is not configurable, using CPU string directly Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge u-boot/master into u-boot-ti/masterTom Rini2013-03-112-3/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In master we had already taken a patch to fix the davinci GPIO code for CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these conflicts manually and comment the #else/#endif lines for clarity. Conflicts: arch/arm/include/asm/arch-davinci/gpio.h drivers/gpio/da8xx_gpio.c Signed-off-by: Tom Rini <trini@ti.com>
| * | mac: Fix the condition check for setting the MAC from the EEPROMHolger Hans Peter Freyther2013-02-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue got introduced in a cleanup by Manjunath Hadli in commit 826e99136e2bce61f3f6572e32d7aa724c116e6d. The eth_getenv_enetaddr_by_index method will validate the MAC addr and if none is set in the environment 0 will be returned. Set the MAC from the eeprom if no valid address is found in environment. Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
| * | gpio: Build the da8xx_gpio code for the davinci644x deviceHolger Hans Peter Freyther2013-02-201-1/+7
| |/ | | | | | | | | | | | | The differences include the number of GPIOs and that one is not required to set the pinmux on request. Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
* | arm: dra7xx: Add silicon id support for DRA752 socLokesh Vutla2013-03-114-2/+14
| | | | | | | | | | | | | | | | Adding CPU detection support for the DRA752 ES1.0 soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: Add board files for DRA7XX socsLokesh Vutla2013-03-113-9/+349
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: Add DDR related data for DRA752 ES1.0Lokesh Vutla2013-03-115-6/+42
| | | | | | | | | | | | | | | | | | | | DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: Add control module changesLokesh Vutla2013-03-113-2/+85
| | | | | | | | | | | | | | | | | | | | Control module register addresses are changed from OMAP5 to DRA7XX socs. So adding the necessary changes for the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: clock: Add the dplls dataLokesh Vutla2013-03-114-8/+94
| | | | | | | | | | | | | | | | | | | | | | | | A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: clock: Add the prcm changesLokesh Vutla2013-03-116-8/+252
| | | | | | | | | | | | | | | | PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
* | ARM: OMAP5: srcomp: enable slew rate compensation cells after powerupLokesh Vutla2013-03-117-1/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* | ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCsLokesh Vutla2013-03-114-2/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | Add pre calculated timing settings of LPDDR2 and DDR3 memories present in OMAP5430 and OMAP5432 ES2.0 versions. Also adding the DDR pad io settings required for OMAP543X SOCs here. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* | ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendumSRICHARAN R2013-03-115-189/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* | ARM: OMAP5: clock: Add the prcm register changes required for ES2.0SRICHARAN R2013-03-113-0/+292
| | | | | | | | | | | | | | | | | | | | | | PRCM register addresses are changed from ES1.0 to ES2.0 due to PER power domain getting moved to CORE power domain. So adding the nessecary register changes for the same. Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* | ARM: OMAP5: Add silicon id support for ES2.0 revision.SRICHARAN R2013-03-114-11/+21
| | | | | | | | | | | | | | | | | | Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* | ARM: OMAP5: Clean up iosettings codeLokesh Vutla2013-03-114-44/+78
| | | | | | | | | | | | | | | | | | | | | | There is some code duplication in the ddr io settings code. This is avoided by moving the data to a Soc specific place and letting the code generic. This avoids unnessecary code addition for future socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Make control module register structure genericLokesh Vutla2013-03-1110-191/+259
| | | | | | | | | | | | | | | | | | | | | | | | A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Cleanup emif specific filesLokesh Vutla2013-03-114-85/+108
| | | | | | | | | | | | | | | | | | | | | | | | Removing the duplicated code in ddr3 initialization. Also creating structure for lpddr2 mode registers to avoid unnessecary revision checks. These change reduces code addition for future Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Clean up the pmic codeSRICHARAN R2013-03-1112-260/+198
| | | | | | | | | | | | | | | | | | | | The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Cleanup the clocks layerSRICHARAN R2013-03-1110-895/+869
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Change the PRCM structure prototype common for all SocsSRICHARAN R2013-03-1119-1205/+1312
| | | | | | | | | | | | | | | | | | | | | | | | The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: OMAP4+: emif: Detect SDRAM from SDRAM config registerLokesh Vutla2013-03-115-7/+28
| | | | | | | | | | | | | | | | | | | | | | Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | Allow AM33xx boards to setup GPMC chipselects.Mark Jackson2013-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose the enable_gpmc_cs_config() function so AM33xx based boards can register GPMC chip selects. Changes in V4: - Fix checkpatch errors (TAB -> space mangling) Changes in V3: - Fix line wrapping Changes in V2: - Indicate this is for AM33xx (not OMAP2) Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
* | OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled.Enric Balletbo i Serra2013-03-111-1/+1
| | | | | | | | | | | | In order to use SPL boot from OneNAND we should initialize the gpmc. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* | SPL: ONENAND: Fix some ONENAND related defines.Enric Balletbo i Serra2013-03-085-5/+5
| | | | | | | | | | | | | | | | Some ONENAND related defines use the term ONE_NAND instead of ONENAND, as the technology name is ONENAND this patch replaces all these defines. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* | omap3: allow dynamic selection of gfx_formatNikita Kiryanov2013-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, omap3_dss_panel_config() sets gfx_format to a value that is hardcoded in the code. This forces anyone who wants to use a different gfx_format to make adjustments after calling omap3_dss_panel_config(). This could be avoided if the value of gfx_format were parameterized as input for omap3_dss_panel_config(). Make gfx_format a field in struct panel_config, and update existing structs to set this field to the value that was originally hard coded. Cc: Wolfgang Denk <wd@denx.de> Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* | omap3: add useful dss definesNikita Kiryanov2013-03-081-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | Add useful omap3 dss defines for: polarity, TFT data lines, lcd display type, gfx burst size, and gfx format Cc: Anatolij Gustschin <agust@denx.de> Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* | omap_hsmmc: add driver check for write protectionNikita Kiryanov2013-03-084-7/+8
| | | | | | | | | | | | | | | | Add check for write protection in omap mmc driver. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* | omap_hsmmc: implement driver check for card detectionNikita Kiryanov2013-03-084-7/+7
| | | | | | | | | | | | | | Implement driver check for card detection. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* | omap: consolidate common mmc definitionsNikita Kiryanov2013-03-085-551/+175
| | | | | | | | | | | | | | | | | | The various mmc_host_def.h files are almost identical. Reduce code duplication by moving the similar definitions to a common header file. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* | am33xx: Update DDR3 EMIF configuration sequenceTom Rini2013-03-081-3/+9
| | | | | | | | | | | | | | | | | | | | Based on http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips we need to re-work our sequence in config_sdram slightly to match what the TRM describes as the correct sequence. In our current (incorrect) sequence some edge cases may fail to initalize correctly. Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-02-213-0/+8
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| * | am33xx: support for booting via usbethIlya Yanok2013-02-182-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds BOOT_DEVICE define for USB booting and fixes spl_board_init function to call arch_misc_init (this is the place there musb is initialized). Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * | da8xx: Add the missing pinmux for da830 to the gpio driverTomas Novotny2013-02-181-0/+4
| |/ | | | | | | | | | | | | | | | | The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of kernel version 3.7.5. If the driver is used for the da850, then SoC variant must be specified by CONFIG_SOC_DA850. Signed-off-by: Tomas Novotny <tomas@novotny.cz> Cc: Tom Rini <trini@ti.com>
* | Merge 'u-boot-microblaze/mainline/arm' into 'u-boot-arm/master'Albert ARIBAUD2013-02-215-1/+206
|\ \ | |/ |/| | | | | | | | | | | This pulls the three following ZYNQ commits into ARM master: 7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board 59c651f4: arm: zynq: Add SLCR support with system reset 00ed3458: arm: zynq: Add lowlevel initialization to C
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