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| * armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-172-0/+37
| | | | | | | | | | | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-243-1/+15
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| * | arm: dts: dra7: fix ethernet name with proper device addressMugunthan V N2016-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix typo error for cpsw device name with proper device address Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | arm: dts: dra7: add syscon node to cpsw to read mac addressMugunthan V N2016-05-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add syscon node to cpsw device node to read mac address from efuse. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | arm: dts: am4372: add syscon node to cpsw to read mac addressMugunthan V N2016-05-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add syscon node to cpsw device node to read mac address from efuse. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | ARM: omap5: add platform specific ethernet phy modes configurationsMugunthan V N2016-05-241-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add platforms specific phy mode configuration bits to be used to configure phy mode in control module. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-05-248-45/+150
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| * | | ARM: zynq: Simplify zynq configurationMichal Simek2016-05-241-42/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extending Kconfig for adding new platform is a lot of work for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and remove all dependencies on TARGET_ZYNQ_* options including SPL. As a side-effect it also remove custom init folder for ps7_init_gpl.* files. Folder is chosen based on device-tree file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add SPL support supportMichal Simek2016-05-244-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin <sdcard fat partition> cp atf.ub <sdcard fat partition> cp u-boot.bin <sdcard fat partition> 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin <sdcard> cp u-boot*.img <sdcard> 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSIMichal Simek2016-05-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add missing u-boot,dm-pre-reloc to get IPs initialized. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Align gic ranges for 64k in device treeAlexander Graf2016-05-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Call ps7_post_config() for SPLMichal Simek2016-05-241-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If ps7_post_config() is defined call it. It is enabling for example level shifters for PL bitstreams. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Add support for SPL_LOAD_FITMichal Simek2016-05-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Enable minimal function to be able to compile SPL_LOAD_FIT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-busMasahiro Yamada2016-05-241-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9f56917ab88a ("dm: core: make simple-bus compatible to simple-mfd") made possible to import the following commit: Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1 The SLCR (System-Level Control Registers) block is an MFD (Multi Function Device) rather than a bus. "simple-mfd" seems a more suitable compatible string than "simple-bus". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM: sama5d2: Implement boot device autodetectionMarek Vasut2016-05-244-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for saving ARM register R4 early during boot using save_boot_params . Implement support for decoding the stored register R4 value in spl_boot_device() to obtain boot device from which the SoC booted. This way, the SPL will always load U-Boot from the same device from which the SPL itself booted instead of using hard-coded boot device. This functionality is useful for example when booting sama5d2-xplained from SD card, where by default the SPL would try loading the U-Boot from eMMC and fail. This is because eMMC is on SDHCI0 (BOOT_DEVICE_MMC1), while SD slot is on SDHCI1 (BOOT_DEVICE_MMC2) and the SPL was hard-wired to always boot from BOOT_DEVICE_MMC1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | ARM: at91: clock: complete the GCK's clock sourcesWenyou Yang2016-05-242-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add the UPLL clock and master clock as a clock source for getting the generated clock frequency to complete its clock sources support. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | ARM: at91: clock: fix the GCK's clock sourceWenyou Yang2016-05-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Before enabling a generated clock whose source is from the UPLL clock, check and enable the UPLL clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | board: atmel: add SAMA5D2 PTC Engineering boardWenyou Yang2016-05-241-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board supports following features: - Boot media support: NAND Flash/SPI Flash - Support ethernet - Support USB mass storage Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | ARM: at91: sama5d2: add macro & field definitionsWenyou Yang2016-05-242-0/+29
|/ / | | | | | | | | | | | | They will be used on SAMA5D2 PTC board. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | ARM: fix ifdef in ARMv8 lowlevel_init() againMasahiro Yamada2016-05-231-1/+1
| | | | | | | | | | | | | | | | | | Commit 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()") accidentally inverted the logic of CONFIG_ARMV8_MULTIENTRY. Fixes: 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-05-173-10/+6
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| * | dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSISimon Glass2016-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This option currently enables both the command and the SCSI functionality. Rename the existing option to CONFIG_SCSI since most of the code relates to the feature. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: spi: soft_spi: switch to use linux compatible stringPeng Fan2016-05-171-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Support compatible string "spi-gpio" which is used by Linux Linux use different bindings, so use UBOOT_COMPAT and LINUX_COMPAT to differentiate them. 2. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle no rx or no tx case. 3. Tested on i.MX6 UltraLite board with 74LV595 spi-gpio chip. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | video: tegra: refuse to bind to disabled dcsStephen Warren2016-05-171-4/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This prevents the following boot-time message on any board where only the first DC is in use, yet the DC's DT node is enabled: stdio_add_devices: Video device failed (ret=-22) (This happens on at least Harmony, Ventana, and likely any other Tegra20 board with display enabled other than Seaboard). The Tegra DC's DT node represents a display controller. It may itself drive an integrated RGB display output, or be used by some other display controller such as HDMI. For this reason the DC node itself is not enabled/disabled in DT; the DC itself is considered a shared resource, not the final (board-specific) display output. The node should instantiate a display output driver only if the rgb subnode is enabled. Other output drivers are free to use the DC if they are enabled and their DT node references the DC's DT node. Adapt the Tegra display drivers' bind() routine to only bind to the DC's DT node if the RGB subnode is enabled. Now that the display driver does the right thing, remove the workaround for this issue from Seaboard's DT file. Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | imx: imx-common: print i.MX 7 SoC names consistentlyStefan Agner2016-05-171-1/+1
| | | | | | | | | | | | | | | | | | According to the product website, the full names are i.MX 7Solo and i.MX 7Dual, whereas the short form is i.MX7S and i.MX7D. Be consistent and print the short form for both supported i.MX 7 SoCs. Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* | imx: imx7d: fix ahb clock mux 1Stefan Agner2016-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch>
* | imx: iomux-v3: fix UART input selectsStefan Agner2016-05-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2.
* | imx: mx6: mx6sl_pins: add GPIO variant for SD1_DAT5Eric Nelson2016-05-171-0/+1
|/ | | | | | | This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Peng Fan <van.freenix@gmail.com>
* arm/arm64: Move barrier instructions into separate headerAndre Przywara2016-05-123-21/+46
| | | | | | | | | | | | | | | | Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-05-062-1/+2
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| * socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabledAnatolij Gustschin2016-05-061-1/+1
| | | | | | | | | | | | | | Building without ethernet driver doesn't work. Fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
| * ARM: socfpga: Disable USB OC protection on SoCratesMarek Vasut2016-05-061-0/+1
| | | | | | | | | | | | | | | | This is mandatory, otherwise the USB does not work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
* | imx6: cache: disable L2 before touching Auxiliary Control RegisterPeng Fan2016-05-061-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled by ROM, chaning value of ACR will cause SLVERR and uboot hang. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
* | ARM: am33xx: Fix DDR initialization delaysRuss Dill2016-05-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current delays in the DDR initialization routines for am33xx architectures are sometimes not running long enough leading to DDR init errors. On am437x, this shows up as an L3 NOC error after the kernel boots. This is due to the timer not being initialized properly, but instead still containing the timer init values from the boot ROM which cause timers to expire in 1/4th the time required. timer_init is typically not called until board_init_r, however on am33xx/am43xx udelay is required in sdram_init which is called from board_init_f, so a call to timer_init is required earlier. Note that this issue introduced in v2015.01 by: b352dde "am33xx: Drop timer_init call from s_init". Although this could instead fixed by reverting said commit, it would cause timer_init to be called twice in both SPL and non-SPL cases. This gives a little more fine grained control and also matches what is being done on omap-command and fsl-layerscape. Signed-off-by: Russ Dill <russ.dill@ti.com>
* | ARM: fix ifdefs in ARMv8 lowlevel_init()Stephen Warren2016-05-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 724219a65f55 "ARM: always perform per-CPU GIC init" removed some ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the wrong endif was removed. This patch adds back that missing endif, and adds a new ifdef to match the endif the now-correctly-terminated block used to match against. Use "git show -U25 724219a65f55" to see enough context to make the original issue clear. In practical terms, this makes no difference to runtime behaviour. The code that was incorrectly compiled into the binary when ifndef MULTIENTRY is a no-op for other cases, since branch_if_master evaluates to a hard- coded jump. The only issues were: - A few extra instructions were added to the binary. - The comment on the endif at the very end of the function, indicating which ifdef it matched, were wrong. An alternative might be to simply fix the comment on that trailing ifdef, but that only addresses the second point above, not the first. Fixes: 724219a65f55 ("ARM: always perform per-CPU GIC init") Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Fix various typos, scattered over the code.Robert P. J. Day2016-05-052-2/+2
|/ | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* ARM: tegra: enable GPU node by compatible valueStephen Warren2016-05-043-15/+22
| | | | | | | | | | | | | | | | | | | In current Linux kernel Tegra DT files, 64-bit addresses are represented in unit addresses as a pair of comma-separated 32-bit values. Apparently this is no longer the correct representation for simple busses, and the unit address should be represented as a single 64-bit value. If this is changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no longer be able to find and enable the GPU node, since it looks up the node by name. Fix that function to enable nodes based on their compatible value rather than their node name. This will work no matter what the node name is, i.e for DTs both before and after any rename operation. Cc: Thierry Reding <treding@nvidia.com> Cc: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Change my mailaddressAndreas Bießmann2016-05-023-3/+3
| | | | | | I'll switch my mails to my own server, so drop all gmail references. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arch/arm/imx-common/Makefile: Update u-boot.uim MKIMAGEFLAGSTom Rini2016-05-021-1/+1
| | | | | | We need to be passing -T firmware here and aren't. Signed-off-by: Tom Rini <trini@konsulko.com>
* Revert "rockchip: rk3288: correct sdram setting"Vagrant Cascadian2016-05-021-7/+7
| | | | | | | | | | This reverts commit b5788dc0dd9570e98552833767f4373db965985d. Ram size is incorrectly reported as 512MB on a firefly-rk3288 board with 2GB of ram. Reverting this patch displays the full amount of ram. Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-05-0210-29/+47
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| * ARM: uniphier: move pin-mux code into pin_init functionMasahiro Yamada2016-05-015-27/+5
| | | | | | | | | | | | | | The code in uniphier_sld3_sbc_init() is pin-muxing, so it would be a better fit in uniphier_sld3_early_pin_init(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: allow to use System Bus for ROM boot mode of PH1-LD20Masahiro Yamada2016-05-015-1/+37
| | | | | | | | | | | | | | | | | | The System Bus is not available by default on the ROM boot mode of PH1-LD20. To use devices connected to the System Bus, such as the Micro Support Card, it is necessary to set up pin-muxing and some System Bus Controller register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: enable Peripherl clock to use UART in SPLMasahiro Yamada2016-05-011-0/+4
| | | | | | | | | | | | This is needed to use UART on SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix boot mode table of PH1-LD20Masahiro Yamada2016-05-011-1/+1
| | | | | | | | | | | | | | PH1-LD20 does not have the dedicated boot swap select latch. Instead, it is controlled from the boot mode select. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Revert "omap3: Use raw SPL by default for mmc1"Tom Rini2016-05-021-0/+2
|/ | | | | | | | | | | | | Unfortunately with this change we now are unable to do FS mode boots from MMC1 as with the way the code works today we will always load and assume that the hard-coded raw location contains U-Boot. Further, we cannot fix this by just changing other logic to try FS-then-RAW as it would also make us have to ignore what order the ROM is telling us to try. This reverts commit 22d90d560a2b01c47f180e196e6c6485eb8e65db. Signed-off-by: Tom Rini <trini@konsulko.com>
* sunxi: mctl_mem_matches: Add missing memory barrierHans de Goede2016-04-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | We are running with the caches disabled when mctl_mem_matches gets called, but the cpu's write buffer is still there and can still get in the way, add a memory barrier to fix this. This avoids mctl_mem_matches always returning false in some cases, which was resulting in: U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26) DRAM: 1024 MiB U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology CPU: Allwinner A23 (SUN8I) DRAM: 512 MiB Where 512 MiB is the right amount, but the DRAM controller would be initialized for 1024 MiB. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: DRA7: Add ABB setup for all domainsNishanth Menon2016-04-255-0/+52
| | | | | | | | | | | | | ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: Enable ABB configuration for MM voltage domainNishanth Menon2016-04-255-0/+19
| | | | | | | | | | Since we setup the voltage and frequency for the MM domain, we *must* setup the ABB configuration needed for the domain as well. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structureNishanth Menon2016-04-253-2/+7
| | | | | | | | | | | ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC. Hence, move the txdone mask definition over to structure describing voltage domain. Signed-off-by: Nishanth Menon <nm@ti.com>
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