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* tegra2: Don't use board pointer before it is set upSimon Glass2011-12-091-9/+1
| | | | | | | | | | In board_init_f() the gd->bd pointer is not valid when dram_init() is called. This only avoids dying because DRAM is at zero on Tegra2. The common ARM routine sets up the banks in the same way anyway, so we can just remove this code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra2: Remove unneeded 'dynamic ram size' messageSimon Glass2011-12-091-3/+1
| | | | | | | | | | | | | | | | | | | | | | | This message is not required, since it is followed by an 'official' U-Boot message. U-Boot 2011.03-00048-gd7cb0d3 (May 11 2011 - 17:17:23) TEGRA2 Board: NVIDIA Seaboard dynamic ram_size = 1073741824 DRAM: 1 GiB becomes: TEGRA2 Board: NVIDIA Seaboard DRAM: 1 GiB This is a separate commit since it changes behavior. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra2: Remove unneeded boot codeSimon Glass2011-12-095-147/+1
| | | | | | | | Since we have cache support built in we can remove Tegra's existing cache initialization code amd other related dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: Move CP15 init out of cpu_init_crit()Simon Glass2011-12-092-6/+21
| | | | | | | | | | | | | | | | | | | | Some SOCs have do not start up with their 'main' CPU. The first U-Boot code may then be executed with a CPU which does not have a CP15, or not a useful one. Here we split the initialization of CP15 into a separate call, which can be performed later if required. Once the main CPU is running, you should call cpu_init_cp15() to perform this init as early as possible. Existing ARMv7 boards which define CONFIG_SKIP_LOWLEVEL_INIT should not need to change, this CP15 init is still skipped in that case. The only impact for these boards is that the cpu_init_cp15() will be available even if it is never used on these boards. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra2: Simplify tegra_start() boot pathSimon Glass2011-12-093-25/+37
| | | | | | | | | | | | | | | | | The Tegra2 boot path is more complicated than it needs to be. Since we want to move to building most of U-Boot with ARMv7 and only a small part with ARMv4T (for AVP) it should be as simple as possible. This makes tegra2_start() into a simple function which either does AVP init or A9 init depending on which core is running it. Both cores now following the same init path, beginning at _start, and the special Tegra2 boot path code is no longer required. Only two files need to be built for ARMv4T, and this is handled in the Tegra2 CPU Makefile. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra2: Add arch_cpu_init() to fire up Cortex-A9Simon Glass2011-12-092-0/+21
| | | | | | | | | | | | | We want to move away from a special Tegra2 start-up, and just use arch_cpu_init() instead. However, if we run board_init_f() from boot we need to build it for ARMv4T, since the Tegra's AVP start-up CPU does not support ARMv7. The effect of this is to do the AVP init earlier, and in arch_cpu_init(), rather that board_early_init_f(). Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Fix warnings in arch/arm/cpu/arm920t/s3c24x0/usb_ohci.cSimon Glass2011-12-091-8/+12
| | | | | | | | | | | | | | | | | Sorry if this is already fixed somewhere - I could not find it. This fixes these warnings: usb_ohci.c: In function 'submit_control_msg': usb_ohci.c:1081: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules usb_ohci.c:1081: note: initialized from here usb_ohci.c:1084: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules usb_ohci.c:1084: note: initialized from here usb_ohci.c:1087: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules usb_ohci.c:1087: note: initialized from here Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* arch/arm/include/asm/arch-omap5/clocks.h: Fix GCC 4.2 warningsAnatolij Gustschin2011-12-061-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Fix: clocks.c: In function 'setup_post_dividers': clocks.c:175: warning: comparison is always true due to limited range of data type clocks.c:177: warning: comparison is always true due to limited range of data type clocks.c:179: warning: comparison is always true due to limited range of data type clocks.c:181: warning: comparison is always true due to limited range of data type clocks.c:183: warning: comparison is always true due to limited range of data type clocks.c:185: warning: comparison is always true due to limited range of data type clocks.c:187: warning: comparison is always true due to limited range of data type clocks.c:189: warning: comparison is always true due to limited range of data type Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com>
* arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warningsAnatolij Gustschin2011-12-061-5/+3
| | | | | | | | | | | | | | | | Fix: clocks-common.c: In function 'setup_dplls': clocks-common.c:256:6: warning: variable 'sysclk_ind' set but not used [-Wunused-but-set-variable] clocks-common.c: In function 'setup_non_essential_dplls': clocks-common.c:292:6: warning: variable 'sysclk_ind' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Tom Rini <trini@ti.com>
* arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warningsAnatolij Gustschin2011-12-061-2/+3
| | | | | | | | | | | | | | Fix: spl.c: In function 'jump_to_image_no_args': spl.c:103: warning: assignment makes pointer from integer without a cast spl.c:105: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Tom Rini <trini@ti.com>
* MX: serial_mxc: cleanup removing nasty #ifdefStefano Babic2011-12-066-19/+21
| | | | | | | | | | | | | | | | | | The serial driver for iMX SOCs is continuosly changed if a new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port> defines were used only to find the base address for the selected UART. Instead of that, move the base address to the board configuration file and drop all #ifdef from driver. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Helmut Raiger <helmut.raiger@hale.at> CC: John Rigby <jcrigby@gmail.com> CC: Matthias Weisser <weisserm@arcor.de> CC: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org>
* MXS: Add static annotations to dma driverMarek Vasut2011-12-061-25/+0
| | | | | | | | | | | Some functions were internal to the apbh dma driver, so annotate them static. Some of the functions weren't used at all so drop them. This makes the U-Boot binary smaller by about 1500 bytes. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Correct a warning in clock.cSimon Glass2011-12-061-1/+1
| | | | | | | | | | | | | This corects the warning below, obtained with my gcc 4.6 compiler. arch/arm/cpu/armv7/mx5/libmx5.o: In function `decode_pll': arch/arm/cpu/armv7/mx5/clock.c:94: undefined reference to `__aeabi_uldivmod' I am not able to test this on MX5x hardware, but it does improve the MAKEALL output for me. You may already have a similar patch, but I cannot see it on the list. Signed-off-by: Simon Glass <sjg@chromium.org>
* OMAP3: Add SPL_BOARD_INIT hookTom Rini2011-12-063-0/+13
| | | | | | | | Add an SPL_BOARD_INIT hook and for OMAP3 have it turn on i2c. OMAP4 doesn't need i2c enabled in SPL. Enable SPL_BOARD_INIT on devkit8000. Cc: Frederik Kriewitz <frederik@kriewitz.eu> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Add SPL support to omap3_evmTom Rini2011-12-061-0/+26
| | | | | | | Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. This also changes CONFIG_SYS_TEXT_BASE to 0x80100000. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Add SPL support to BeagleboardTom Rini2011-12-061-0/+29
| | | | | | | | | | | | | | | | | | This introduces 200MHz Micron parts timing information based on x-loader to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to 0x80100000. Cc: Dirk Behme <dirk.behme@gmail.com> Beagleboard rev C5, xM rev A: Tested-by: Tom Rini <trini@ti.com> Beagleboard xM rev C: Tested-by: Matt Ranostay <mranostay@gmail.com> Beagleboard rev B7, C2, xM rev B: Tested-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3 SPL: Add identify_nand_chip functionTom Rini2011-12-063-0/+91
| | | | | | | | | | A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3 SPL: Rework memory initalization and devkit8000 supportTom Rini2011-12-063-39/+17
| | | | | | | | | This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1. Cc: Frederik Kriewitz <frederik@kriewitz.eu> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Suffix all Micron memory timing parts with their speedTom Rini2011-12-061-10/+11
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Add optimal SDRC autorefresh control valuesTom Rini2011-12-061-5/+11
| | | | | | | | This adds the optimal SDRC autorefresh control register values for 100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this to provide the default 165MHz value. Signed-off-by: Tom Rini <trini@ti.com>
* omap3: mem: Add MCFG helper macroTom Rini2011-12-061-16/+30
| | | | | | | | | This adds an MCFG macro to calculate the correct value, similar to the ACTIMA/ACTIMB macros and adds a comment that all of the potential values here are documented in the TRM. Then we convert the Micron value to use this macro. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Remove get_mem_type prototypeTom Rini2011-12-061-1/+0
| | | | | | This function doesn't exist for omap3 Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Change mem_ok to clear again after reading backTom Rini2011-12-061-0/+1
| | | | | | | | It's possible to need to call this function on the same banks multiple times so we want to be sure that 'pos A' is cleared out again at the end. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Add a helper function to set timings in SDRCTom Rini2011-12-061-55/+61
| | | | | | | | Since we go through the sequence to setup the SDRC timings more than once, break this logic out into its own function and have that function call mem_ok() to make sure the memory is usable. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()Tom Rini2011-12-061-12/+11
| | | | | | | | | | | | | We update the comment in make_cs1_contiguous() to be a little bit more clear (it's been copy/pasted from other silicons) and then explain in dram_init() why we need to always try this. Note that in the previous behavior we were always calling this on boards that never had cs1 populated anyhow so making sure we do this always is fine and will correct things like omap3evm detecting an invalid amount of memory (384MB). Signed-off-by: Tom Rini <trini@ti.com>
* omap3: mem: Comment enable_gpmc_cs_config moreTom Rini2011-12-062-3/+13
| | | | | | | Expand the "enable the config" comment to explain what the bit shifts are and define out two of the magic numbers. Signed-off-by: Tom Rini <trini@ti.com>
* arm: printf() is not available in some SPL configurationsChristian Riesch2011-12-061-0/+2
| | | | | | | | | | This patch avoids build breakage for SPLs that do not support printf. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Tom Rini <trini@ti.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, davinci: move misc function in arch treeHeiko Schocher2011-12-062-1/+151
| | | | | | | | | | | | move the board/davinci/common/misc.c file to arch/arm/cpu/arm926ejs/davinci/misc.c, so all davinci boards can use this functions. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <tom.rini@gmail.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Christian Riesch <christian.riesch@omicron.at>
* arm, davinci, da850: add uart1 tx rx pinmux configHeiko Schocher2011-12-062-0/+6
| | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Tom Rini <trini@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <tom.rini@gmail.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Christian Riesch <christian.riesch@omicron.at>
* arm, davinci: move davinci_rtc struct to hardware.hHeiko Schocher2011-12-061-0/+39
| | | | | | | | | move struct davinci_rtc to arch/arm/include/asm/arch-davinci/hardware.h and add RTC_KICK0R_WE, RTC_KICK1R_WE defines, so they are global useable. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com>
* arm, davinci: Remove duplication of pinmux configuration codeChristian Riesch2011-12-061-28/+8
| | | | | | | | | | This patch replaces the pinmux configuration code in arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c by the code from arch/arm/cpu/arm926ejs/davinci/pinmux.c. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* arm, da850: Add pinmux configurations to the arch treeChristian Riesch2011-12-063-0/+217
| | | | | | | | | | | | | Up to now nearly every davinci board has separate code for the definition of pinmux configurations. This patch adds pinmux configurations for the DA850 SoCs to the arch tree which may later be used for all DA850 based boards. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Heiko Schocher <hs@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Acked-by: Heiko Schocher <hs@denx.de>
* arm, davinci: Move pinmux functions from board to arch treeChristian Riesch2011-12-063-1/+108
| | | | | | | | | | | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Heiko Schocher <hs@denx.de> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Syed Mohammed Khasim <sm.khasim@gmail.com> Cc: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Nick Thompson <nick.thompson@ge.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Nick Thompson <nick.thompson@ge.com>
* arm, arm926ejs: always do cpu critical initsHeiko Schocher2011-12-061-4/+2
| | | | | | | | | | | | | always do the cpu critical inits in cpu_init_crit, and only jump to lowlevel_init, if CONFIG_SKIP_LOWLEVEL_INIT is not defined. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <tom.rini@gmail.com> Cc: Christian Riesch <christian.riesch@omicron.at>
* AM3517: move AM3517 specific mux defines to generic headerIlya Yanok2011-12-061-0/+41
| | | | | | | AM3517 specific CONTROL_PADCONF_* defines moved from board-specific files to <asm/arch-omap3/mux.h> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
* AM35xx: add EMAC supportIlya Yanok2011-12-064-0/+104
| | | | | | AM35xx has DaVinci-compatible EMAC. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
* arm926ejs: add noop implementation for dcache opsIlya Yanok2011-12-062-1/+76
| | | | | | | | Added noop implementation for dcache operations that will buzz about missing real implementation and disable the dcache. This fixes compilation of DaVinci EMAC driver on arm926ejs. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
* davinci_emac: move arch-independent defines to separate headerIlya Yanok2011-12-065-289/+4
| | | | | | | | | | | DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs also. This patch moves common defines from arch-davinci/emac_defs.h to drivers/net/davinci_emac.h DaVinci specific PHY drivers hacked to include the new header. We might want to switch to phylib in future. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
* omap4: fix IO settingAneesh V2011-12-061-1/+6
| | | | | | | | | | | | The value from TRIM is not working for some 4430 silicons. So, override with hw team recommended value. However, for 4460 TRIM value shall be used as long as the part is trimmed This fixes boot problem on some OMAP4430 ES2.0 Panda boards out there. Cc: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4460: add ES1.1 identificationAneesh V2011-12-063-1/+12
| | | | Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4: emif: fix error in driverAneesh V2011-12-061-2/+2
| | | | | | | | | | There was a typo in the EMIF driver. It went un-noticed because it affected only when automatic detection is enabled and even then half the memory was configured and identified properly. Reported-by: Rockefeller <rockefeller.lin@innocomm.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* omap: remove I2C from SPLAneesh V2011-12-061-1/+0
| | | | | | | Due to some recent changes I2C is no longer required in SPL. Remove the i2c_init() call to save some space Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4460: fix TPS initializationAneesh V2011-12-061-8/+0
| | | | | | | | | | | TPS power IC is controlled using a GPIO (gpio_wk7). This GPIO should be maintained at logic 1 always. As such an internal pull-up on this pin will do the job, driving the GPIO outuput is not needed. This will avoid the need of using GPIO library in SPL and also may save some power. Signed-off-by: Aneesh V <aneesh@ti.com>
* start.S: remove omap3 specific code from start.SAneesh V2011-12-063-23/+9
| | | | | | | Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Tom Rini <trini@ti.com>
* armv7: setup vectorAneesh V2011-12-061-0/+17
| | | | | | | | The vector is not correctly setup in armv7 except for OMAP3. Correcting this. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: include armv7/cpu.c in SPL buildAneesh V2011-12-061-2/+2
| | | | | | | | | This allows SPL to have default implementation of save_boot_params(), useful for SoCs that do not intend to override this default implementation Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: disable L2 cache in cleanup_before_linux()Aneesh V2011-12-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | We were not disabling external caches before jumping to kernel. We were flushing all caches including external caches and disabling caches globally in CP15 System Control register. Apparently this is not enough. The bootstrap loader in Linux kernel that does decompression enables data-caches again, flush them after use and disable them before jumping to kernel proper. However, it's not aware of the external caches. Since we have left external cache enabled, external cache will get used once caches are enabled globally, but it's not flushed because decompressor is not aware of external caches. When it jumps to kernel with caches disabled globally, we have stale data in the external cache and a coherency problem. This was breaking the boot for OMAP4 with latest mainline kernel. The solution is to disable external caches in cleanup_before_linux(). With this fix kernel is booting again. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* arm, arm926ejs: Fix clear bss loop for zero length bssChristian Riesch2011-12-061-3/+5
| | | | | | | | This patch fixes the clear bss loop for bss sections that have zero length, i.e., where __bss_start == __bss_end__. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* PXA: Rename pxa_dram_init to pxa2xx_dram_initMarek Vasut2011-12-062-3/+3
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Export cpu_is_ and pxa_dram_init functionsMarek Vasut2011-12-061-0/+29
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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