| Commit message (Collapse) | Author | Age | Files | Lines |
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The MT25QL01GB is a 128MB NOR flash chip planned to be used on
a Witherspoon system (AST2500).
Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
Tested-by: Adriana Kobylak <anoo@us.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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This code change adds the AST_SOC_G5 version of ast_get_m_pll_clk(),
which is relevant to AST1520, AST2500, and AST3200 devices.
This change properly enables the AST_SOC_G5 logic in print_cpuinfo(),
which can be turned on by defining CONFIG_DISPLAY_CPUINFO.
Signed-off-by: David Thompson <dthompson@mellanox.com>
Reviewed-by: Shravan Ramani <sramani@mellanox.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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This maintains the existing behaviour of u-boot on ast2500.
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Signed-off-by: Joel Stanley <joel@jms.id.au>
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Signed-off-by: Joel Stanley <joel@jms.id.au>
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The MX66L51235F had a wrong write buffersize of 512 bytes set which
causes issues when trying to write an environment block >256 bytes
as the SPI chip only "listens" to the last 256 bytes.
Signed-off-by: Robert Lippert <rlippert@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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The timestamp and lastdec variables are under BSS which is a problem
as the timer_init() routine is called in the early init phase. Move
them under arch_global_data.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
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Add support to the aspeed flash driver to enable the common mtd layer
through CONFIG_FLASH_CFI_MTD.
This enables the flash to be used by u-boot mtd drivers including
the mtdparts and ubi commands.
Signed-off-by: Adriana Kobylak <anoo@linux.vnet.ibm.com>
Acked-by: Milton Miller <miltonm@us.ibm.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
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This adds defines for WDT2 (and WDT3 for the ast2500), and renames the
existing one to WDT1.
Signed-off-by: Joel Stanley <joel@jms.id.au>
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1.[P1] Add margin check/retry for DDR4 Vref training margin.
2.[P1] Add margin check/retry for DDR3/DDR4 read timing training margin.
3.[P2] Add initial sequence for LPC controller
4.[P2] Add initial full-chip reset option
5.[P3] Add 10ms delay after DDR reset
Signed-off-by: Joel Stanley <joel@jms.id.au>
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This is the latest release from Aspeed.
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Extracted from ast_sdk.v00.03.21 which is based on u-boot v2013.
Signed-off-by: Joel Stanley <joel@jms.id.au>
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