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* tegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL buildAxel Lin2013-05-281-2/+0
| | | | | | | | Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_critAxel Lin2013-05-281-0/+2
| | | | | | | | | cpu_init_crit() can be skipped, but the code is still enabled requiring a platform to supply lowlevel_init(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: support SKU 7 of Tegra20Stephen Warren2013-05-281-0/+1
| | | | | | | | | | Make U-Boot aware of the Tegra20 SKU 7, and treat it identically to any other Tegra20. My Whistler board has a SoC with this SKU. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: support SKU 1 of Tegra114Stephen Warren2013-05-281-0/+1
| | | | | | | | | | | | Make U-Boot aware of the Tegra114 SKU 1, and treat it identically to any other Tegra114. This value is used on (at least some) Dalmore boards with a production rather than engineering chip. Such boards are in the hands of some partners who want to use upstream U-Boot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra: clk: always use find_best_divider() for periph clocksAllen Martin2013-05-281-5/+5
| | | | | | | | | | | | | | | | When adjusting peripheral clocks always use find_best_divider() instead of clk_get_divider() even when a secondary divider is not available. In the case where is requested clock is too slow to be derived from the parent clock this allows a best effort to get close to the requested clock. This comes up for commands like "sf" where the user can pass a clock speed on the command line or "sspi" where the clock is hardcoded to 1MHz, but the Tegra114 SPI controller can't go that low. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: Enable -ffunction-sections / -fdata-sections / --gc-sectionsTom Rini2013-05-231-4/+0
| | | | | | | | | While other architectures have enabled these gcc / ld options for some time on U-Boot itself, ARM has only been doing this on SPL. Enable this on full U-Boot as well now. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@ti.com>
* ARM: atmel: add sama5d3xek supportBo Shen2013-05-216-0/+649
| | | | | | | | | | | | | Add sama5d3xek support with following feature - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector - boot from SPI flash support - boot from SD card support - LCD support - EMAC support - USB OHCI support Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm: at91: enable mci support for at91sam9g20ek.Wu, Josh2013-05-121-0/+4
| | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm: at91: add at91sam9n12ek board supportWu, Josh2013-05-123-2/+180
| | | | | | | | | | | | Add support for following features: - nand boot, with PMECC 2bit ECC for 512 bytes sector - SPI flash boot - SD card boot - LCD support Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix -Wimplicit-function-declaration for at91_lcd_hw_init()] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-1117-91/+234
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| * ARM: OMAP: Add arch_cpu_init functionSRICHARAN R2013-05-101-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | The boot parameters passed from SPL to UBOOT must be saved as a part of uboot's gd data as early as possible, before we will inadvertently overwrite it. So adding a arch_cpu_init for the required Socs to save it. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: OMAP: Cleanup boot parameters usageSRICHARAN R2013-05-103-66/+23
| | | | | | | | | | | | | | | | | | | | | | The boot parameters are read from individual variables assigned for each of them. This been corrected and now they are stored as a part of the global data 'gd' structure. So read them from 'gd' instead. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: OMAP: Correct save_boot_params and replace with 'C' functionSRICHARAN R2013-05-101-6/+44
| | | | | | | | | | | | | | | | | | | | | | Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently. So the current code would not work for a 'XIP' boot. Change this by saving the boot parameters in 'gd' which is always writable. Also add a 'C' function instead of an assembly code that is more readable. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines commonSRICHARAN R2013-05-106-8/+10
| | | | | | | | | | | | | | | | These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * am33xx: Fix warning with CONFIG_DISPLAY_CPUINFOTom Rini2013-05-101-5/+1
| | | | | | | | | | | | | | | | The arm_freq and ddr_freq variables are unused, so remove. Fixup whitespace slightly while in here. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
| * da850: provide davinci_enable_uart0Eric Benard2013-05-101-0/+8
| | | | | | | | | | | | | | | | this is needed to bring UART0 out of reset but this function currently only exists for dm644x/355/365/646x when da850 (at least am1808 also need it). Signed-off-by: Eric Bénard <eric@eukrea.com>
| * ARM: OMAP5: Fix warm reset with USB cable connectedLokesh Vutla2013-05-104-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to workLubomir Popov2013-05-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | USB TLL clocks do not support 'explicit_en', only 'hw_auto' control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be moved to the clk_modules_hw_auto_essential[] array in order to make the clock work. This fix is needed (but not sufficient) for USB EHCI operation in U-Boot. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * arm: omap: emif: Fix DDR3 init after warm resetLokesh Vutla2013-05-101-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EMIF supports a global warm reset mode, during which the EMIF keeps the SDRAM content. But if leveling is enabled at the time of warm reset for DDR3, the following steps needs to be done after warm reset: 1) Keep EMIF in self refresh mode. 2) Reset PHY to bring back the PHY to a known state. 3) Start Levelling procedure. Doing the same. And also enabling DLL lock and code output after warm reset. Tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * OMAP5: I2C: Enable i2c5 clocksLubomir Popov2013-05-101-0/+1
| | | | | | | | | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The i2c5 clock was however not enabled; do this here. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * am33xx: add pll and clock support for TI814x CPSWMatt Porter2013-05-101-2/+101
| | | | | | | | | | | | | | Enables required PLLs and clocks for CPSW on TI814x. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-1116-521/+255
|\ \ | | | | | | | | | | | | | | | Conflicts: drivers/mtd/nand/mxc_nand_spl.c include/configs/m28evk.h
| * | arm: mxs: Add LCDIF clock configuration functionMarek Vasut2013-05-061-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function turns on the LCDIF clock and configures it's frequency. The dividers settings are calculated within the function and the current implementation should be fast and accurate. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * | arm: mxs: Preprocess u-boot.bd so they contain full pathMarek Vasut2013-05-063-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The u-boot-imx23.bd and u-boot-imx28.bd need to be preprocessed, otherwise they have issues with out-of-tree build where elftosb tool couldn't sometimes find the u-boot.bin and spl/u-boot-spl.bin . Preprocess these .bd files with sed and insert full path to u-boot.bin and spl/u-boot-spl.bin to prevent this issue. Moreover, to avoid adding more churn into main Makefile, move all this preprocessing and u-boot.sb generation into CPU directory instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| * | arm: mx23: Fix VDDMEM misconfigurationMarek Vasut2013-05-062-20/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VDDMEM ramped up in very weird way as it was horribly misconfigured. Instead of setting up VDDMEM in one swipe, let it rise slowly the same way as VDDD and VDDA in spl_power_init.c and then only clear ILIMIT before memory gets inited. This makes sure the VDDMEM rises sanely, not jumps up and down as it did till now. The VDDMEM prior to this change did this: 2V0____ .--------2V5 | `--' 0V____| The VDDMEM now does this: 2V0_____,-----------2V5 / 0V__| Moreover, VDDIO on MX23 uses 25mV steps while MX28 uses 50mV steps, fix this difference too. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * | mxs: Explain why some mx23 DDR registers are not configuredFabio Estevam2013-05-061-0/+9
| | | | | | | | | | | | | | | | | | | | | Put an explanation in the source code as to why some DDR registers do not need to be configured. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx23: Operate DDR voltage supply at 2.5VFabio Estevam2013-05-061-2/+2
| | | | | | | | | | | | | | | | | | | | | After the recent fixes in the mx23 DDR setup, it is safe to operate DDR voltage at the recommended 2.5V voltage level again. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | imx: mx5: Remove legacy iomux supportBenoît Thébaudeau2013-05-052-187/+1
| | | | | | | | | | | | | | | | | | | | | | | | Legacy iomux support is no longer needed now that all boards have been converted to iomux-v3. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | imx: mx35: Remove legacy iomux supportBenoît Thébaudeau2013-05-052-115/+0
| | | | | | | | | | | | | | | | | | | | | Legacy iomux support is no longer needed now that all boards have been converted to iomux-v3. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: mx25: Remove legacy iomux supportBenoît Thébaudeau2013-05-051-117/+0
| | | | | | | | | | | | | | | | | | | | | Legacy iomux support is no longer needed now that all boards have been converted to iomux-v3. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | arm: mx5: Add NAND clock handlingMarek Vasut2013-05-051-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Augment the MX5 clock code with function to enable and configure NFC clock. This is necessary to get NFC working on MX5. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
| * | mxs: spl_mem_init: Change EMI port priorityFabio Estevam2013-05-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL as 0x2, which means: PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registersFabio Estevam2013-05-051-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per FSL bootlets code. mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved". HW_DRAM_CTL8 is setup as the last element. So skip the initialization of these DRAM_CTL registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs: spl_mem_init: Remove erroneous DDR settingFabio Estevam2013-05-051-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18. Remove this erroneous setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs: spl_mem_init: Fix comment about start bitFabio Estevam2013-05-051-1/+1
| | | | | | | | | | | | | | | | | | Start bit is part of HW_DRAM_CTL8 register, so fix the comment. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | Add mxc_ocotp driverBenoît Thébaudeau2013-04-281-0/+14
| | | | | | | | | | | | | | | | | | Add an mxc_ocotp driver for i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: Homogenize and fix fuse register definitionsBenoît Thébaudeau2013-04-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mx23: Put back RAM voltage level to its original valueFabio Estevam2013-04-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 5c2f444c9 (mxs: Reset the EMI block on mx23) changed the DDR voltage level, which causes mx23evk to fail to load a kernel. Put back the original values, so that mx23evk can boot a kernel again. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Robert Nelson <robertcnelson@gmail.com>
| * | mx5: Define a common get_board_rev()Fabio Estevam2013-04-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting a FSL kernel based on 2.6.35 it is necessary to pass the revision tag to the kernel. Place a common weak function into soc.c for such purpose. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * | mtd: mxs_nand: Add support for i.MX6Stefan Roese2013-04-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | imx: Move some i.MX common functions into the imx-common directoryStefan Roese2013-04-221-63/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the following functions into the imx-common directory: - mxs_wait_mask_set() - mxs_wait_mask_clr() - mxs_reset_block() These are currently used by i.MX28. But the upcoming GPMI NAND port for i.MX6 will also use these functions. So lets move them to a common location to re-use them. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | imx: Move some header files from arch-mxs to imx-commonStefan Roese2013-04-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following headers are moved to a i.MX common location: - regs-common.h - regs-apbh.h - regs-bch.h - regs-gpmi.h - dma.h This way this header can be re-used also by other i.MX platforms. For example the i.MX6 which will need it for the upcoming NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx6: Add solo-lite variant supportFabio Estevam2013-04-221-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | mx6 solo-lite is another member of the mx6 series. For more information about mx6 solo-lite, please visit: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | Merge branch 'next'Stefano Babic2013-04-211-2/+2
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| | * | mx35 iomux: correct offsets of IOMUX registersPhilip Paeps2013-04-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes mxc_iomux_set_input() work correctly. Previously, the incorrect offset of IOMUXSW_INPUT_CTL caused mxc_iomux_set_input() to write to the wrong register, possibly resulting in unexpected behaviour. Signed-off-by: Philip Paeps <philip@paeps.cx> Acked-by: Stefano Babic <sbabic@denx.de>
* | | | Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-113-15/+1
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| * | | | pxa: Add weak attribute to reset_cpu() functionŁukasz Dałek2013-05-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows pxa2xx based boards to reimplement reset_cpu() function with board specific reset sequence. Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
| * | | | lib: consolidate hang()Andreas Bießmann2013-05-012-14/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Delete all occurrences of hang() and provide a generic function. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> [trini: Modify check around puts() in hang.c slightly] Signed-off-by: Tom Rini <trini@ti.com>
* | | | fpga: zynq: Add support for loading bitstreamMichal Simek2013-05-061-0/+35
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-301-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
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