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* | Use correct spelling of "U-Boot"Bin Meng2016-02-061-1/+1
|/ | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* imx: mx6: implement mmc_get_env_devPeng Fan2016-02-041-0/+32
| | | | | | | | | | Implement mmc_get_env_dev, devno can be got from smbr1 of SRC. Introduce a weak function board_mmc_get_env_dev, different boards can implement it according to different sdhc controllers that used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx7dsabresd: move mmc_get_env_devno to soc codePeng Fan2016-02-041-0/+21
| | | | | | | | | | | Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to match the one in common/env_mmc.c. Introduce a weak function board_mmc_get_env_dev. Different boards can implement this according to sdhc controller which is used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculationYe Li2016-02-021-4/+0
| | | | | | | | | | The checking with max frequency supported is not correct, because the temp is calculated by max pre and post dividers. We can decrease any divider to meet the max frequency limitation. Actually, the calculation below the codes is doing this way to find best pre and post dividers. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6sx: Fix issue in LCDIF clock enablementYe Li2016-02-021-2/+2
| | | | | | | | Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always enter the -EINVAL return. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO boardYe Li2016-02-021-0/+6
| | | | | | | Initial version for mx6sx SABREAUTO board support with features: PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander. Signed-off-by: Ye Li <ye.li@nxp.com>
* mx6: soc: Add ENET2 mac address supportYe Li2016-02-021-9/+23
| | | | | | | The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading MAC address from fuse for ENET2. Signed-off-by: Ye Li <ye.li@nxp.com>
* arm: imx6: Add DDR3 calibration code for MX6 Q/D/DLMarek Vasut2016-02-021-0/+559
| | | | | | | | | Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code fine-tunes the behavior of the MMDC controller in order to improve the signal integrity and memory stability. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* arm: cache: Implement cache range check for v7Marek Vasut2016-01-311-0/+21
| | | | | | | | | | | | | Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-01-281-10/+6
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| * arm: ls102xa: Rewrite the logic of ft_fixup_enet_phy_connect_type()Bin Meng2016-01-281-10/+6
| | | | | | | | | | | | | | | | | | eth_get_dev_by_index() is an API which is not available in driver model. Use eth_get_dev_by_name() instead, which can also simplifly the code logic a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-01-271-5/+5
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| * | arm: ls1021a: Adjust sata register default valuesTang Yuantian2016-01-251-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Updated the default sata register values to enhance the performance and stability. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | sunxi: Add support for LPDDR3 for A83TVishnu Patekar2016-01-261-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T. Mostly the timing parameters are different from DDR3. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi: Groundwork to support new dram type for A83TVishnu Patekar2016-01-261-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different A83T boards have different DRAM types. Banapi M3 has LPDDR3, Allwinner Homlet v1.2 has DDR3. This adds groundwork to support for new DRAM type for A83T. Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must be set in respective board defconfig. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi: Redundant code cleanup from a83t dram initVishnu Patekar2016-01-261-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | This removes the redundant lines of code from mctl_sys_init. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi: Support PSCI ops on Allwinner H3Chen-Yu Tsai2016-01-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | H3 has the same power sequencing procedure as the A31/A31s, which includes the power clamps. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi: Support H3 CCU security switchesChen-Yu Tsai2016-01-262-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H3's CCU includes some switches which disable non-secure access to some of the more critical clock controls, such as MBUS, PLLs, and main platform busses. Configure them to enable non-secure access. For now the only SoC that has this feature is the H3. For other platforms just use a default (weak) empty function so things do not break. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3Chen-Yu Tsai2016-01-263-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure Memory Touch Arbiter is the same thing as the TrustZone Protection Controller found on A31/A31s. Access to many peripherals on the H3 can be controlled by the SMTA, and the settings default to secure access only. This patch supports the new settings, and sets them to allow non-secure access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | imx: mx7: default enable MDIO open drainPeng Fan2016-01-241-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The management data input/output (MDIO) requires open-drain, i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports this feature. So to TO1.1, need to enable open drain by setting bits GPR0[8:7] for TO1.1. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | | imx: mx6ul/sx: fix mmdc_ch0 clk calculationPeng Fan2016-01-241-4/+57
|/ / | | | | | | | | | | | | | | | | | | | | | | | | Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications Processor Reference Manual and "Figure 18-5. BUS clock generation" of i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk sources from pll4_main_clk(pll_audio), the calculation is wrong. Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support for decode_pll. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-01-211-0/+6
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| * | arm: omap-common: do not build timer when CONFIG_TIMER definedMugunthan V N2016-01-201-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To prepare timer driver to DM/DT conversion do not build the exiting timer driver when CONFIG_TIMER is defined. But since omap's SPL doesn't support DM yet so built timer driver only for SPL build when CONFIG_TIMER is defined. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | sunxi: Add support for the I2C controller which is part of the PRCMJelle van der Waa2016-01-212-0/+22
|/ / | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> [hdegoede@redhat.com: Minor cleanups] Signed-off-by: Hans de Goede <hdegoede@redhat.com> applied with fixing 2 checkpatch warnings: WARNING: please, no space before tabs Signed-off-by: Heiko Schocher <hs@denx.de>
* | armv7: Add missing newline after OMAP die IDLadislav Michl2016-01-201-2/+2
|/ | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Enric Balletbo Serra <enric.balletbo@collabora.com>
* am33xx/am43xx: Add platform data for GPIOsTom Rini2016-01-081-0/+23
| | | | | | | | | | | | | On these platforms we have many cases of boards that enable device model and GPIO support but do not enable OF_CONTROL and pass in a device tree with the binary. We need to bring in the platform data here as well. Tested on Beaglebone Black. Reported-by: Robert Nelson <robertcnelson@gmail.com> Reported-by: Francisco Aguerre <franciscoaguerre@gmail.com> Reported-by: Jason Kridner <jkridner@beagleboard.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-01-032-1/+2
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| * imx: ddr: drop duplicated debug infoPeng Fan2016-01-031-1/+0
| | | | | | | | | | | | | | Drop duplicated debug info for tcl. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6: add missing return valueJeroen Hofstee2015-12-071-0/+2
| | | | | | | | | | | | | | cc: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-143-0/+99
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| * | armv7/fsl-ls102xa: Workaround for DDR erratum A008514Yao Yuan2015-12-151-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance. The value: 63b2_0042h comes from the hardware team. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv7: ls102xa: cci-400: Enable snoop and DVM message requests.Yao Yuan2015-12-151-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable snoop and DVM message on all CCI-400 slave ports. Setting on disabled feature (snoop or DVM) is ignored by CCI-400. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> [York Sun: Add commit message] Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: enable all the snoop signal for masters.Yao Yuan2015-12-131-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the IP feature's snoop signal to support hardware snoop for cache coherence. SNPCNFGCR contains the bits to drive snoop signal for various masters. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls1021a: merge SoC specific code in a separate fileYao Yuan2015-12-132-0/+67
| | | | | | | | | | | | | | | | | | | | | Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102x: add get_svr and IS_SVR_REV helperShengzhou Liu2015-12-131-0/+8
| | | | | | | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv7: omap-common: Rework SPL board_mmc_init()Tom Rini2015-12-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the changes in a1e56cf the way that we had board_mmc_init() structured for OMAP parts (so that we always report device 0) are no longer functional. For now, make the case of booting from the second device initialize both devices (we have no devices that only have the second device as MMC). A further rework and consolidation of the functions should be done at a later date. Tested on Beaglebone Black (SD and eMMC boot). Reported-by: Vagrant Cascadian <vagrant@debian.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | | am33xx,ddr3: fix ddr3 sdram configurationEgli, Samuel2015-12-121-1/+10
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the DDR3 initialization procedure in order to comply with DDR3 standard. A 500 us delay is specified between the DDR3 reset and clock enable signal. Until now, this delay was not respected. Some DDR3 chips don't bother but the bigger the RAM becomes the more likely it seems that this delay is needed. We observed that DRAM > 256 MB from the manufacturer Samsung have an issue when the specification is not respected. Changes: 1) Add a 1 ms wait for L3 timeout error trigger 2) Don't delay DDR3 initialization Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his suppresses the initialization of DDR3 Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Reviewed-by: James Doublesin <doublesin@ti.com> Cc: Tom Rini <trini@konsulko.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de>
* | sunxi: Fix H3 DRAM DQ read delay configurationJens Kuske2015-12-101-6/+6
| | | | | | | | | | | | | | | | | | | | | | The read delays were set incorrectly, leading to reliability issues at higher DRAM clock speeds. This commit adjusts this to match the vendor boot0 behaviour. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sun4i: clock: Cleanup some whitespace errorsOlliver Schinagl2015-12-101-3/+3
| | | | | | | | | | | | | | | | Add some spaces around operators. Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: twi: Enable clocks on sun7iOlliver Schinagl2015-12-102-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC but forgot to extend the range check in clock_twi_onoff, resulting in the clock not getting enabled. The range-check is not needed at all, since clock_twi_onoff only gets called with such high indexes when CONFIG_I2C3_ENABLE / CONFIG_I2C4_ENABLE is set and Kconfig already only allows these on sun6i / sun7i. This commit removes the range-check all together fixing i2c bus 4 and 5 not working on sun7i. Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com> [hdegoede@redhat.com] Remove range check instead of extending it Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add support for Allwinner A83T DRAMvishnupatekar2015-12-102-0/+425
| | | | | | | | | | | | | | | | | | | | | | Add support for A83T dram. Register are different from sun8i A33. init code is similar to A33 dram init. hope we'll shift duplicate code in dram_sun8i_* to dram helper in future. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: clk: add basic clocks for A83Tvishnupatekar2015-12-102-0/+140
| | | | | | | | | | | | | | | | | | | | | | Add basic clocks pll1, pll5, and some default values from allwinner u-boot. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz, fixing the mmc support not working [hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to stabilize, fixing cold-booting directly from sdcard not working Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: power: enabled support for axp818vishnupatekar2015-12-102-3/+5
| | | | | | | | | | | | | | | | | | Enabled support for AXP818 in SPL and u-boot. DCDC1, DCDC2, DCDC3 and DCSC5 are enabled. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add support for UART0 in PB pin group on A83Tvishnupatekar2015-12-101-0/+4
| | | | | | | | | | | | | | | | | | | | On A83T, PB9,PB10 are UART0 pins. On allwinner A83T Dev board(h8homlet), this uart0 serial connector is exposed. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add Machine Support for A83T SOCvishnupatekar2015-12-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | Allwinner A83T is octa-core cortex-a7 SOC. This enables support for A83T. SMP is not yet supported. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | am33xx: Update serial pdataTom Rini2015-12-061-11/+7
| | | | | | | | | | | | | | | | We now want to make sure that we have the platform data for NS16550 when we do not have OF_CONTROL set. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-12-042-0/+15
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| * mx6: clock: Modify GPMI clock to support mx6sxYe.Li2015-11-251-0/+12
| | | | | | | | | | | | | | On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li <B37916@freescale.com>
| * cgtqmx6eval: Add SPL supportOtavio Salvador2015-11-251-0/+3
| | | | | | | | | | | | | | | | | | Congatec has several MX6 boards based on quad, dual, dual-lite and solo. Add SPL support so that all the variants can be supported Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-11-302-1/+12
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