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* mx5: lowlevel_init: Remove unused macroFabio Estevam2013-10-311-6/+0
| | | | | | | setup_wdog macro is not used anywhere, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* ARM: mx5: Enable L2 cacheFabio Estevam2013-10-311-0/+6
| | | | | | Enable L2 cache for improving the system performance. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk2013-10-141-22/+22
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-14/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* imx: mx5: lowlevel_init: Simplify codeBenoît Thébaudeau2013-04-121-6/+2
| | | | | | | Don't use several instructions to build constant values. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Mark lowlevel_init board-specific codeBenoît Thébaudeau2012-11-191-1/+1
| | | | | | | | | | | | The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Matt Sealey <matt@genesi-usa.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Add workaround for ARM erratum ID 468414Fabio Estevam2012-10-171-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add the software workaround for ARM erratum ID 468414. According to mx53/mx51 errata document: "ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a subsequent request Description: Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded to a subsequent, unrelated memory request. The conditions are as follows: • Neon loads and stores must be in use • Neon L1 caching must be disabled • Trustzone must be configured and in use • The secure memory address space and the non-secure memory address space both use the same physical addresses, either as an alias or the same memory location or for separate memory locations The issue is reported by ARM, erratum ID 468414, Category 2" Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx5: lowlevel_init.S: Fix PLL settings for mx53Fabio Estevam2012-10-171-33/+63
| | | | | | | | | | | | | | | | | | Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx5: lowlevel_init.S: Split init_clock macroFabio Estevam2012-10-171-30/+65
| | | | | | | | | | | init_clock is currently shared between mx51 and mx53 and it contains lots of ifdef's which makes it really hard to follow the code. Split the init_clock between mx51 and mx53 to allow easier readability. No functional changes are made. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx5: Optimize lowlevel_init code sizeBenoît Thébaudeau2012-10-151-53/+59
| | | | | | | | | | | | | | | Optimize mx5 lowlevel_init.S code size: - Compute values at compile time rather than at runtime where possible. - Assign r4 to hold the zero value rather than setting registers to 0 again and again. - Associate a function to setup_pll rather than expanding its large macro code multiple times. - Allocate constant values in section only if used. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: cosmetic: Clean up lowlevel_initBenoît Thébaudeau2012-09-011-23/+23
| | | | | | | | | | Coding style cleanup: - Remove useless parentheses. - Use tabs for indentations and alignments. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* armv7: add appropriate headers for assembly functionsAneesh V2012-05-151-2/+3
| | | | | | | | Use ENTRY and ENDPROC with assembly functions to ensure necessary assembler directives for all functions. Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* mx53: Make PLL2 to be the parent of UART clockFabio Estevam2012-03-271-3/+17
| | | | | | | | | | | | | | | | | | Change the parent UART clock to be PLL2, so that U-boot can also boot a Freescale 2.6.35 kernel for mx53. FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid conflicts with IPU clocks, so that the video resolution can be changed without affecting the UART clock. On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded and this patch fixes this problem. Tested on a mx53loco board booting a FSL kernel and also a mainline kernel. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* mx53: Turn off child clocks before reconfigure perclk_rootFabio Estevam2011-11-041-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. If these steps aren't followed, GPT timer may stop and the kernel stops at "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Makefile : fix generation of cpu related asm-offsets.hStefano Babic2011-09-071-1/+1
| | | | | | | | | | | commit 0edf8b5b2fa0d210ebc4d6da0fd1aceeb7e44e47 breaks building on a different directory with the O= parameter. The patch wil fix this issue, generating always asm-offsets.h before the other targets. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de> CC: Wolfgang Denk <wd@denx.de>
* ARM: MX51: PLL errata workaroundDavid Jander2011-09-041-0/+38
| | | | | | | | | | | | | This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl>
* ARM: MX5: Fix broken leftover TO-2 errata workaroundDavid Jander2011-07-181-1/+5
| | | | | | | | This check was broken. r3 does not contain the silicon revision anymore, so we need to reload it. Also, this errata only applies to i.MX51. Signed-off-by: David Jander <david@protonic.nl> Acked-by: Stefano Babic <sbabic@denx.de>
* MX5: Add initial support for MX53 processorLiu Hui-R643432011-02-021-37/+54
| | | | | | | | | | Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro Signed-off-by: Jason Liu <r64343@freescale.com>
* MX5: Remove dead code with ENABLE_IMPRECISE_ABORTJason Liu2010-10-191-14/+0
| | | | | | | This code section is dead due to we never define ENABLE_IMPRECISE_ABORT for MX5 Signed-off-by: Jason Liu <r64343@freescale.com>
* MX5: rename mx51 to mx5Jason Liu2010-10-181-0/+291
Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu <r64343@freescale.com>
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