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path: root/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
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* Exynos5: ddr3: Choose between single or double channel configAkshay Saraswat2014-11-171-0/+10
| | | | | | | | | | | | Add a 4G configuration and choose it based on the number of banks declared in config file. A board with 4 SDRAM banks declared (as per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* DMC: Exynos5: Enable update mode for DREX controllerAlim Akhtar2014-11-171-0/+19
| | | | | | | | | | | | | | | | As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: DMC: Add software read levelingAkshay Saraswat2014-06-131-4/+246
| | | | | | | | | | | | | Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* DMC: exynos5420: Gate CLKM to when reading PHY_CON13Doug Anderson2014-06-131-5/+38
| | | | | | | | | | | | | | | | | | when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Remove code for enabling read levelingAkshay Saraswat2014-06-131-71/+0
| | | | | | | | | | | | | | | | This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, so we must disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_initAkshay Saraswat2014-06-131-5/+2
| | | | | | | | | | Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje2013-12-301-10/+429
| | | | | | | | | This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* EXYNOS: Move files from board/samsung to arch/armRajeshwari Shinde2013-07-051-0/+233
This patch performs the following: 1) Convert the assembly code for memory and clock initialization to C code. 2) Move the memory and clock init codes from board/samsung to arch/arm 3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code 4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5. 5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main. 6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250. TEST: Tested SD-MMC boot on SMDK5250 and Origen. Tested USB and SPI boot on SMDK5250 Compile tested for SMDKV310. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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