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path: root/arch/arm/cpu/armv7/exynos/clock.c
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* arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420Ajay Kumar2014-09-051-5/+78
| | | | | | | | | | | Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: exynos: clock: modify the set_mmc_clk for exynos4Jaehoon Chung2014-05-161-5/+11
| | | | | | | | | | | | Modified the mmc_set_clock for eynos4. The goal of this patch is that fsys-div register should be reset. And retore the div-value, not using the value of lowlevel_init. (For using SDMMC4, this patch is needs) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: exynos: clock: Remove exynos4x12_set_mmc_clk functionBeomho Seo2014-05-161-28/+1
| | | | | | | | | | | | | exynos4x12_set_mmc_clk function have been removed. Because, exynos4x12_clock and exynos4_clock return same div_fsys* value. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: clock: use the clear and set bits macros.Inha Song2014-02-101-65/+20
| | | | | | | | | Use setbits/clrbits macro instead of readl/writel function. (Suggested by Wolfgang) Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: clock: fixed that cfg is set to wrong value.Inha Song2014-02-101-0/+3
| | | | | | | | | This patch fixed that cfg value is set to wrong value. Because it didn't read the related register. Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: pinmux: remove unnecessary defineMinkyu Kang2014-02-051-1/+1
| | | | | | The value of PERIPH_ID_COUNT was wrong, and unnecessary. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add clock initialization for 5420Rajeshwari Birje2013-12-301-15/+264
| | | | | | | | | | This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: exynos: fix set_mmc_clk for exynos4x12Jaehoon Chung2013-12-031-1/+2
| | | | | | | | Fix the set_mmc_clk() for exnos4x12. If board is exynos4x12, mmc clock should be set to wrong value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: Added I2S0 clocks for audioDani Krishna Mohan2013-09-241-15/+46
| | | | | | | | This patch makes the necessary changes for making use of I2S0 channel instead of I2S1 channel on smdk board. This changes are done to maintain the uniformity to use I2S0 channel. Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.Łukasz Majewski2013-07-161-5/+4
| | | | | | | | | | | Provide proper setting for the APLL fout frequency calculation for Exynos4 based targets (especially Exynos4210 - Trats board). Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* arm: exynos: fix clock calculationMinkyu Kang2013-07-091-5/+38
| | | | | | | | There are differnce with clock calcuation by cpu variations. This patch will fix it according to user manual. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results.Amar2013-06-131-2/+2
| | | | | | | | | | | | This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk(). Signed-off-by: Amar <amarendra.xt@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5: clock: Update the equation to calculate PLL output frequencyAkshay Saraswat2013-05-211-4/+2
| | | | | | | | | | | | | | According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: pwm: Remove dead code of function exynos5_get_pwm_clkAkshay Saraswat2013-04-011-21/+0
| | | | | | | | | As we shall now be using clock_get_periph_rate function. We find no reason for keeping code in function exynos5_get_pwm_clk. Hence, removing it. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: pwm: Use generic api to get pwm clk freqPadmavathi Venna2013-04-011-1/+1
| | | | | | | | | | | | | Use generic api to get the pwm clock frequency Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: clock: Add generic api to get the clk freqPadmavathi Venna2013-04-011-0/+144
| | | | | | | | | | | | | | | Add generic api to get the frequency of the required peripherial. This API gets the source clock frequency and returns the required frequency by dividing with first and second dividers based on the requirement. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clkJaehoon Chung2013-01-111-0/+5
| | | | | | | | Mobile storage is used the CLK_DIV_FSYS3 value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: clock: support get_mmc_clk for exynosJaehoon Chung2013-01-111-0/+102
| | | | | | | | | To get exactly clock value for mmc, support the get_mmc_clk() like set_mmc_clk(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: Change parent clock of FIMD to MPLLAjay Kumar2013-01-101-1/+1
| | | | | | | | | | | With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequencyChander Kashyap2012-12-261-5/+158
| | | | | | | Adds functions to extract clock frequency of Exynos4x12 IPs. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
*-. Merge samsung, imx, tegra into u-boot-arm/masterAlbert ARIBAUD2012-12-221-0/+17
|\ \ | | | | | | | | | | | | | | | This commit merges branches from samsung, imx and tegra meant to fix merge issues between u-boot/master and u-boot-arm/master, as well as a few manual merge fixes.
| | * Merge remote-tracking branch 'u-boot/master' into u-boot-arm-mergedAllen Martin2012-12-191-0/+16
| | |\ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: README arch/arm/cpu/armv7/exynos/clock.c board/samsung/universal_c210/universal.c drivers/misc/Makefile drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/seaboard.h
| | * exynos:clock: Add i2c clockPiotr Wilczek2012-12-111-0/+17
| |/ | | | | | | | | | | | | | | This patch adds i2c clock for Exynos4 Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Add clock for SPIHatim RV2012-11-151-0/+125
| | | | | | | | | | | | | | | | | | | | | | Add api to calculate and set the clock for SPI channels Signed-off-by: James Miller <jamesmiller@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Add clock for I2SRajeshwari Shinde2012-11-151-0/+121
| | | | | | | | | | | | | | | | | | This patch adds clock support for I2S Signed-off-by: R. Chandrasekar <rcsekar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Clock: Add common function for pll rate calculationMinkyu Kang2012-11-151-64/+38
|/ | | | | | | | Moved the common code to calculate pll clock rate to new function exynos_get_pll_clk(). Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
* EXYNOS5: support exynos5 lcd clock controlDonghwa Lee2012-09-011-1/+107
| | | | | | | | This patch support exynos5 lcd clock control. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: EXYNOS: fixed compiler warning messageJaehoon Chung2012-09-011-0/+3
| | | | | | | | | | | Removed [-Wuninitialized] warning message. The fout_sel is assigned to "-1" by default. And start, gpio_func is initialized to 0. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: Add BPLL supportRajeshwari Shinde2012-09-011-7/+21
| | | | | | | | This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-011-1/+11
| | | | | | | | | | | MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS: CLK: Add i2c clockRajeshwari Shinde2012-07-311-0/+33
| | | | | | | | | This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* EXYNOS: add LCD and MIPI DSI clock interface.Donghwa Lee2012-05-151-0/+184
| | | | | | | | | To sets up lcd and mipi clock in EXYNOS display driver, added clock interface. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: EXYNOS: Add support for Exynos5 based SoCsChander Kashyap2012-02-121-5/+203
| | | | | | | | Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macroChander Kashyap2012-02-121-5/+1
| | | | | | | | | CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: Fix ARM Clock frequency calculationChander Kashyap2012-02-121-6/+9
| | | | | | | | | | Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calculating it as follows: ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1) Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* S5PC2XX: Rename S5pc2XX to exynosChander Kashyap2011-12-091-0/+258
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15 based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15 based SoC's will be sub-classified as Exynos4 and Exynos5 respectively. In order to better adapt and reuse code across various upcoming Samsung Exynos based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix are renamed as exynos4/EXYNOS4. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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