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* gpio: pca953x: Use ARRAY_SIZE instead of reinventing itAxel Lin2013-08-161-4/+1
| | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* tools/Makefile: Move _GNU_SOURCE to MakefileYork Sun2013-08-168-21/+3
| | | | | | | | | | Commit 669dfc2e adds libfdt_env.h to HOSTCPPFLAGS. It causes stdio.h to be included before _GNU_SOURCE is defined in C files. On some old hosts some prototypes are protected by #ifdef __USE_GNU, which is set when _GNU_SOURCE is defined. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* image: Display FIT timestamp when bootingSimon Glass2013-08-161-0/+11
| | | | | | | | | | | | | The timestamp is shown in fit_print_contents() but for some reason not in fit_image_print(). This seems to be an oversight, since it is the latter which is used by bootm. Add timestamp printing in this case. (There is code duplication in these two function, for looking at in a future patch). Signed-off-by: Simon Glass <sjg@chromium.org>
* bootm: fix conditional controlling call to fixup_silent_linuxPaul B. Henson2013-08-161-1/+1
| | | | | | | | | This function is only defined if CONFIG_SILENT_CONSOLE is set and CONFIG_SILENT_U_BOOT_ONLY is not set, the call to it should be based on the same conditions. Signed-off-by: Paul B. Henson <henson@acm.org> Acked-by: Simon Glass <sjg@chromium.org>
* RFC: bootm: Add silent_linux environment variableSimon Glass2013-08-162-2/+18
| | | | | | | | | | At present the console for linux is silent if the U-Boot console is silent, unless CONFIG_SILENT_U_BOOT_ONLY is set. I wonder if a better way would be to have an environment variable to control this? Then we can control the verbosity from scripts, and set the variable to 'no' for those boards that want Linux to boot with console output. Signed-off-by: Simon Glass <sjg@chromium.org>
* SPL: Limit image name print lengthTaras Kondratiuk2013-08-161-2/+3
| | | | | | | | | If image name is longer than 32 bytes, then it will be truncated. This will remove '\0' at the end of the line, so printf will go out of string limit. Signed-off-by: Taras Kondratiuk <taras@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* Enable xmodem supportAngus Ainslie2013-08-161-4/+20
| | | | | | | This is a trivial patch that just enables xmodem downloads using the existing ymodem framework. Signed-off-by: Angus Ainslie <angus@akkea.ca>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-147-73/+188
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| * include/fsl_usb.h: Cleanup license headerYork Sun2013-08-141-17/+1
| | | | | | | | | | | | | | | | Replace license header with SPDX license identifier. Replace GPL-2.0 with GPL-2.0+. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
| * powerpc/c29xpcie: add readme document for c29xpciePo Liu2013-08-141-0/+100
| | | | | | | | Signed-off-by: Po Liu <Po.Liu@freescale.com>
| * powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variablesramneek mehresh2013-08-141-22/+0
| | | | | | | | | | | | | | | | | | Remove getting values of usb mode and phy_type from "usb_dr_mode" and "usb_phy_type" uboot env variables. Now, these are determined only from hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * fsl/usb: Move USB internal phy definitions to fsl_usb.hramneek mehresh2013-08-143-51/+84
| | | | | | | | | | | | | | | | | | fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 & 2Prabhakar Kushwaha2013-08-142-0/+20
| | | | | | | | | | | | | | | | | | | | It is not necessary for all processor to have serdes block 1 & 2. They may have only one serdes block. So, put serdes block 1 & 2 related code under defines Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | tegra: Avoid using I2C prior to relocationSimon Glass2013-08-131-0/+4
| | | | | | | | | | | | | | | | | | Tegra recently moved to the new I2C framework, which sets up I2C prior to relocation, and prior to calling i2c_init_board(). This causes a crash on Tegra boards. Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'dcc' of git://www.denx.de/git/u-boot-microblazeTom Rini2013-08-134-24/+25
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| * serial: arm_dcc: Register with serial coreJagannadha Sutradharudu Teki2013-08-132-6/+29
| | | | | | | | | | | | | | Register arm_dcc with drivers/serial/serial.c Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * serial: arm_dcc: Remove stdio structure supportJagannadha Sutradharudu Teki2013-08-133-22/+0
| | | | | | | | | | | | | | | | | | Removed stdio structure ops support on arm_dcc driver, and need to register with serial core so-that it can access like remianing serial drivers. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-1386-814/+4027
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| * | powerpc/mpc85xx: Cleanup license header in source filesYork Sun2013-08-1221-232/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
| * | 83xx/pcie: fix build error for 83xx pcieRoy Zang2013-08-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build error caused by patch "powerpc/pcie: add PCIe version 3.x support": pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function) pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function) Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]James Yang2013-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but the mask omitted the LSB. This patch provides a 2-bit wide mask. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/c29xpcie: add support for C29XPCIE boardMingkai Hu2013-08-0910-0/+1030
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Singed-off-by: Po Liu <Po.Liu@freescale.com> [yorksun: Fixup include/configs/C29XPCIE.h] Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/85xx: Add C29x SoC supportMingkai Hu2013-08-097-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
| * | powerpc/pcie: remove PCIe version 3.x define for B4860 and B4420Zang Roy-R619112013-08-091-1/+0
| | | | | | | | | | | | | | | | | | B4860 and B4420 has PCIe version 2.4 IP instead of 3.x Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| * | powerpc/pcie: add PCIe version 3.x supportZang Roy-R619112013-08-094-15/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian2013-08-095-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | board/b4860qds: Add support for configuring SerDes1 RefclksShaveta Leekha2013-08-093-2/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add support in B4860 board files for using IDT driver where IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer that generate different refclks for SerDes modules, used this driver for reconfiguring SerDes1 Refclks(based on SerDes1 protocols) for CPRI to work. CPRI works on 122.88MHz and default refclks coming on board are not suitable for it 2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file to b4860qds board file, as SerDes1 Refclk1 would come from PHY MUX in case of certain protocols, that have been checked here. This change would make on board SGMIIs to work 3) Add I2C addresses for IDT8T49N222A devices in board/include file 4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.hShaveta Leekha2013-08-092-1/+1
| | | | | | | | | | | | | | | | | | | | | It allows files not in the same path to use this function as required by B4 board file Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| * | powerpc/mpc85xx: Add defines for serdes RSTCTL registerShaveta Leekha2013-08-091-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| * | board/freescale/common: IDT8T49N222A configuration codeShaveta Leekha2013-08-093-0/+341
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code for configuring IDT8T49N222A device for various output refclks - The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer with alarm and monitoring functions suitable for networking and communications applications. It is able to generate wide range of output frequencies. - In B4860QDS, it has been used to generate different refclks to SerDes modules - Programming of these devices are performed by I2C interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | board/bsc9132qds: Configure DSP DDR controllerPriyanka Jain2013-08-092-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | board/bsc9132qds: Add DSP side tlb and lawsPriyanka Jain2013-08-096-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIELiu Gang2013-08-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF80000; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000", and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so the TLB entry will be from base address 0xffc00000 and with 4M size. Then the u-boot will set TLB entry 14 from base address "CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd00000. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff00000 with 1M size space. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * | p1020rdb-pd: platform supportHaijun.Zhang2013-08-095-14/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB. DDR changed from DDR2 1G to DDR3 2G. NAND: 128 MiB Flash: 64 MiB Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Scott Wood <scottwood@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc85xx: Workaround for A-005812York Sun2013-08-094-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-0916-21/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc8xxx: Add x4 DDR device supportYork Sun2013-08-096-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/t4240qds: Adjust DDR timing for RDIMMYork Sun2013-08-091-10/+9
| | | | | | | | | | | | | | | | | | | | | RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for dual rank. Single- and quad-rank are not tested due to availability. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffffYork Sun2013-08-092-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When chip select interleaving is enabled, cs0_bnds is used for address binding. Other csn_bnds are not used. When two controllers interleaving is enabled, cs0_bnds of both controllers are used, other csn_bnds are not. However, the unused csn_bnds may be used internally for calculating addresses for calibration. Setting those registers to 0 may confuse controllers in some cases. Instead, setting them to 0xffffffff together with normal LAWs will guarantee the address is not mapped to DDR. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/T4240EMU: Add T4240EMU targetYork Sun2013-08-0912-609/+1006
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add emulator support for T4240. Emulator has limited peripherals and interfaces. Difference between emulator and T4240QDS includes: ECC for DDR is disabled due the procedure to load images No board FPGA (QIXIS) NOR flash has 32-bit port for higher loading speed IFC and I2C timing don't really matter, so set them fast No ethernet Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/corenet: Move RCW print to cpu.cYork Sun2013-08-095-62/+22
| | | | | | | | | | | | | | | | | | | | | The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/t4qds: cleanup board header fileYork Sun2013-08-091-68/+0
| | | | | | | | | | | | | | | | | | CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef. Signed-off-by: York Sun <yorksun@freescale.com>
| * | mpc85xx: Base emulator supportYork Sun2013-08-095-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base. Signed-off-by: York Sun <yorksun@freescale.com>
| * | drivers/fm: Fix compiling error if FW location is not definedYork Sun2013-08-091-0/+2
| | | | | | | | | | | | | | | | | | | | | FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even remote. In case none of them is defined, set it to null. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/corenet: Move CONFIG_FSL_CORENET out of board header fileYork Sun2013-08-095-4/+5
| | | | | | | | | | | | | | | | | | | | | Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board specific feature and belongs to SoC header. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/t4: Correct LIODN assignment for SRIOLiu Gang2013-08-092-2/+3
| | | | | | | | | | | | | | | | | | | | | For T4 platform, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * | powerpc/b4860: Correct LIODN assignment for SRIOLiu Gang2013-08-092-2/+3
| | | | | | | | | | | | | | | | | | | | | For B4, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * | powerpc/srio: Update the SRIO LIODN registers and ID table macroLiu Gang2013-08-092-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | powerpc/85xx: Add TWR-P10xx board supportXie Xiaobo2013-08-097-0/+1180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TWR-P1025 Specification: ----------------------- Memory subsystem: 512MB DDR3 (on board DDR) 64Mbyte 16bit NOR flash One microSD Card slot Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC3: Connected to Atheros AR8035 GETH PHY UART: Two UARTs are routed to the FDTI dual USB to RS232 convertor USB: Two USB2.0 Type A ports I2C: AT24C01B 1K Board EEPROM (8 bit address) QUICC Engine: Connected to DP83849i PHY supply two 10/100M ethernet ports QE UART for RS485 or RS232 PCIE: One mini-PCIE slot Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> [yorksun: Fixup include/configs/p1_twr.h] Signed-off-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-mipsTom Rini2013-08-134-150/+160
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