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* SPI: mxc_spi: remove second reset from ECSPI config handlerMarkus Niebel2014-10-271-3/+0
| | | | | | | | | | | | the second reset prevents other registers to be written. This will prevent to have the correct signal levels for SCLK before writing to the config reg in spi_xchg_single. Tested with GPIO based chipselect and SPI_MODE_3 on i.MX6S Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Move the config options to the topMarek Vasut2014-10-271-8/+8
| | | | | | | | | | | | | Just move the configuration options scattered all over the driver to the top of the source file. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Add short note about EPCS/EPCQx1Marek Vasut2014-10-271-0/+6
| | | | | | | | | | | | | | | Add short documentation-alike note on how to use the Altera SPI driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V into doc/SPI/README.altera_spi Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Clean up the use of variable dMarek Vasut2014-10-271-10/+13
| | | | | | | | | | | | | | | | The variable d is used in rather questionable way. Rework the code a bit so it's clearer what it does. Also, rename the variable from d to data to make it's name less mysterious. Finally, change it's data type to uint32_t , since it's accessed as a 32bit number. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Zap endless loopMarek Vasut2014-10-271-2/+11
| | | | | | | | | | | | | | | The driver contained an endless loop when waiting for TX completion, this is a bad idea since if the hardware fails, the loop might spin forever. Add timeout and handle it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Clean up most checkpatch issuesMarek Vasut2014-10-271-10/+13
| | | | | | | | | | | | | | | | | This patch just zaps most of the checkpatch cries present in the driver. There is one more left, which will be addressed separately. There is no functional change. This patch also adds a bunch of newlines all around the place, this is to make the code much more readable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Clean up bit definitionsMarek Vasut2014-10-271-13/+13
| | | | | | | | | | | | | | Clean up the definitions of bits in the Altera SPI driver, there is no need to put braces around numbers afterall. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: altera: Use struct-based register accessMarek Vasut2014-10-271-24/+25
| | | | | | | | | | | | | | | | Zap the offset-based register access and use the struct-based one as this is the preferred method. No functional change, but there are some line-over-80 problems in the driver, which will be addressed later. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2014-10-2719-28/+123
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| * ot1200: add sata supportChristian Gmeiner2014-10-231-0/+5
| | | | | | | | | | | | One of the possible boot devices can be sata. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * ot1200: fix sf detectionChristian Gmeiner2014-10-232-1/+6
| | | | | | | | | | | | | | | | | | | | | | Commit 155fa9af95ac5be857a7327e7a968a296e60d4c8 changed the way to define a GPIO line, which can be used to force CS high across multiple transactions. In order to fix sf detection change board code to make use of board_spi_cs_gpio(..). Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
| * mx6sabre_common: Add HDMI config to common codeFabio Estevam2014-10-213-34/+17
| | | | | | | | | | | | | | HDMI config options can be placed into the common mx6sabre_common.h file to avoid duplication. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6qsabreauto: Add HDMI supportFabio Estevam2014-10-212-1/+76
| | | | | | | | | | | | Let HDMI splash screen support work by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ot1200: remove superfluous "string" tagChristian Gmeiner2014-10-211-5/+0
| | | | | | | | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: i.MX video: declare displays and display_count publiclyEric Nelson2014-10-212-3/+5
| | | | | | | | | | | | | | | | Declare displays[] and display_count in imx-common/video.h to prevent "Should it be static?" messages when compiling board files with "make C=1". Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * ARM: i.MX: provide declaration for board_spi_cs_gpioEric Nelson2014-10-2110-0/+26
| | | | | | | | | | | | | | | | Provide a public declaration of the board_spi_cs_gpio() callback for i.MX SPI chip selects to prevent the warning "Should it be static?" when compiling with "make C=1". Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * ARM: i.MX6: include prototype for get_board_rev()Eric Nelson2014-10-211-0/+1
| | | | | | | | | | | | | | Include <asm/bootm.h> to see the prototype for get_board_rev() and prevent warning "Should it be static?" with "make C=1". Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * ARM: prevent compiler warnings from bootm.cEric Nelson2014-10-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Without preceding declarations, "make C=1" generates "Should it be static?" warnings for symbols do_bootm_linux, boot_prep_vxworks, and boot_jump_vxworks Include of bootm.h also identified a signature mismatch (const on argv[]). Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-10-2779-934/+3468
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| * | omap3/am33xx: mux: fix several checkpatch issuesIgor Grinberg2014-10-2314-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following checkpatch issues: CHECK: No space is necessary after a cast \#39: FILE: arch/arm/include/asm/arch-am33xx/mux.h:39: +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ CHECK: Avoid CamelCase: <CONTROL_PADCONF_JTAG_nTRST> \#284: FILE: arch/arm/include/asm/arch-omap3/mux.h:284: +#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C ERROR: space required after that ',' (ctx:VxV) \#446: FILE: arch/arm/include/asm/arch-omap3/mux.h:446: +#define MUX_VAL(OFFSET,VALUE)\ ^ Cc: Raphael Assenat <raph@8d.com> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Peter Barada <peter.barada@logicpd.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Nishanth Menon <nm@ti.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Stefan Roese <sr@denx.de>
| * | omap3: cm-t35: remove enable_gpmc_cs_config()Igor Grinberg2014-10-231-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpmc_init() function already calls enable_gpmc_cs_config() for chip select 0. Although the bus width is configured for 16 bit, it gets reconfigured correctly in the omap_gpmc driver later. Remove the enable_gpmc_cs_config() function call and the associated gpmc_nand_config[] array. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
| * | omap3: cm-t35: use define for mmc wp gpioIgor Grinberg2014-10-231-1/+3
| | | | | | | | | | | | | | | | | | Switch to using define for MMC WP GPIO instead of a magic number. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
| * | omap3: Kconfig: fix the cm-t35 board option promptIgor Grinberg2014-10-231-1/+1
| | | | | | | | | | | | | | | | | | | | | The cm-t35 board support covers both cm-t3530 and cm-t3730 boards. Mention both boards in the Kconfig option prompt. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
| * | am335x_evm: Correct "raw" portions of DFU alt intoTom Rini2014-10-231-5/+5
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | am335x_boneblack: Only modify NAND/NOR/MMC1 pinmux on BBB in boneblack builds.Tom Rini2014-10-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of Beaglebone Black we only want to set the NAND or NOR cape pinmux when the config has been specifically modified by the user for this non-default case. Make the default be to set the MMC1 (eMMC) pinmux. We don't need similar changes for Beaglebone White as there is nothing on MMC1 by default there. Signed-off-by: Tom Rini <trini@ti.com>
| * | arm: am43xx: switch over to CONFIG_ENV_IS_IN_FATFelipe Balbi2014-10-231-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | By using CONFIG_ENV_IS_IN_FAT it's far easier to have a private, minimal environment for e.g. booting off of network or mounting rootfs on NFS without having to modify the configuration header. Signed-off-by: Felipe Balbi <balbi@ti.com>
| * | common: Makefile: allow for spl builds with env_fatFelipe Balbi2014-10-231-0/+1
| | | | | | | | | | | | | | | | | | | | | If CONFIG_SPL_BUILD and CONFIG_ENV_IS_IN_FAT are defined, u-boot spl will fail to build. Fix that. Signed-off-by: Felipe Balbi <balbi@ti.com>
| * | omap3: overo: Add usb host supportStefan Herbrechtsmeier2014-10-232-0/+42
| | | | | | | | | | | | Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
| * | omap3: overo: Separate module and expansion board MUX configurationStefan Herbrechtsmeier2014-10-232-75/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | Separate overo module and expansion board MUX configuration. This allows an foreign expansion board to use the boot loader without any adaption. It only needs to save the expansion name in the EEPROM to load a specific device tree. Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
| * | omap3: overo: Move ethernet setup to board_eth_init functionStefan Herbrechtsmeier2014-10-231-29/+47
| | | | | | | | | | | | | | | | | | | | | Move ethernet setup to the board_eth_init function and select the available network devices via expansion id. Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
| * | omap3: overo: Call bootm only after successful nand readStefan Herbrechtsmeier2014-10-231-2/+3
| | | | | | | | | | | | Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
| * | ARM: keystone: cmd_ddr3: add ddr3 commands to test ddrHao Zhang2014-10-233-5/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ddr3 commands: test <start_addr in hex> <end_addr in hex> - test DDR from start\n address to end address\n ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n compare DDR data of (size) bytes from start address to end address\n ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n in DDR data at <addr>, the command will read a 32-bit data\n from <addr>, and write (data ^ bit_err) back to <addr>\n Delete CONFIG_MAX_UBOOT_MEM_SIZE, as it was supposed to be used for ddr3 commands and for now it's not needed any more. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | keystone2: ecc: add ddr3 error detection and correction supportVitaly Andrianov2014-10-236-0/+319
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the DDR3 ECC support to enable ECC in the DDR3 EMIF controller for Keystone II devices. By default, ECC will only be enabled if RMW is supported in the DDR EMIF controller. The entire DDR memory will be scrubbed to zero using an EDMA channel after ECC is enabled and before u-boot is re-located to DDR memory. An ecc_test environment variable is added for ECC testing. If ecc_test is set to 0, a detection of 2-bit error will reset the device, if ecc_test is set to 1, 2-bit error detection will not reset the device, user can still boot the kernel to check the ECC error handling in kernel. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | ARM: keystone: msmc: extend functionality of SESVitaly Andrianov2014-10-233-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add functions to set/get SES PMAX values of Pivilege ID pair. Also add msmc module definitions. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | dma: ti-edma3: introduce edma3 driverKhoronzhuk, Ivan2014-10-233-0/+506
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EDMA3 controller’s primary purpose is to service data transfers that you program between two memory-mapped slave endpoints on the device. Typical usage includes, but is not limited to the following: - Servicing software-driven paging transfers (e.g., transfers from external memory, such as SDRAM to internal device memory, such as DSP L2 SRAM) - Servicing event-driven peripherals, such as a serial port - Performing sorting or sub-frame extraction of various data structures - Offloading data transfers from the main device DSP(s) - See the device-specific data manual for specific peripherals that are accessible via the EDMA3 controller Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | board: k2e_evm: add network supportHao Zhang2014-10-232-1/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds network support code and enables keystone_net driver usage for k2e_evm evaluation board. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | ARM: keystone: clock: add support for K2E SoCsKhoronzhuk, Ivan2014-10-233-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | For K2E and K2L SoCs clock output from PASS PLL has to be enabled after NETCP domain and PA module are enabled. So create new function for that and call it after PA module is enabled. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: increase PHY auto negotiate timeKhoronzhuk, Ivan2014-10-231-5/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new Marvel PHY (88E1514) used on K2L/K2E EVM requires longer time to auto negotiate with SoC's SGMII port. It can take about 3 sec to up the PHY after reset, so add code to expose sgmii auto negotiation waiting process. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: add Keystone2 K2E SoC supportKhoronzhuk, Ivan2014-10-232-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Keystone2 Edison SoC uses the same keystone net driver. This patch adds opportunity to use it by K2E SoCs. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_serdes: add keystone K2E SoC supportKhoronzhuk, Ivan2014-10-234-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Keystone2 Edison SoC uses the same keystone SerDes driver. This patch adds support for K2E SoCs. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | ARM: keystone2: keysonte_nav: add support for K2E SoCKhoronzhuk, Ivan2014-10-231-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keystone2 Edison SoC uses the same keystone navigator, but uses different NETCP PktDMA definitions. This patch adds required definitions. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: use general get link functionKhoronzhuk, Ivan2014-10-232-46/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phy framework has function to get link, so use it instead of own implementation. There is no reason to check SGMII link while sending each packet, phy link is enough. Check SGMII link only while ethernet open. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: register eth PHYs on MDIO busKhoronzhuk, Ivan2014-10-233-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As MDIO bus has been added we can register PHYs with it. After registration, the PHY driver will be probed according to the hardware on board. Startup PHY at the ethernet open. Use phy_startup() instead of keystone_get_link_status() when eth open, as it verifies PHY link inside and SGMII link is checked before. For K2HK evm PHY configuration at init was absent, so don't enable phy config at init for k2hk evm. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: register MDIO busKhoronzhuk, Ivan2014-10-231-38/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently MDIO framework is not used to configure Ethernet PHY. As result some of already implemented functions are duplicated. So register MDIO bus in order to use it. On that stage it's just registered, it'll be used as we start to use PHY framework. Use mdio bus read/write/reset functions in the driver. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: keystone_net: use mdio_reset functionKhoronzhuk, Ivan2014-10-231-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | Don't use mdio_enable twice while eth open. Also rename it to keystone2_mdio_reset as more appropriate name. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | net: phy: print a number of phy that is not foundKhoronzhuk, Ivan2014-10-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In case when several Ethernet ports are supported it's convenient to see the number of phy that is not found. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | soc: keystone_serdes: generalize configuration mechanismKhoronzhuk, Ivan2014-10-231-47/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cmu, comlane, lane configuration mechanism are similar for sub systems as well such as PCI or sRIO, but they have different values based on input clock and output bus rate. According to this compact driver to simplify adding different configuration settings based on clock and rate. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | soc: keystone_serdes: generalize to be used by other sub systemsHao Zhang2014-10-234-42/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes driver is used by other sub systems like PCI, sRIO etc. So modify it to be more general. The SerDes driver provides common API's that can also be extended for other peripherals SerDes configurations. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurationsHao Zhang2014-10-234-82/+94
| | | | | | | | | | | | | | | | | | | | | | | | Enhance the driver to use cmu/comlane/lane specific configurations instead of 1 big array of configuration. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | soc: keystone_serdes: create a separate SGMII SerDes driverKhoronzhuk, Ivan2014-10-237-138/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch split the Keystone II SGMII SerDes related code from Ethernet driver and create a separate SGMII SerDes driver. The SerDes driver can be used by others keystone subsystems like PCI, sRIO, so move it to driver/soc/keystone directory. Add soc specific drivers directory like in the Linux kernel. It is going to be used by keysotone soc specific drivers. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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