| Commit message (Collapse) | Author | Age | Files | Lines |
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Tegra124's MMC controller is very similar to earlier SoC generations,
and can be supported by the same driver.
However, there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW. This
patch updates the driver to support that new compatible value.
That said, the HW differences are only relevant when enabling certain
high-performance transfer modes. Since the driver is currently very
simple and doesn't enable those modes, we don't actually need to address
any of these HW differences in the code yet, hence the simple nature of
this patch.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Based on the Tegra TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.
The fix is to set the system clock to CLK_M before initializing PLLP,
and then switch back to PLLP_OUT4, which has an appropriate divider
configured, after PLLP has been configured
Implement this logic in new function tegra30_set_up_pllp(),
which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP
clock switching. Remove the duplicate PLLP setup from pllx_set_rate()
and adjust_pllp_out_freqs().
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
[swarren, significantly refactored the change]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.
The cpu.c change in this patch was extracted from a much larger patch
by Jimmy Zhang. The pmc.h change was written from scratch, but inspired
by related changes made by Tom Warren.
There could well be other differences in the PMC register set for chips
after Tegra20/30. However, they don't affect the code in U-Boot at
present, so I haven't attempted an exhaustive update of pmc.h.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Some clock sources have 3-bit muxes in bits 31:29. Implement core
support for this mux field.
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Since all code that sets or interprets MASK_BITS_* now uses the enums
to define/compare the values, there is no need for MASK_BITS_* to have
a specific integer value. In fact, having a specific integer value may
encourage people to hard-code those values, or interpret the values in
incorrect ways.
As such, remove the logic that assigns a specific value to the enum
values in order to make it completely clear that it's just an enum, not
something that directly represents some integer value.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Not all code that set or interpreted "mux_bits" was using the named
macros, but rather some was simply using hard-coded integer constants.
This makes it hard to determine which pieces of code are affected by
changes to those constants.
Replace the integer constants with the equivalent macro definitions so
that everything is nicely tied together.
Note that I'm not convinced all the code was using the correct integer
constants, and hence I'm not convinced that all the code is now using
the desired macros. However, this change is a purely mechanical
replacement and should have no functional change. Fixing any bugs will
come later, separately.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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OUT_CLK_SOURCE_ are currently named after the number of bits the mask
they represent includes. However, bit count is not the only possible
variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to
OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to
more completely describe exactly what they represent, without having to
go look up the definitions.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The only place where the MASK_BITS_* values are used is in
adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28,
new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK,
i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually
implemented.
Note that no Tegra clock register actually uses all of bits 31:28 as
the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
those cases, nothing is stored in the bits above the mux field, so it's
safe to pretend that the mux field extends all the way to the end of the
register. As such, the U-Boot clock driver is currently a bit lazy, and
doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
them all together and pretends they're all 31:28. This patch doesn't
cause this issue; it was pre-existing. Hopefully, future patches will
clean this up.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code that uses it.
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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$usb_need_init prevents "usb start" from being run multiple times for
each boot attempt, i.e. once for USB storage, another for PXE, and
another for DHCP. However, the flag that's used to determine when to run
"usb start" is never cleared, so a subsequent "boot" command will never
probe for a freshly plugged in USB device. Fix this so that new USB
devices will be probed once per boot attempt.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The U-Boot "cardhu" build supports only revision 4 of the Cardhu board
and later compatible revisions. Hence, set $board_name in the default
environment to "cardhu-a04" rather than just "cardhu".
The Linux kernel has separate DTs for Cardhu A02 and A04, although the
former isn't really supported any more. Consequently, the kernel DT file
that matches the U-Boot cardhu build is "tegra30-cardhu-a04.dtb" rather
than "tegra30-cardhu.dtb". Set the $fdtfile default environment variable
to reflect this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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For Tegra20, the SKU ID actually impacts how U-Boot programs the chip,
and hence we need to explicitly know about each and every SKU ID in order
to operate correctly.
However, for Tegra30/114, this isn't the case. Rather than forcing each
new user with a different SKU to manually add their SKU ID into the code,
simply accept any SKU ID.
If U-Boot ever starts e.g. programming maximal CPU clocks etc., we'll
need to undo this, or make the default case map to conservative defaults,
but for now it's likely the path to least support cost.
Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Upon further inspection of relevant parts of the architecture, the
maximum SPL binary size is 220KiB.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
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Patch adds modification to shared omap5 abb_setup() function, and
proper registers definitions needed for ABB setup sequence. ABB is
initialized for MPU voltage domain at OPP_NOM.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
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ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support
for ES1.1 IDCODE change.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
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This patch enables dynamically powering down the
IO receiver when not performing a read on boards using DDR3.
This optimizes both active and standby power consumption.
This bit is not set on EVM SK and EVM 1.5 and later boards.
Setting the same.
This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
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This patch enables dynamically powering down the
IO receiver when not performing a read on DDR3 board.
This optimizes both active and standby power consumption.
This is derived from a patch that is done on AM335x[1]
[1] http://arago-project.org/git/projects/?p=u-boot-am33x.git;a=commit;h=6a9ee4bc72ece53fabf01825605fba3d71d5feb2
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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To reduce code duplication update omap3_igep00x0.h to use ti_omap3_common.h.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
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Create a new file, include/configs/ti_omap3_common.h, for everything
common to the OMAP3 SoC leaving just the board specific part to board
configuration file.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
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Other TI processors like am33xx, omap4 and omap5 have called these variables
as NON_SECURE_SRAM_*, shouldn't be a big problem rename these variables to
be coherent.
One reason more to rename these variables is to have the possibility of any
OMAP3 board to use the ti_armv7_common.h include as the NON_SECURE_SRAM_END
is used to define the CONFIG_SYS_INIT_SP_ADDR variable.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
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If CONFIG_NR_DRAM_BANKS is not defined, we say (for simplicity) that we have
1 bank, but for some boards should be interesting that we can define
CONFIG_NR_DRAM_BANKS. To handle this possibility just define the number of
DRAM banks if is not already defined. This is useful for some OMAP3 boards
where the DRAM initialitzation is only at u-boot level.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
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The ELM hardware engine wihich is used for ECC error detections is not present
on OMAP3 SoC, so move the CONFIG_SPL_NAND_AM33XX_BCH from ti_armv7_common.h to
SoC configuration file.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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Follow the pattern ti_<processor family>_common.h used by other TI processors
to be coherent. So just rename omap5_common.h to ti_omap5_common.h.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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Follow the pattern ti_<processor family>_common.h used by other TI processors
to be coherent. So just rename omap4_common.h to ti_omap4_common.h.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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Signed-off-by: Tom Rini <trini@ti.com>
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The commit
f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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The commit
f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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The Versatiles come up with the primary UART set to ttyAMA0 at
38400 baud, and unless we pass this to the kernel it will assume
it is set to 9600 baud which will be quite awkward for the
terminal, let's try to be helpful and inform the kernel what
setting is used.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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When U-Boot is configured for Versatile AB, it will still pass
the machine ID of Versatile PB to the kernel. After this simple
fix the system boots correctly.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
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Run "tools/reformat.py -i -d '-' -s 8 <boards.cfg >boards0.cfg && mv boards0.cfg boards.cfg"
in order to keep the entries sorted.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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This is only required for "PIC" relocation and doesn't apply to modern
"PIE" relocation which does data relocation as well as code.
"init_sequence_r" is just an array that consists of compile-time
adresses of init functions. Since this is basically an array of integers
(pointers to "void" to be more precise) it won't be modified during
relocation - it will be just copied to new location as it is.
As a consequence on execution after relocation "initcall_run_list" will
be jumping to pre-relocation addresses. As long as we don't overwrite
pre-relocation memory area init calls are executed correctly. But still
it is dangerous because after relocation we don't expect initially used
memory to stay untouched.
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Thomas Langer <thomas.langer@lantiq.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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Add the USB host boot support for the am43xx evm
Add the macros to boot from a usb drive in uBoot
Signed-off-by: Dan Murphy <dmurphy@ti.com>
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Add SPL support to be able to detect a USB Mass Storage device
connected to a USB host. Once a USB Mass storage device is detected
the SPL will load the u-boot.img from a FAT partition to target address.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
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Move the FAT functions to a common location for reuse.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
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We do not have to define CONFIG_MPC5xxx in board config headers
(and start.S) because it is defined in arch/powerpc/cpu/mpc5xxx/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Delete some serial.h files, whole code in which is surrounded by
#if 0 ... #endif
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
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The function os_free() returns nothing.
Its return type should be "void" rather than "void *".
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Before this commit, all arch/arm/cpu/${CPU}/config.mk except ARMv8
had the same option:
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
This commit moves it into arch/arm/config.mk.
If the compiler does not support the option,
it is ignored by $(call cc-option,...).
So this commit gives no harm to ARMv8.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Define CONFIG_MPC86xx in arch/powerpc/cpu/mpc86xx/config.mk
because all target boards with mpc86xx cpu define it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk
because all target boards with mpc85xx cpu define it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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We do not have to define CONFIG_MPC824X in board config headers
because it is defined in arch/powerpc/cpu/mpc824x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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We do not have to define CONFIG_5xx in a source file
because it is defined in arch/powerpc/cpu/mpc5xx/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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We do not have to define CONFIG_MPC512X in board config headers
because it is defined in arch/powerpc/cpu/mpc512x/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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We do not have to define CONFIG_8xx in source files
because it is defined in arch/powerpc/cpu/mpc8xx/config.mk
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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We do not have to define CONFIG_MPC83xx in board config headers
because it is defined in arch/powerpc/cpu/mpc83xx/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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We do not have to define CONFIG_4xx in board config headers
because it is defined in arch/powerpc/cpu/ppc4xx/config.mk.
include/configs/JSE.h defines "CONFIG_4x", not "CONFIG_4xx".
I believe it is a typo because "CONFIG_4x" is not used at all
in other files.
So, I also deleted "CONFIG_4x" in include/configs/JSE.h.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Commit e5c5301f refactored the build system not to make
directories in board makefiles.
But commit 8f380381 create directories again in
board/avionic-design/tec-ng/Makefile.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Alban Bedel <alban.bedel@avionic-design.de>
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Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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