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* PXE: FDT: Add support for fdt in PXEChander Kashyap2012-09-272-5/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now DT support is becoming common for all new SoC's. Hence it is better to have option for getting specific FDT from the remote server. This patch adds support for new label i.e. 'fdt'. This will allow to retrieve 'fdt blob' from the remote server. This patch take care for the following scenarios. The usage of fdt is optional. The 'fdt blob' can be retrieved from tftp or can be available locally or can be absent. If 'fdt_addr_r' environment variable is set and 'fdt' label is defined retrieve 'fdt blob' from tftp. 'fdt_addr_r' is then passed along bootm command. If 'fdt_addr' is set and 'fdt blob' is not retrieved from the tftp pass 'fdt_addr' to bootm command. In this case 'fdt blob' will be available at 'fdt_addr'. If 'fdt_addr' is not set and 'fdt blob' is not retrieve from tftp pass NULL to boot command. In this case 'fdt blob' is not required and absent. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Jason Hobbs <jason.hobbs@calxeda.com>
* FEC: Replace magic contantsMarek Vasut2012-09-272-3/+6
| | | | | | | | | | Replace the magic contant 1 << 24 with properly defined bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* FEC: Rework the TX wait mechanismMarek Vasut2012-09-271-9/+11
| | | | | | | | | | | | | | | | | | | | | | | The mechanism waiting for transmission to finish in fec_send() now relies on the E-bit being cleared in the TX buffer descriptor. In case of data cache being on, this means invalidation of data cache above this TX buffer descriptor on each test for the E-bit being cleared. Apparently, there is another way to check if the transmission did complete. This is by checking the TDAR bit in the X_DES_ACTIVE register. Reading a register does not need any data cache invalidation, which is beneficial. Rework the sequence that wait for completion of the transmission so that the TDAR bit is tested first and afterwards check the E-bit being clear. This cuts down the number of cache invalidation calls to one. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* FEC: Remove endless loop in the FEC driverMarek Vasut2012-09-271-1/+13
| | | | | | | | | | | | The FEC hardware sometimes errors out on data transfer and hangs in the tightloop adjusted by this patch. So add timeout into the tightloop to make such a hang recoverable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* FEC: Properly align address over the buffers for cache opsMarek Vasut2012-09-271-6/+8
| | | | | | | | | | Align the address that's to be invalidated/flushed properly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Benoit Thebaudeau <benoit.thebaudeau@advans> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* FEC: Do not pass unaligned buffer to network stackMarek Vasut2012-09-271-1/+2
| | | | | | | | | | | | | | Do not pass unaligned RX buffer to the upper layers. The upper layer, especially in the ARP case, recycles the buffer and passes it back into the FEC, into it's TX path. With caches enabled, the FEC hangs on this from time to time. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Benoit Thebaudeau <benoit.thebaudeau@advans> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* net: Add Vitesse VSC8662 PHY supportPriyanka Jain2012-09-271-4/+14
| | | | | | | | | | | -VSC8662 is Dual Port 10/100/1000Base-T Phy, 100Base-FX/1000/Base-X Gigabit Ethernt Transceiver Phy. -Its register set and features are similar to other Vitesse Phys Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* net/phy: support the mv88e6352 switchValentin Longchamp2012-09-273-0/+411
| | | | | | | | | | | | | | | | | This patch add support for the configuration of an external switch from the 88E6xxx series from Marvell trough an MDIO link using indirect adressing. This can be used if we do not want to use an EEPROM for the configuration. This driver is not generic and was not tested on other switches than the 88e6352. This is proposed as a first implementation that is somewhat limited but works and that can be used as a basis for further developments for this switch family. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Joe Hershberger <joe.hershberger@gmail.com>
* net: eth_write_hwaddr: Return error for invalid MACsBenoît Thébaudeau2012-09-271-2/+5
| | | | | | | | | If dev->enetaddr was supposed to be set with dev->write_hwaddr() but the MAC address was not valid, return an error. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* net: Add driver for Zynq Gem IPMichal Simek2012-09-263-1/+442
| | | | | | | | | Device driver for Zynq Gem IP. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Joe Hershberger <joe.hershberger@gmail.com> CC: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* net: asix: add AX88772B supportLucas Stach2012-09-261-12/+23
| | | | | | | | | | | | | | | | | | | | Add AX88772B ID together with two fixes needed to make this work. 1. The packet length check has to be adjusted, as all ASIX chips only use 11 bits to indicate the length. AX88772B uses the other bits to indicate unrelated things, which cause the check to fail. This fix is based on a fix for the Linux kernel by Marek Vasut. Linux upstream commit: bca0beb9363f8487ac902931a50eb00180a2d14a 2. AX88772B provides several bulk endpoints. Only the first IN/OUT endpoints work in the default configuration. So stop enumeration after we found them to avoid overwriting the endpoint config with a non-working one. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: asix: add read_mac functionLucas Stach2012-09-261-12/+35
| | | | | | | | | | | | | | Initial device MAC should be read while getting info about the device, so it's wrong to only read it in asix_init(). Add a dedicated function to read the initial MAC, which is also able to handle devices that have their initial MAC stored in EEPROM. Call this function inasix_eth_get_info(). Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: asix: add write_hwaddr functionLucas Stach2012-09-261-11/+52
| | | | | | | | | | | | | All ASIX chipsets aside from AX88172 are able to set the MAC address on the hardware level. Add a function to expose this ability. To differentiate between chip types we now carry flags as driver private data. Also while touching the asix_dongles array constify this. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: asix: split out basic reset functionLucas Stach2012-09-261-18/+26
| | | | | | | | | | | | The basic device reset ensures that the device is ready to service commands and does not need to get redone before each network operation. Split out the basic reset from asix_init() and instead call it from asix_eth_get_info(), so that it only gets called once. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: introduce transparent driver private in ueth_dataLucas Stach2012-09-262-20/+37
| | | | | | | | | | Avoid clutter in ueth_data. Individual drivers should not mess with structures belonging to the core like this. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Filter incoming netconsole packets by IPJoe Hershberger2012-09-243-3/+9
| | | | | | | Check the incoming packets' source IP address... if ncip isn't set to a broadcast address, only listen to the client at ncip. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Allow netconsole settings to change after nc_startJoe Hershberger2012-09-241-31/+65
| | | | | | | Refresh the netconsole settings from the env before each packet instead of only on netconsole init. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Improve the speed of netconsoleJoe Hershberger2012-09-245-17/+98
| | | | | | | | | | | | | | | | | | | Previously u-boot would initialize the network interface for every network operation and then shut it down again. This makes sense for most operations where the network in not known to be needed soon after the operation is complete. In the case of netconsole, it will use the network for every interaction with the shell or every printf. This means that the network is being reinitialized very often. On many devices, this intialization is very slow. This patch checks for consecutive netconsole actions and leaves the ethernet hardware initialized between them. It will still behave the same old way for all other network operations and any time another network operation happens between netconsole operations. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* net: Make the netconsole buffer size configurableJoe Hershberger2012-09-242-2/+8
| | | | | | | | | Allow a board to configure a larger buffer for netconsole, but leave the default. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Mike Frysinger <vapier@gentoo.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* net: sh_eth: Add support R8A7740 of rmobile (arm core)Nobuhiro Iwamatsu2012-09-242-3/+13
| | | | | | | | R8A7740 of rmobile has ethernet device, and this is same IP of sh-ether. This support R8A7740 of rmobile. Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* dm: net: Fixup the armada100 FEC driverMarek Vasut2012-09-241-2/+3
| | | | | | | | | | | Apply the following questionable adjustment to silence GCC. armada100_fec.c: In function ‘armdfec_send’: armada100_fec.c:589:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* net: emaclite: Support OF initializationMichal Simek2012-09-241-0/+30
| | | | | | | | Support new CONFIG_OF_CONTROL option where device probing is done based on device tree description. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Joe Hershberger <joe.hershberger@gmail.com>
* dm: net: Move IXP NPE to drivers/net/Marek Vasut2012-09-24151-2/+2
| | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: bugfix: NetSetTimeout assumes CONFIG_SYS_HZ=1000Tetsuyuki Kobayashi2012-09-241-1/+1
| | | | | | NetSetTimeout sets incorrect value to timeDelta when CONFIG_SYS_HZ != 1000. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* api: net: fix length check in eth_receive()Michael Walle2012-09-241-4/+1
| | | | | | | | | | | | | | | If the requested length is too small to hold the received packet, eth_receive() will return -1 and will leave the packet in the receive buffers. Instead of returning an error in this case, we return the first portion of the received packet and remove it from the receive buffers. This fixes FreeBSD's ubldr. Without this patch it will just stop receiving packets if the NIC receives more than PKTBUFSRX too large packets. Signed-off-by: Michael Walle <michael@walle.cc> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Rafal Jaworowski <raj@semihalf.com> Cc: Piotr Kruszynski <ppk@semihalf.com>
* net: Make netconsole src and dest ports configurableJoe Hershberger2012-09-243-16/+34
| | | | | | | | | | | | | | | It is desirable to use different port numbers for sending and receiving packets with netconsole in the case where you have more than one device on the local subnet with netconsole enabled for broadcast. When they use the same port for both, any output from one will look like input to the other. This is typlically not desirable. This patch allows the input and output ports to be specified separately in the environment. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Mike Frysinger <vapier@gentoo.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Prepare v2012.10-rc1Tom Rini2012-09-211-2/+2
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini2012-09-215-12/+35
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| * pci: fix some warnings related to assumptions aboutKumar Gala2012-09-222-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following commit introduced some warnings associated with using pci_addr_t instead of a proper 32-bit data type. commit af778c6d9e2b945ee03cbc53bb976238a3374f33 Author: Andrew Sharp <andywyse6@gmail.com> Date: Wed Aug 1 12:27:16 2012 +0000 pci: fix errant data types and corresponding access functions On some platforms pci_addr_t is defined as a 64-bit data type so its not proper to use with pci_{read,write}_config_dword. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fdt: Add header guard to fdtdec.hSimon Glass2012-09-211-0/+3
| | | | | | | | | | | | | | This makes it easier to include this header from other headers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * fdt: Tidy debugging, add to fdtdec_get_int/addr()Simon Glass2012-09-211-8/+19
| | | | | | | | | | | | | | The new debugging shows the value of integers and addresses read from the device tree and tidy up GPIO output. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Add gpio_request() to asm-generic headerSimon Glass2012-09-211-0/+9
| | | | | | | | | | | | This function should also be part of the GPIO API, so add it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21131-803/+2455
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| * \ Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-2144-349/+409
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| | * | mx35pdk: README: Remove NAND referencesFabio Estevam2012-09-171-76/+2
| | | | | | | | | | | | | | | | | | | | | | | | Booting from NAND is currently not supported, so remove its references. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | mx28evk: extend default environmentOtavio Salvador2012-09-171-8/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The environment has been based on mx53loco and m28evk but keeping the possibility to easy change the default console device as Freescale and mainline kernels differ on the device name. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| | * | MX6: drop binary constants from iomux headerStefano Babic2012-09-171-62/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Constants set with binary value (0b...) are not compiled from old toolchain when used by the clrsetbits_le32 macro. Replaces them with the corresponding hex value. The error reported (for example with the mx6qsabrelite board) is something like: mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | MX35: mx35pdk: add support for MMCStefano Babic2012-09-102-2/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for SD card and change the default environment due to increased u-boot size. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | mx6qsabrelite:Use IMX_GPIO_NR MacroAshok Kumar Reddy2012-09-101-12/+12
| | | | | | | | | | | | | | | | Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
| | * | MX: set a common place to share code for Freescale i.MXStefano Babic2012-09-108-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up now only MX5 and MX6 can share code, because they have a common source directory in cpu/armv7. Other not armv7 i.MX can profit of the same shared code. Move these files into a directory accessible for all, similar to plat-mxc in linux. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | ima3-mx53:Rename CONFIG_PRIME => CONFIG_ETHPRME, removeAshok Kumar Reddy2012-09-101-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | unused macro CONFIG_DISCOVER_PHY Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | mx31: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-069-20/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX31 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Helmut Raiger <helmut.raiger@hale.at>
| | * | MX28: MMC: Avoid DMA DCache race conditionMarek Vasut2012-09-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prevents dcache-related problem. The problem manifested itself on the SPI driver, this is just a port to the MMC driver. The scenario is the same. In case an "mmc read" is issued to a buffer which was written right before it and data cache is enabled, the cache eviction might happen during the DMA transfer into the buffer, therefore corrupting the buffer. Clear any cache lines that might contain the buffer to prevent such issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * | MX28: SPI: Fix the DMA chainingMarek Vasut2012-09-061-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that in order for the SPI DMA to properly support continuous transfers longer than 65280 bytes, there are some very important parts that were left out from the documentation. Firstly, the XFER_SIZE register is not written with the whole length of a transfer, but is written by each and every chained descriptor with the length of the descriptors data buffer. Next, unlike the demo code supplied by FSL, which only writes one PIO word per descriptor, this does not apply if the descriptors are chained, since the XFER_SIZE register must be written. Therefore, it is essential to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are written with zero, since they don't apply. The DMA programs the PIO words in an incrementing order, so four PIO words. Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC must not be set during the whole transfer, but it must be set only on the last descriptor in the chain. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * | MX28: SPI: Fix the DMA DCache race conditionMarek Vasut2012-09-061-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes dcache-related problem. The problem manifested when dcache was enabled and the following command issued twice: mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000 The SHA1 checksum was correct during the first call. Yet with every subsequent call of the above command, it differed and was wrong. It turns out this was because of a race condition. On the first time the command was called, no cacheline contained any data from the destination memory location. The DMA transfered data into the location and the cache above the location was invalidated. Then the checksum was computed, but that meant the data were loaded into data cache. On any subsequent call, the DMA again transfered data into the same destination. Yet during the transfer, some of the DCache lines were evicted and written back into the main memory. Once the DMA transfer completed, the data cache was invalidated over the memory location as usual. But the data that were to be loaded back into the data cache by subsequent SHA1 checksuming were corrupted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * | Fix mx31_decode_pllBenoît Thébaudeau2012-09-061-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| | * | mx35 timer: Switch to 32-kHz sourceBenoît Thébaudeau2012-09-061-17/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the mx35 timer driver to the 32-kHz clock source to avoid calling mxc_get_clock() again and again, and to be consistent with the timer drivers of other i.MX SoCs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | mx35: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-065-30/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX35 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | mx25: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-065-11/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX25 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Matthias Weisser <weisserm@arcor.de>
| | * | mx35: Fix clock dividersBenoît Thébaudeau2012-09-062-59/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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