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* powerpc/p1022ds: fix DIU/LBC switching with NAND enabledTimur Tabi2012-08-081-8/+74
| | | | | | | | | | | In order for indirect mode on the PIXIS to work properly, both chip selects need to be set to GPCM mode, otherwise writes to the chip select base addresses will not actually post to the local bus -- they'll go to the NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM mode before switching to indirect mode. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p1022ds: add support for SPI and SD bootMatthew McClintock2012-08-084-3/+70
| | | | | | | | | | | | | | | | | | Add TLB mappings, board target options, and configuration items need for SPI/SD boot. Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them. Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/82xx: adapt SDRAM settings for mgcoge3neGerlando Falauto2012-07-311-2/+4
| | | | | | | | | | The HW guys suggested to change these two values. And these values are now identical to the values we use on mgcoge. PSDMR_WRC was set to 1C as it should lead to better performance. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* powerpc/82xx: use SDRAM detection for mgcoge2neGerlando Falauto2012-07-311-4/+13
| | | | | | | | | | | | | | mgcoge2ne was an intermediate step towards mgcoge3ne. One difference is the smaller SDRAM on mgcoge2ne (128MB). To support both boards with the same u-boot we use here the SDRAM detection. This patch enables SDRAM detection between 256MB and 128MB. So in addition to the existing 256MB geometry: 4 chips x 8M (13 rows, 10 cols) x 16 bit x 4 banks we can now also have 128MB geometry: 4 chips x 4M (13 rows, 9 cols) x 16 bit x 4 banks Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* powerpc/82xx: add SDRAM detection for km82xxGerlando Falauto2012-07-311-2/+49
| | | | | | | | | | | | This patch adds SDRAM detection feature to km82xx boards. To enable this feature, define CONFIG_SYS_SDRAM_LIST as the initializer for an array of struct sdram_conf_s. These structs will expose the bitfields within registers PSDMR and OR1 which have to be different between configurations; common bitfields will be defined, as usual, within CONFIG_SYS_PSDMR and CONFIG_SYS_OR1. If CONFIG_SYS_SDRAM_LIST is not defined, then the usual behavior is retained. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* powerpc/82xx: move km/km82xx-common.h within km82xx.hGerlando Falauto2012-07-312-318/+289
| | | | | | | The only file including km82xx-common.h is km82xx.h. So there is no need to have it as a separate file. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* powerpc/82xx: merge mgcoge.h and mgcoge3ne.h into km82xx.hGerlando Falauto2012-07-313-96/+59
| | | | | | | | | Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need to keep them as separate .h config files. Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h file. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* powerpc/82xx: move mgcoge, mgcoge3ne defines to ease subsequent mergeGerlando Falauto2012-07-312-34/+34
| | | | Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* powerpc/82xx: remove unused define for mgcoge3neHolger Brunck2012-07-311-3/+0
| | | | Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* SMDK6400: Add MAINTAINERS entryZhong Hongbo2012-07-311-1/+4
| | | | Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2012-07-3129-321/+822
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: km/common: remove printfs for i2c deblocking code CONFIG: SMDK5250: I2C: Enable I2C I2C: Add support for Multi channel I2C: Modify the I2C driver for EXYNOS5 I2C: Move struct s3c24x0_i2c to a common place. EXYNOS: PINMUX: Add pinmux support for I2C EXYNOS5: define EXYNOS5_I2C_SPACING EXYNOS: Add I2C base address. EXYNOS: CLK: Add i2c clock mx6qsabrelite: add i2c multi-bus support imx-common: add i2c.c for bus recovery support i.mx53: add definition for I2C3_BASE_ADDR i.mx: iomux-v3.c: move to imx-common directory i.mx: iomux-v3.h: move to imx-common include directory iomux-v3: remove include of mx6x_pins.h mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS support mxc_i2c: add bus recovery support mxc_i2c: prep work for multiple busses support mxc_i2c: add i2c_regs argument to i2c_imx_stop mxc_i2c: add retries mxc_i2c: check for arbitration lost mxc_i2c: change slave addr if conflicts with destination. mxc_i2c: don't disable controller after every transaction mxc_i2c: place i2c_reset code inline mxc_i2c: place imx_start code inline mxc_i2c: remove redundant read mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into wait_for_sr_state mxc_i2c.c: code i2c_probe as a 0 length i2c_write mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_write mxc_i2c: create i2c_init_transfer mxc_i2c: clear i2sr before waiting for bit mxc_i2c: create tx_byte function mxc_i2c: remove ifdef of CONFIG_HARD_I2C mxc_i2c: fix i2c_imx_stop i2c: deblock i2c bus also if accessed before realocation Signed-off-by: Wolfgang Denk <wd@denx.de>
| * km/common: remove printfs for i2c deblocking codeHolger Brunck2012-07-311-3/+0
| | | | | | | | | | | | | | | | | | This code will also be used before reallocation and during this time we are not allowed to do these printings. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de>
| * CONFIG: SMDK5250: I2C: Enable I2CRajeshwari Shinde2012-07-312-1/+39
| | | | | | | | | | | | | | | | | | | | | | This enables I2C support on smdk5250. Pinmux setting moved to board file to avoid repeated setting of gpio lines. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * I2C: Add support for Multi channelRajeshwari Shinde2012-07-311-0/+27
| | | | | | | | | | | | | | | | This adds multiple i2c channel support for I2C. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * I2C: Modify the I2C driver for EXYNOS5Rajeshwari Shinde2012-07-311-77/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the S3C I2C driver to suppport EXYNOS5. The cahnges made to driver are as follows: - I2C base address is passed as a parameter to many functions to avoid multiple #ifdef - Channel initialisation is moved to a commom funation as it is required by i2c_init. - Hardcoding for I2CCON_ACKGEN removed. - Replaced printf with debug. - Checkpatch issues resolved. - Pinmux setting will be done in board/samsung/smdk5250/smdk5250.c to avoid repeated setting of gpio lines, as it have multi bus support. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * I2C: Move struct s3c24x0_i2c to a common place.Rajeshwari Shinde2012-07-312-10/+33
| | | | | | | | | | | | | | | | | | | | struct s3c24x0_i2c is being moved to common local header file so that the same can be used by s3c series and exynos series SoCs. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * EXYNOS: PINMUX: Add pinmux support for I2CRajeshwari Shinde2012-07-312-0/+60
| | | | | | | | | | | | | | This patch adds pinmux code for I2C. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * EXYNOS5: define EXYNOS5_I2C_SPACINGRajeshwari Shinde2012-07-311-0/+2
| | | | | | | | | | | | | | | | This patch defined EXYNOS5_I2C_SPACING used to calculate I2C channel base address. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * EXYNOS: Add I2C base address.Rajeshwari Shinde2012-07-311-0/+3
| | | | | | | | | | | | | | | | This patch adds the base address for I2C. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * EXYNOS: CLK: Add i2c clockRajeshwari Shinde2012-07-312-0/+34
| | | | | | | | | | | | | | | | | | This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * mx6qsabrelite: add i2c multi-bus supportTroy Kisky2012-07-312-8/+48
| | | | | | | | | | | | | | This includes bus recovery support. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Jason Liu <r64343@freescale.com>
| * imx-common: add i2c.c for bus recovery supportTroy Kisky2012-07-317-1/+186
| | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * i.mx53: add definition for I2C3_BASE_ADDRTroy Kisky2012-07-311-0/+1
| | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * i.mx: iomux-v3.c: move to imx-common directoryTroy Kisky2012-07-313-2/+2
| | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * i.mx: iomux-v3.h: move to imx-common include directoryTroy Kisky2012-07-316-6/+6
| | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * iomux-v3: remove include of mx6x_pins.hTroy Kisky2012-07-311-1/+0
| | | | | | | | | | | | | | This include is not needed. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Jason Liu <r64343@freescale.com>
| * mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS supportTroy Kisky2012-07-311-0/+17
| | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * mxc_i2c: add bus recovery supportTroy Kisky2012-07-311-0/+26
| | | | | | | | | | | | | | | | | | Add support for calling a function that will toggle the SCL line to return the bus to idle condition. The actual toggling function is added in a later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * mxc_i2c: prep work for multiple busses supportTroy Kisky2012-07-311-21/+104
| | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * mxc_i2c: add i2c_regs argument to i2c_imx_stopTroy Kisky2012-07-311-12/+7
| | | | | | | | | | | | | | This is prep work for CONFIG_I2C_MULTI_BUS. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| * mxc_i2c: add retriesTroy Kisky2012-07-311-9/+27
| | | | | | | | | | | | | | Retry unexpected hardware errors. This will not retry a received NAK. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * mxc_i2c: check for arbitration lostTroy Kisky2012-07-311-0/+7
| | | | | | | | | | | | | | No need to continue waiting if arbitration lost. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| * mxc_i2c: change slave addr if conflicts with destination.Troy Kisky2012-07-311-0/+2
| | | | | | | | | | | | | | The i2c controller cannot be both master and slave in the same transaction. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * mxc_i2c: don't disable controller after every transactionTroy Kisky2012-07-311-15/+13
| | | | | | | | | | | | | | This helps in a multiple bus master environment which is why I also added a wait for bus idle. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * mxc_i2c: place i2c_reset code inlineTroy Kisky2012-07-311-12/+3
| | | | | | | | | | | | | | | | imx_reset is only referenced once so move to that location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| * mxc_i2c: place imx_start code inlineTroy Kisky2012-07-311-33/+20
| | | | | | | | | | | | | | | | imx_start is only referenced once so move to that location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| * mxc_i2c: remove redundant readTroy Kisky2012-07-311-1/+0
| | | | | | | | | | | | | | | | wait_for_sr_state returns i2sr on success so no need to read again. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| * mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into ↵Troy Kisky2012-07-311-51/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | wait_for_sr_state Not using udelay gives a more accurate timeout. The current implementation of udelay in imx-common does not seem to wait at all for a udelay(1). Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> ---- V2: Added WATCHDOG_RESET as suggested by Marek Vasut add error message when stop fails mxc_i2c: code i2c_probe as a 0 length i2c_write Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * mxc_i2c.c: code i2c_probe as a 0 length i2c_writeTroy Kisky2012-07-311-17/+8
| | | | | | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_writeTroy Kisky2012-07-311-3/+7
| | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * mxc_i2c: create i2c_init_transferTroy Kisky2012-07-311-26/+18
| | | | | | | | | | | | | | | | | | Initial code of i2c_read and i2c_write is identical, move to subroutine. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * mxc_i2c: clear i2sr before waiting for bitTroy Kisky2012-07-311-4/+5
| | | | | | | | | | | | | | | | | | | | | | Let's clear the sr register before waiting for bit to be set, instead of clearing it after hardware sets it. No real operational difference here, but allows combining of i2c_imx_trx_complete and i2c_imx_bus_busy in later patches. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| * mxc_i2c: create tx_byte functionTroy Kisky2012-07-311-58/+24
| | | | | | | | | | | | | | | | Use tx_byte function instead of having 3 copies of the code. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| * mxc_i2c: remove ifdef of CONFIG_HARD_I2CTroy Kisky2012-07-311-5/+1
| | | | | | | | | | | | | | | | This is always selected when CONFIG_I2C_MXC is selected, so it adds no value. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| * mxc_i2c: fix i2c_imx_stopTroy Kisky2012-07-311-1/+1
| | | | | | | | | | | | | | | | | | | | Instead of clearing 2 bits, all the other bits were set because '|=' was used instead of '&='. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * i2c: deblock i2c bus also if accessed before realocationHolger Brunck2012-07-311-0/+1
| | | | | | | | | | | | | | | | | | If we switch to a different i2c bus in changing the mux config for the i2c mux, we have to be sure to deblock the bus also before realocation. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Heiko Schocher <hs@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2012-07-3117-111/+595
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Wire up SPI driver spi: microblaze: Adds driver for Xilinx SPI controller microblaze: intc: Clear interrupt code microblaze: Call serial multi initialization microblaze: Move __udelay implementation microblaze: Remove extern from board.c microblaze: Wire up dts configuration fdt: Add board specific dts inclusion microblaze: Move individual board linker scripts to common script in cpu tree. microblaze: Add gpio.h microblaze: Add missing undefs for UBI and UBIFS microblaze: Expand and correct configuration comments microblaze: Enable ubi support microblaze: Avoid compile error on systems without cfi flash microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | microblaze: Wire up SPI driverStephan Linz2012-07-311-3/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Depending on XILINX_SPI_FLASH_BASEADDR enable SPI flash and environment in SPI flash. Expected values from xparameters.h are: - XILINX_SPI_FLASH_BASEADDR - XILINX_SPI_FLASH_MAX_FREQ - XILINX_SPI_FLASH_CS Signed-off-by: Stephan Linz <linz@li-pro.net> Acked-by: Michal Simek <monstr@monstr.eu>
| * | spi: microblaze: Adds driver for Xilinx SPI controllerStephan Linz2012-07-313-0/+350
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an improved version of the driver patch original submitted by Graeme Smecher <graeme.smecher@mail.mcgill.ca> The changes are: - remove hard coded Xilinx BSP defines (XPAR_SPI_*) and use CONFIG_SYS_SPI_BASE from config.h instead - add extensive register struct definitions - remove offset calculation for register access and use the new register struct instead - move default SPI controller configuration from spi_setup_slave() to spi_claim_bus() - add spi_set_speed() - insert SPI controller deactivation in spi_release_bus() - protect while loops in spi_xfer() with counter / timeouts - support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP Come from: http://patchwork.ozlabs.org/patch/71797/ Signed-off-by: Stephan Linz <linz@li-pro.net> Tested-by: Michal Simek <monstr@monstr.eu>
| * | microblaze: intc: Clear interrupt codeMichal Simek2012-07-106-48/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | Clear and prepare for device-tree driven configuration. Remove CONFIG_SYS_INTC_0 definition Use dynamic allocation instead of static. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Simon Glass <sjg@chromium.org>
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