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* usb: host: ehci: samsung: Move hcor initialization after usb phy setupLukasz Majewski2015-12-171-2/+2
| | | | | | | | | | | | | With the old order of initialization the hcor pointer has been setup to the same address as Exynos EHCI base address (0x12110000 instead of 0x12110010). Such behaviour was caused by reading value of 0 instead of 0x10 from EHCI HCCPBASE register without doing proper clock initialization before. To fix this problem hcor initialization has been moved after USB PHY setup. Now ehci_readl(&ctx->hcd->cr_capbase) returns correct value. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.hMarek Vasut2015-12-1715-18/+18
| | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the global s3c_udc.h header to dwc2_udc.h. The rename is done automatically: $ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \ `git grep "s3c_udc\.h" | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename s3c_udc_probe() functionMarek Vasut2015-12-1713-14/+14
| | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the second and final to rename global symbol, the s3c_udc_probe() function. The rename is done automatically: $ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \ `git grep s3c_udc_probe | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename struct s3c_plat_otg_dataMarek Vasut2015-12-1714-16/+16
| | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the first to rename global symbol, the struct s3c_plat_otg_data. The rename is done automatically: $ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \ `git grep s3c_plat_otg_data | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename USB_GADGET_S3C_UDC_OTG* to USB_GADGET_DWC2_OTG*Marek Vasut2015-12-177-12/+12
| | | | | | | | | | | | | The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the config option to make it less misleading. No functional change, just a mechanical change done using the following script: git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \ while read line ; do sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ; done Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Tweak the commentsMarek Vasut2015-12-175-5/+5
| | | | | | | The driver is actually for the Designware DWC2 controller. Tweak the comments in the driver to reflect this fact. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename remaining macrosMarek Vasut2015-12-174-22/+22
| | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the remaining S3C_* macros to match the DWC2 naming. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename sources to dwc2_*cMarek Vasut2015-12-174-6/+6
| | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the local source files to dwc2_*c and adjusts the Makefile to use the new names. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename local headers to dwc2_*hMarek Vasut2015-12-175-8/+8
| | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the local header files to dwc2_*h and adjusts the sources to use the new names. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Change the driver name to dwc2-udcMarek Vasut2015-12-171-3/+3
| | | | | | Just change the driver name. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Zap useless externsMarek Vasut2015-12-172-5/+3
| | | | | | | The extern statements are useless, remove them. Also remove the extern ... controller, which is completely useless. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename remaining local s3c_*() functionsMarek Vasut2015-12-172-23/+23
| | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the remaining local s3c_*() functions to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename s3c_udc_*() functionsMarek Vasut2015-12-172-47/+47
| | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the s3c_ep_*() functions to reflect this. The function s3c_udc_probe() is a special case and is not renamed by this patch yet. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename s3c_ep_*() functionsMarek Vasut2015-12-171-11/+11
| | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the s3c_ep_*() functions to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename s3c_ep0_*() functionsMarek Vasut2015-12-172-14/+14
| | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the s3c_ep0_*() functions to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Staticize functions in s3c_udc_otg_xfer_dma.cMarek Vasut2015-12-171-7/+7
| | | | | | Just staticize the functions, they are not used outside of the file. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Staticize s3c_udc_ep_set_stallMarek Vasut2015-12-172-3/+1
| | | | | | This function is local to s3c_udc_otg_xfer_dma.c , staticize it. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename struct s3c_requestMarek Vasut2015-12-173-28/+28
| | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_request to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename struct s3c_epMarek Vasut2015-12-173-46/+46
| | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_ep to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename struct s3c_dev_*_epMarek Vasut2015-12-171-4/+4
| | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_dev_*_ep to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename struct s3c_usbotg_phy to dwc2_usbotg_phyMarek Vasut2015-12-172-5/+5
| | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy to make things more obvious and clear. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Split private bits from s3c_udc.hMarek Vasut2015-12-175-92/+108
| | | | | | | | | Most of the functions are local to the s3c_udc driver, remove them from the s3c_udc.h header to stop those bits from propagating all over the place. Instead, move all the private stuff into new private s3c_udc_otg_priv.h header. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename struct s3c_usbotg_reg to dwc2_usbotg_regMarek Vasut2015-12-172-3/+3
| | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_usbotg_reg to struct dwc2_usbotg_reg to make things more obvious and clear. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename struct s3c_udc to dwc2_udcMarek Vasut2015-12-175-51/+51
| | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_udc to struct dwc2_udc to make things more obvious and clear. Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename regs-otg.h to s3c_udc_otg_regs.hMarek Vasut2015-12-173-2/+2
| | | | | | | Rename the header file, so it's obvious which driver it's part of. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
* eeprom: fix eeprom write procedureAlexey Brodkin2015-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This fixes commit 1a37889b0ad084a740b4f785031d7ae9955d947b: ----------------------->8-------------------- eeprom: Pull out the RW loop Unify the code for doing read/write into single function, since the code for both the read and write is almost identical. This again trims down the code duplication. ----------------------->8-------------------- where the same one routine is utilized for both EEPROM writing and reading. The only difference was supposed to be a "read" flag which in both cases was set with 1 somehow. That lead to a missing delay in case of writing which lead to write failure (in my case no data was written). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de>
* Revert "include/linux: move typdef for uintptr_t"York Sun2015-12-162-1/+3
| | | | | | | | This reverts commit e8f954a756a825130d11b9c8fca70101dd8b3ac5, which causes compiling errors on 32-bit hosts. Acked-by: Aneesh Bansal <aneesh.bansal@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-1457-283/+1079
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| * armv8: Add sata support on Layerscape ARMv8 boardTang Yuantian2015-12-156-0/+131
| | | | | | | | | | | | | | | | | | | | | | Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/crypto/fsl: fix endianness issue in RNGAneesh Bansal2015-12-151-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block. So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> CC: Alex Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-1510-21/+82
| | | | | | | | | | | | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * include/linux: move typdef for uintptr_tAneesh Bansal2015-12-152-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address. If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit. The typdef has been moved from include/compiler.h to include/linux/types.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8: Make SEC read/write as snoopable for LS1043Aneesh Bansal2015-12-151-0/+5
| | | | | | | | | | | | | | | | For LS1043, SEC read/writes are made snoopable by setting the corresponding bits in SCFG to avoid coherency issues. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8: define usec2ticks functionAneesh Bansal2015-12-151-0/+11
| | | | | | | | | | | | | | | | usec2ticks() function has been defined for ARMv8 which will be used by SEC Driver. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_qspi: Pet the watchdog while reading/writingAlexander Stein2015-12-151-0/+5
| | | | | | | | | | | | | | | | | | When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog timeout might occur meanwhile. So pet the watchdog while operating on the flash. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8: fsl-layerscale: Rewrite reserving memory for MC and debug serverYork Sun2015-12-156-60/+25
| | | | | | | | | | | | | | | | | | | | | | MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
| * common: Rewrite hiding the end of memoryYork Sun2015-12-152-9/+16
| | | | | | | | | | | | | | | | | | | | | | As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves some memory from the end of ram, tracked by gd->ram_size. It is not always the top of u-boot visible memory. Rewrite the macro with a weak function to provide flexibility for complex calcuation. Legacy use of this macro is still supported. Signed-off-by: York Sun <yorksun@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun2015-12-158-19/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
| * Reserve secure memoryYork Sun2015-12-154-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure memory is at the end of memory, separated and reserved from OS, tracked by gd->secure_ram. Secure memory can host MMU tables, security monitor, etc. This is different from PRAM used to reserve private memory. PRAM offers memory at the top of u-boot memory, not necessarily the real end of memory for systems with very large DDR. Using the end of memory simplifies MMU setup and avoid memory fragmentation. "bdinfo" command shows gd->secure_ram value if this memory is marked as secured. Signed-off-by: York Sun <yorksun@freescale.com>
| * move erratum a008336 and a008514 to soc specific fileYao Yuan2015-12-152-34/+37
| | | | | | | | | | | | | | | | As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/fsl-ls102xa: Workaround for DDR erratum A008514Yao Yuan2015-12-152-1/+11
| | | | | | | | | | | | | | | | | | | | | | This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance. The value: 63b2_0042h comes from the hardware team. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7: ls102xa: cci-400: Enable snoop and DVM message requests.Yao Yuan2015-12-151-1/+7
| | | | | | | | | | | | | | | | | | Enable snoop and DVM message on all CCI-400 slave ports. Setting on disabled feature (snoop or DVM) is ignored by CCI-400. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> [York Sun: Add commit message] Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: enable all the snoop signal for masters.Yao Yuan2015-12-132-0/+14
| | | | | | | | | | | | | | | | | | | | | | Enable the IP feature's snoop signal to support hardware snoop for cache coherence. SNPCNFGCR contains the bits to drive snoop signal for various masters. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021a: merge SoC specific code in a separate fileYao Yuan2015-12-135-87/+83
| | | | | | | | | | | | | | Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * qbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submitTom Rini2015-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With gcc-5.x we get a warning about the ambiguity of BUG_ON(!a != b) and becomes BUG_ON((!a) != b). In this case reading of the function leads to us wanting to rewrite this as BUG_ON(a != b). Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Geoff Thorpe <Geoff.Thorpe@freescale.com> Cc: Haiying Wang <Haiying.Wang@freescale.com> Cc: Roy Pledge <Roy.Pledge@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_*_serdes.c: Modify memset call in serdes_initTom Rini2015-12-133-3/+3
| | | | | | | | | | | | | | | | | | | | | | GCC 5.x does not like sizeof(array_variable) and errors out. Change these calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) * SERDES_PRCTL_COUNT (the number of array elements). Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * Enable console log from earlyconsole in Linux bootargsPratiyush Mohan Srivastava2015-12-132-2/+2
| | | | | | | | | | | | | | | | Remove 115200 from "earlycon" to avoid loss of initial log messages during linux kernel 4.1 bootup Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-135-4/+22
| | | | | | | | | | | | | | | | This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu2015-12-133-3/+39
| | | | | | | | | | | | | | | | | | DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/errata: move fsl_errata.h to common directoryShengzhou Liu2015-12-134-7/+15
| | | | | | | | | | | | | | | | | | move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
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