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* logos: add Toradex logoStefan Agner2015-08-131-0/+0
| | | | | | | | | | | | | | Use the boot loader splash screen from WinCE which matches our wallpapers position wise. Although the logo is an 8-bit indexed BMP as well colours looked odd at first in U-Boot. After converting to full RGB palette and converting back to an indexed BMP using imagemagick the Logo showed up properly. $ convert tools/logos/toradex-rgb.bmp -type Palette -colors 256 \ -compress none -verbose BMP3:tools/logos/toradex.bmp Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* image-fdt.c: store returned error valueMax Krummenacher2015-08-131-1/+2
| | | | | | | | | | | This fixes the following warning (and the runtime error reporting): ../common/image-fdt.c:491:4: warning: 'fdt_ret' may be used uninitialized in this function [-Wmaybe-uninitialized] Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Glass <sjg@chromium.org>
* colibri_vf: remove spurious new lineMarcel Ziswiler2015-08-131-1/+0
| | | | | | | | Remove spurious new line in configuration file. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* generic-board: allow showing custom board infoMarcel Ziswiler2015-08-131-1/+1
| | | | | | | | | | Allow showing custom board info from a checkboard() function being implemented if CONFIG_CUSTOM_BOARDINFO is specified. Previously the device tree model was always displayed not taking any CONFIG_CUSTOM_BOARDINFO into account. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fs/fs.c: read up to EOF when len would read past EOFMax Krummenacher2015-08-131-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | http://lists.denx.de/pipermail/u-boot/2012-September/134347.html allows for reading files in chunks from the shell. When this feature is used to read past the end of a file an error was returned instead of returning the bytes read up to the end of file. Thus the following fails in the shell: offset = 0 len = chunksize do read file, offset, len write data until bytes_read < len The patch changes the behaviour to printing an informational message and returning the actual read number of bytes aka read(2) behaviour for convenient use in U-Boot scripts. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* configs: ti_armv7_keystone2: increase size reserved for initrdVitaly Andrianov2015-08-131-1/+1
| | | | | | | 9MB reserved for initrd is not enough for default ramfs used for keystone devices, which is ~33MB. This patch increases the size up to 80MB. Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
* configs: ti_armv7_keystone2: fix initrd address at args_ramfsVitaly Andrianov2015-08-131-1/+1
| | | | | | | | | | This patch set the correct initrd address to much rdaddr, which used at get_fs_ramfs commad. Fixes: 3e97f0b63c8e ("configs: ti_armv7_keystone2: switch addresses to generic addresses") Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
* common/lcd_console: fix console/logo regressionMarcel Ziswiler2015-08-131-2/+2
| | | | | | | | | | | | | | | | The following commit changed the order of the column vs. row parameter to the lcd_init_console() function but missed actually changing it as well the second time it is called from lcd_clear() which resulted in a garbled text console which this patch fixes. commit 604c7d4a5a3cf70949f6e6094bf0d52ee3b4804d common/lcd_console: introduce display/framebuffer rotation Tested on Colibri T20 with my latest assortment of tegra fixes/enhancements patch set. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Simon Glass <sjg@chromium.org>
* kconfig: add config option for shell promptNikita Kiryanov2015-08-13517-307/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add option to set shell prompt string from menuconfig and migrate boards globally. The migration is done as follows: - Boards that explicitly and unconditionally set CONFIG_SYS_PROMPT had the entry moved to their defconfig files. - Boards that defined some kind of #ifdef logic which selects the CONFIG_SYS_PROMPT (for example qemu-mips) got an #undef CONFIG_SYS_PROMPT right before the #ifdef logic and were left alone. - This change forces CONFIG_SYS_PROMPT to be a per board decision, and thus CONFIG_SYS_PROMPT was removed from all <soc>_common.h and <arch>_common.h files. This results in a streamlined default value across platforms, and includes the following files: spear-common, sunxi-common, mv-common, ti_armv7_common, tegra-common, at91-sama5_common, and zynq-common. - Boards that relied on <arch/soc>_common.h values of CONFIG_SYS_PROMPT were not updated in their respective defconfig files under the assumption that since they did not explicitly define a value, they're fine with whatever the default is. - On the other hand, boards that relied on a value defined in some <boards>_common.h file such as woodburn_common, rpi-common, bur_am335x_common, ls2085a_common, siemens_am33x_common, and omap3_evm_common, had their values moved to the respective defconfig files. - The define V_PROMPT was removed, since it is not used anywhere except for assigning a value for CONFIG_SYS_PROMPT. Cc: Tom Rini <trini@konsulko.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> [trini: Add spring, sniper, smartweb to conversion] Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: drop "optional" from target select in favor of ARCH_VERSATILEMasahiro Yamada2015-08-124-4/+1
| | | | | | | | | | | | | | | | | | | | | Since commit a26cd04920dc ("arch: Make board selection choices optional"), Kconfig could create such an insane .config file that no SoC/board is selected. This is now a real problem for Buildroot, for example. (http://lists.busybox.net/pipermail/buildroot/2015-July/135125.html) This commit drops the "optional" from the ARM target select menu in favor of "Versatile family". Rationale: - Historically, Linux chose versatile_defconfig as the default of ARM defconfig. (arch/arm/Makefile of Linux describes: KBUILD_DEFCONFIG := versatile_defconfig) - It was published by ARM Ltd. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* dra7xx: Add dra72_evm_defconfig using CONFIG_DMTom Rini2015-08-1211-0/+4575
| | | | | | | | | | - Import various DT files for DRA7 / DR72x / dra72-evm from Linux Kernel v4.1 - Add config file for this board, enable DM and DM_GPIO Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dra7xx: Move CONS_INDEX to Kconfig and enable CONFIG_SPL_STACK_ADDRTom Rini2015-08-124-3/+17
| | | | | | | | - Move the CONS_INDEX selection out of CONFIG_SYS_EXTRA_OPTIONS and into Kconfig proper. - While in here, enable CONFIG_SPL_STACK_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DMTom Rini2015-08-122-3/+3
| | | | | | | | | We now have the CONFIG_SPL_DM for code within SPL to toggle caring about DM or not. Without this change platforms that do enable CONFIG_DM but not CONFIG_SPL_DM may be broken (such as OMAP5). Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com>
* gpio: omap: Drop 'method' parameterTom Rini2015-08-126-86/+94
| | | | | | | | | | The "method" parameter was part of the original port of the driver from the kernel. At some point this may have been added to allow for future differentiation (as omap1 and omap2 have different GPIO IP blocks, so this wasn't an unreasonable thing to do). At this point however it's just extra overhead, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
* am33xx: Update DT files, add am335x_gp_evm_config targetTom Rini2015-08-1210-206/+2156
| | | | | | | | | | - Re-sync DT files for am33xx with Linux Kernel v4.1 - Include DT file now for the "AM335x GP EVM" and build target for it, via device tree and DM. - We only need to provide platform data for UART when OF_CONTROL isn't also enabled really. We can just push GPIO to coming from DT Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: am437x: Introduce new board cm-t43Nikita Kiryanov2015-08-129-0/+655
| | | | | | | | | | | Add initial support for CM-T43, an AM437x based SoM. This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM detection. Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* gpio: am43xx: expand gpio supportNikita Kiryanov2015-08-121-0/+4
| | | | | | | | | AM43XX SoCs support up to 192 GPIO signals. Make this amount available to the driver. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* mmc: omap_hsmmc: enable 8bit interface for eMMC for AM43xxNikita Kiryanov2015-08-121-2/+2
| | | | | | | | | Enable 8bit interface on HSMMC2 for am43xx to support 8bit eMMC chips. Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* mmc: omap_hsmmc: enable proper CMD(DAT) lines reset procedure for am43xxNikita Kiryanov2015-08-121-1/+1
| | | | | | | | | | | The CMD(DAT) lines reset procedure described in the OMAP4(AM335x, OMAP5, DRA7xx) TRMs is also necessary for AM43XX. Enable it in the driver. Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: am43xx: enable spi clockNikita Kiryanov2015-08-121-0/+1
| | | | | | | | | | Add spi clock to the list of am43xx basic clocks to make the SPI subsystem available on am43xx systems. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: omap3_spi: add am43xx support to omap3_spiNikita Kiryanov2015-08-121-1/+1
| | | | | | | | | Add support for AM43XX to the omap3_spi driver. Cc: Jagan Teki <jteki@openedev.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM64: hikey: Add a README for this board.Peter Griffin2015-08-121-0/+160
| | | | | | | To help others with compiling and flashing ATF and u-boot add a README for this board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board.Peter Griffin2015-08-126-0/+551
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HiKey is the first 96boards consumer edition compliant board. It features a hi6220 SoC which has eight ARM A53 cpu's. This initial port adds support for: - 1) Serial 2) eMMC / SD card 3) USB 4) GPIO It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable. Notes: eMMC has been tested with basic reading of eMMC partition into DDR. I have not tested writing / erasing. Due to lack of clock control it won't be running in the most performant high speed mode. SD card slot has been tested for reading and booting kernels into DDR. It is also currently configured to save the u-boot environment to the SD card. USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage are correctly enumerated. GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs. Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller.Peter Griffin2015-08-123-0/+65
| | | | | | | | | This patch adds the glue code for hi6220 SoC which has 2x synopsis dw_mmc controllers. This will be used by the hikey board support in subsequent patches. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* pmic: pmic_hi6553: Add a driver for the hi6553 pmic found on hikey board.Peter Griffin2015-08-123-0/+213
| | | | | | | | | This adds a simple pmic driver for the hi6553 pmic which is used in conjunction with the hi6220 SoC on the hikey board. Eventually this driver will be updated to be a proper UCLASS PMIC driver which can parse the voltages direct from device tree. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* hisilicon: hi6220: Add a hi6220 pinmux driver.Peter Griffin2015-08-125-0/+305
| | | | | | | This patch adds basic pinmux support for the hi6220 SoC, which is found on the hikey board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* ARM: hi6220: Add register and bitfield definition header files.Peter Griffin2015-08-122-0/+807
| | | | | | | This patch adds the header files which will be used in the subsquent board / drivers to enable support for hi6220 hikey board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* dm: gpio: hi6220: Add a hi6220 GPIO driver model driver.Peter Griffin2015-08-123-0/+126
| | | | | | | This patch adds support for the GPIO perif found on hi6220 SoC. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* common/cmd_source.c: Fix the source command failure under 64-bit platformGong Qianyu2015-08-121-3/+3
| | | | | | | | | | | Modify the data pointer type from ulong* to u32*. For arm64 type "ulong" could be 64-bit. Then in line 89 of common/cmd_source.c: "while (*data++);" data will point to the next 64 bits each time. As the uImage file generated by mkimage tool keeps the same data format in either 32-bit or 64-bit platform, the difference would cause failure in 64-bit platform. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
* spl: Fix compile warning for arm64Gong Qianyu2015-08-121-1/+1
| | | | | | Make the cast explicit for "warning: cast to pointer from integer of different size". Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
* imx28: Fix issue with GCC 5.xMåns Rullgård2015-08-121-1/+1
| | | | | | | | | | | | | | The semantics for non-static functions declared inline have changed in gcc5, causing the empty functions not to be emitted as an external symbol. Since lowlevel_init() is only referenced from start.S, it should not be declared inline at all. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Otavio Salvador <otavio@ossystems.com.br> [trini: Reword commit message] Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Use common definition for clk_get_rateLokesh Vutla2015-08-128-103/+167
| | | | | | | | Since all the clocks are defined common, and has the same logic to get the frequencies, use a common definition for for clk_get_rate(). Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Remove unsed external clocksLokesh Vutla2015-08-129-66/+15
| | | | | | | | Remove unused external clocks and make a common definition for all keystone platforms. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Cleanup init_pll definitionLokesh Vutla2015-08-125-46/+84
| | | | | | | | | This is just a cosmetic change that makes the calling of pll init code looks much cleaner. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Use common structure for PLLsLokesh Vutla2015-08-1210-51/+22
| | | | | | | | | | Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Fix dev and arm speed detectionLokesh Vutla2015-08-1212-162/+114
| | | | | | | | | Use common devspeed and armspeed definitions. Also fix reading efuse bootrom register. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Cleanup PLL init codeLokesh Vutla2015-08-128-174/+211
| | | | | | | | | | | There are two types of PLL for all keystone platforms: Main PLL, Secondary PLL. Instead of duplicating the same definition for each secondary PLL, have a common function which does initialization for both PLLs. And also add proper register definitions. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFOLokesh Vutla2015-08-122-0/+33
| | | | | | | | | | Add print_cpuinfo() function and enable CONFIG_DISPLAY_CPUINFO for keystone platforms, so that cpu info can be displayed during boot. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Cleanup SoC detectionLokesh Vutla2015-08-121-16/+26
| | | | | | | | | Add proper register definition for JTAG ID and cleanup cpu_is_* functions. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA72: disable workaround for 801819Nishanth Menon2015-08-121-0/+11
| | | | | | | | | | | | | | | | | DRA72x processor variants are single core and it does not export ACP[1]. Hence, we have no source for generating an external snoop requests which appear to be key to the deadlock in DRA72x design. Since we build the same image for DRA74x and DRA72x platforms, lets runtime detect and disable the workaround (in favor of performance) on DRA72x platforms. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7/ OMAP5: implement Auxiliary Control Register configurationNishanth Menon2015-08-122-0/+7
| | | | | | | | | | Implement logic for ACR(Auxiliary Control Register) configuration using ROM Code smc service. Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: Introduce erratum workaround for 801819Nishanth Menon2015-08-122-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add workaround for Cortex-A15 ARM erratum 801819 which says in summary that "A livelock can occur in the L2 cache arbitration that might prevent a snoop from completing. Under certain conditions this can cause the system to deadlock. " Recommended workaround is as follows: Do both of the following: 1) Do not use the write-back no-allocate memory type. 2) Do not issue write-back cacheable stores at any time when the cache is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it is implementation defined whether cacheable stores update the cache when the cache is disabled it is not expected that any portable code will execute cacheable stores when the cache is disabled. For implementations of Cortex-A15 configured without the “L2 arbitration register slice” option (typically one or two core systems), you must also do the following: 3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111 So, we provide an option to disable write streaming on OMAP5 and DRA7. It is a rare condition to occur and may be enabled selectively based on platform acceptance of risk. Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3] is set to 0. Note: certain unicore SoCs *might* not have REVIDR[3] not set, but might not meet the condition for the erratum to occur when they donot have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency Extensions). Such SoCs will need the work around handled in the SoC specific manner, since there is no ARM generic manner to detect such configurations. Based on ARM errata Document revision 18.0 (22 Nov 2013) Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* integrator: switch to DM serial portLinus Walleij2015-08-126-20/+28
| | | | | | | | This switches the Integrator boards over to using the device model for its serial ports. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* usb: ohci: enable cache supportWu, Josh2015-08-122-12/+2
| | | | | | | | Remove the CONFIG_DM_USB limitation to enable cache support functions. Tested on SAMA5D3x-EK board. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* ARM: cache: implement a default weak flush_cache() functionWu, Josh2015-08-125-60/+5
| | | | | | | | | | | | | | | | | Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
* ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh2015-08-125-32/+9
| | | | | | | | | | | | | Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: York Sun <yorksun@freescale.com>
* m68k: cache: add an empty stub functions for invalidate/flush dcacheWu, Josh2015-08-121-0/+9
| | | | | | | | | | | | | | Since some driver like ohci, lcd used dcache functions. But m68k don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all m68k cpu. Also each cpu can implement its own implementation. If not implemented then by default is using an empty function. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Angelo Dureghello <angelo@sysam.it>
* Correct License and Copyright information on few filesRuchika Gupta2015-08-125-4/+7
| | | | | | | | | gpio.h - Added missing copyright in few files. rsa-mod-exp.h - Corrected copyright in the file. fsl_sec.h - Added missing license in files drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
* ti: drop value from CONFIG_SYS_NAND_BUSWIDTH_16BITStefano Babic2015-08-1212-12/+12
| | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mcx: add Ethernet over USBStefano Babic2015-08-121-0/+3
| | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
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