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| * | arm: mvebu: Disable MBUS error propagationStefan Roese2015-08-172-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing MBUS windows not backed-up by e.g. PCIe devices will hang the SoC. Disable MBUS error propagation back to CPU allows to read 0xffffffff instead of hanging the SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Flush caches and disable MMU only on A38xStefan Roese2015-08-171-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only with disabled MMU its possible to switch the base register address on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not accessible, as its still locked to cache. So to fully release / unlock this area from cache, we need to first flush all caches, then disable the MMU and disable the L2 cache. On Armada XP this does not seem to be needed. Even worse, with this code added, I sometimes see strange input charactes loss from the console. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Setup the MBUS bridge registersStefan Roese2015-08-172-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this patch, the MBUS bridge registers (base and size) are configured upon each call to mbus_dt_setup_win(). This is needed, since the board code can also call this function in later boot stages. As done in the maxbcm board. This is needed to fix a problem with the secondary CPU's not booting in Linux on AXP. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Change MBUS base addresses and sizesStefan Roese2015-08-172-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the MBUS base addresses and sizes to use more generic names and also adds defines for the sizes. It also moves the base address to higher addresses. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: db-mv784mp-gp.h: Fix image creation - use correct offsetStefan Roese2015-08-171-0/+1
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese2015-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on the DB-MV784MP-GP eval board. To really enable ECC support on this board the I2C EEPROM needs to get changed. As it saves the enabling of ECC support internally. For this the following commands can be used to enable ECC support on this board: Its recommended for first save (print) the value(s) in this EEPROM address: => i2c md 4e 0.1 2 0000: 05 00 .. To enable ECC support you need to set bit 1 in the 2nd byte: Marvell>> i2c mw 4e 1.1 02 Marvell>> i2c md 4e 0.1 2 0000: 05 02 .. To disable ECC support again, please use this command: Marvell>> i2c mw 4e 1.1 00 Marvell>> i2c md 4e 0.1 2 0000: 05 00 .. On other AXP boards, simply plugging an ECC DIMM should be enough to enable ECC support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu/armada100: dram.c: Remove CONFIG_SYS_BOARD_DRAM_INITStefan Roese2015-08-172-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid of all references here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | Revert "Align global_data to a 16-byte boundary"Simon Glass2015-08-172-3/+1
|/ / | | | | | | | | | | | | | | | | | | This causes widespread breakage due to the operation of the low-level code in crt0.S and cro0_64.S for ARM at least. The fix is not complicated but it seems safer to revert this for now. This reverts commit 2afddae07523f23f77acd066ad1719f53d289f98. Signed-off-by: Simon Glass <sjg@chromium.org>
* | i2c: lpc32xx: fix write timeoutSylvain Lemieux2015-08-171-0/+2
| | | | | | | | | | | | Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_write" when parameters alen = 0 and len = 0. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | i2c: lpc32xx: fix read timeoutSylvain Lemieux2015-08-171-5/+5
| | | | | | | | | | | | Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_read" when parameters alen != 0 and len = 0. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | i2c: lpc32xx: use api to get hclk instead of fix valueSylvain Lemieux2015-08-171-1/+1
| | | | | | | | | | | | The HCLK is not constant and can take different value; use the api function to get the value of the HCLK for the I2C clock high and low computation. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | arm: lpc32xx: gpio macro for pin mappingSylvain Lemieux2015-08-171-0/+40
| | | | | | | | | | | | Add LPC32xx GPIO interface macro for pin mapping. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | lpc32xx: cpu: add support for soft resetSylvain Lemieux2015-08-171-6/+17
| | | | | | | | | | | | | | | | Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset). To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | arm: lpc32xx: mux: add missing registersSylvain Lemieux2015-08-172-1/+18
| | | | | | | | | | | | | | Add missing registers in struct definition. Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011). Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | Delete an accidentally added .rej fileTom Rini2015-08-141-10/+0
|/ | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-08-1439-264/+875
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| * Revert "fdt: Fix fdtdec_get_addr_size() for 64-bit"Simon Glass2015-08-141-36/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5b34436035fc862b5e8d0d2c3eab74ba36f1a7f4. This function has a few problems. It calls fdt_parent_offset() which as mentioned in code review is very slow. https://patchwork.ozlabs.org/patch/499482/ https://patchwork.ozlabs.org/patch/452604/ It also happens to break SPI flash on Minnowboard max which is how I noticed that this was applied. I can send a patch to tidy that up, but in any case I think we should consider a revert until the function is better implemented. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add a simple interrupt script to the READMESimon Glass2015-08-141-0/+15
| | | | | | | | | | | | | | | | | | | | It is a bit tedious to figure out the interrupt configuration for a new x86 platform. Add a script which can do this, based on the output of 'pci long'. This may be helpful in some cases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: minnowmax: Define and enable interrupt setupSimon Glass2015-08-143-4/+69
| | | | | | | | | | | | | | | | Set up interrupts correctly so that Linux can use all devices. Use savedefconfig to regenerate the defconfig file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add clarifications to the x86 READMEStoppa, Igor2015-08-141-11/+21
| | | | | | | | | | | | | | | | | | | | * Explicitly list the targets supported in each section of the instructions from the x86 README. * Drop references to 'raw mode', in favor of 'bare mode'. Signed-off-by: Igor Stoppa <igor.stoppa@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Return -1 when reading a PCI config register failsSimon Glass2015-08-141-3/+6
| | | | | | | | | | | | | | | | This can fail for internal reasons, so return a sensible value rather than a random one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Drop FSP error defines and use EFI insteadSimon Glass2015-08-142-12/+1
| | | | | | | | | | | | | | | | Now that we have an efi.h header we can use that for FSP error defines. Drop the FSP ones. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Set APs' req_seq to the reg number from device treeBin Meng2015-08-141-0/+7
| | | | | | | | | | | | | | | | | | Multiple APs are brought up simultaneously and they may get the same seq num in the uclass_resolve_seq() during device_probe(). To avoid this, set req_seq to the reg number in the device tree in advance. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * video: vesa: Correct a typo in the Kconfig VESA mode stringBin Meng2015-08-141-1/+1
| | | | | | | | | | | | | | There is one typo in the VESA mode 105h string. Correct it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Show the un-relocated IP address in exceptionsSimon Glass2015-08-141-0/+2
| | | | | | | | | | | | | | | | | | | | When trying to figure out where an exception has occured, the relocated address is not a lot of help. Its value depends on various factors. Show the un-relocated IP as well. This can be looked up in System.map directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Convert minnowmax to use CONFIG_DM_NETSimon Glass2015-08-142-6/+1
| | | | | | | | | | | | | | Move to driver model for networking on minnowmax. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Convert minnowmax to use CONFIG_DM_USBSimon Glass2015-08-141-4/+5
| | | | | | | | | | | | | | Move to driver model for USB on minnowmax. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * Revert "dm: pci: Allow scan bridge child devices before relocation"Simon Glass2015-08-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit df189d9ba3f8fd1bc67e3c0c3c4ace16cd065ee1. Unfortunately this commit breaks chromebook_link because it adds lots of PCI devices before relocation and there is not enough pre-reloc malloc() memory. Rathar then increase this memory, revert for now until we figure this out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Switch to using generic global_data setupSimon Glass2015-08-143-84/+18
| | | | | | | | | | | | | | | | | | | | | | There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Move the GDT into global_dataSimon Glass2015-08-142-5/+8
| | | | | | | | | | | | | | | | | | Rather than keeping track of the Global Descriptor Table in its own memory we may as well put it in global_data with everything else. As a first step, stop using the separately allocated GDT. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * Allow arch-specific setting of global_data in board_init_f_mem()Simon Glass2015-08-142-2/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | At present we have a simple assignment to gd. With some archs this is implemented as a register or through some other means; a simple assignment does not suit in all cases. Change this to a function and add documentation to describe how this all works. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * Align global_data to a 16-byte boundarySimon Glass2015-08-142-1/+3
| | | | | | | | | | | | | | | | Some archs like to have larger alignment for their global data. Use 16 bytes which suits all current archs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove init_gd() functionSimon Glass2015-08-141-1/+0
| | | | | | | | | | | | | | This is declared but no-longer exists. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: Support running as an EFI payloadSimon Glass2015-08-141-0/+2
| | | | | | | | | | | | | | | | We should not fiddle with interrupts or the FSP when running as an EFI payload. Detect this and skip this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: Tidy up interrupt and FSP initSimon Glass2015-08-141-1/+8
| | | | | | | | | | | | | | | | We should signal to the FSP that PCI enumeration is complete. Perform this task in a suitable place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow pirq_init() to return an errorSimon Glass2015-08-146-19/+18
| | | | | | | | | | | | | | | | This function can fail. In this case we should return the error rather than swallowing it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Split out fsp_init_phase_pci() code into a new functionSimon Glass2015-08-142-3/+15
| | | | | | | | | | | | | | | | | | | | | | This code may be useful for boards that use driver model for PCI. Note: It would be better to have driver model automatically call this function somehow. However for now it is probably safer to have it under board control. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up the PIRQ routing code a littleSimon Glass2015-08-141-28/+13
| | | | | | | | | | | | | | | | | | This code could use a little tightening up. There is some repetition and an odd use of fdtdec_get_int_array(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Re-order efi-x86_defconfigSimon Glass2015-08-141-5/+5
| | | | | | | | | | | | | | Use savedefconfig to get this file into the correct order. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: pci: Add a way to iterate through all PCI devicesSimon Glass2015-08-142-0/+85
| | | | | | | | | | | | | | | | | | These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: pci: Provide friendly config access functionsSimon Glass2015-08-142-0/+94
| | | | | | | | | | | | | | | | | | At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: fsp: Do not assert VPD_IMAGE_REV when DEBUGBin Meng2015-08-143-4/+1
| | | | | | | | | | | | | | | | | | | | When using different release version of Intel FSP, the VPD_IMAGE_REV is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304). Remove the asserting of this so that U-Boot does not hang in a debug build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Configure FSP UPD from device treeAndrew Bradford2015-08-146-30/+388
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself. Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay Fixed lines >80col Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Add all IDE/SATA PCI device IDsBin Meng2015-08-143-4/+10
| | | | | | | | | | | | | | | | The BayTrail SoC has 4 different PCI devices IDs regarding to IDE and AHCI. Add these IDs in pci_ids.h and also add the other SATA ID in the Bayley Bay and MinnowMax board configuration header. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * common: Display >=4GiB memory bank sizeBin Meng2015-08-142-3/+4
| | | | | | | | | | | | | | | | bd->bi_dram[] has both start address and size defined as 32-bit, which is not the case on some platforms where >=4GiB memory bank is used. Change them to support such memory banks. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-pmicTom Rini2015-08-144-2/+110
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| * | Add missing part of: "power: pmic: pfuze100 support driver model"Peng Fan2015-08-144-2/+110
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This part of mentioned commit, was missed by my mistake during the rebase. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Original commit message: power: pmic: pfuze100 support driver model 1. Support driver model for pfuze100. 2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100 3. This driver intends to support PF100, PF200 and PF3000, so add the device id into the udevice_id array. 4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS. Change-Id: I4fc88414f3c0285f9648e47ec7aed60addeccc4d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | powerpc: ipek01: convert to generic boardAnatolij Gustschin2015-08-142-1/+3
| | | | | | | | | | | | | | Also update maintainer info. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* | powerpc: inka4x0: convert to generic boardAnatolij Gustschin2015-08-142-1/+3
| | | | | | | | | | | | | | Also update maintainer info. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* | powerpc: socrates: convert to generic boardAnatolij Gustschin2015-08-141-0/+2
| | | | | | | | | | Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: York Sun <yorksun@freescale.com>
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