diff options
Diffstat (limited to 'include')
38 files changed, 1444 insertions, 323 deletions
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index a4050f34cc..120fdc6659 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -14,6 +14,8 @@ #define CONFIG_MPC5200 #define CONFIG_A3M071 /* A3M071 board */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index cc88ac1618..3c6765560e 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -19,6 +19,8 @@ #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_A4M072 1 /* ... on A4M072 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 14bac155a3..932a3090b4 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -77,7 +77,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ diff --git a/include/configs/alt.h b/include/configs/alt.h index 7bd649fb42..5c8223c4d9 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -11,60 +11,16 @@ #define __ALT_H #undef DEBUG -#define CONFIG_ARMV7 #define CONFIG_R8A7794 #define CONFIG_RMOBILE_BOARD_STRING "Alt" -#define CONFIG_SH_GPIO_PFC -#include <asm/arch/rmobile.h> - -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_DFL -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_RUN -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI +#include "rcar-gen2-common.h" #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_TEXT_BASE 0x70000000 #else #define CONFIG_SYS_TEXT_BASE 0xE6304000 #endif -#define CONFIG_SYS_THUMB_BUILD -#define CONFIG_SYS_GENERIC_BOARD - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_OF_LIBFDT -#define BOARD_LATE_INIT - -#define CONFIG_BAUDRATE 38400 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "" - -#define CONFIG_VERSION_VARIABLE -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_TMU_TIMER #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC @@ -76,40 +32,14 @@ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ -#define ALT_SDRAM_BASE 0x40000000 -#define ALT_SDRAM_SIZE (1024u * 1024 * 1024) -#define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE 512 -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF2 -#undef CONFIG_SYS_CONSOLE_INFO_QUIET -#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -#define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 504 * 1024 * 1024) -#undef CONFIG_SYS_ALT_MEMTEST -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) +#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SPI @@ -120,17 +50,6 @@ #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH -/* ENV setting */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_ADDR 0xC0000 -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_low=0x40e00000\0" \ - "bootm_size=0x100000\0" \ - /* SH Ether */ #define CONFIG_NET_MULTI #define CONFIG_SH_ETHER @@ -151,7 +70,7 @@ #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 @@ -161,11 +80,8 @@ #define CONFIG_SYS_I2C_SH #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 #define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 #define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 #define CONFIG_SYS_I2C_SH_SPEED2 400000 #define CONFIG_SH_I2C_DATA_HIGH 4 #define CONFIG_SH_I2C_DATA_LOW 5 @@ -173,10 +89,6 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ -/* Filesystems */ -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT - /* USB */ #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index a30c016b41..735c82aa8d 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -61,6 +61,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory Configuration */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 73917b0ec1..a6a80de88a 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -48,6 +48,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO @@ -135,7 +137,6 @@ #ifndef CONFIG_AT91SAM9G20EK_2MMC #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 226f8c1612..407a53e555 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -33,6 +33,8 @@ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_ATMEL_LEGACY #define CONFIG_SYS_TEXT_BASE 0x21f00000 @@ -107,7 +109,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index b666d9494d..fa19e8bcc8 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -119,7 +119,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index b8d5dd156f..d5f0197466 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -100,7 +100,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 diff --git a/include/configs/corvus.h b/include/configs/corvus.h index eb1584d3cc..5b50c1d6dd 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -19,7 +19,6 @@ #define MACH_TYPE_CORVUS 2066 #define CONFIG_SYS_GENERIC_BOARD - /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. @@ -27,7 +26,7 @@ * hex number here! */ -#define CONFIG_SYS_TEXT_BASE 0x73f00000 +#define CONFIG_SYS_TEXT_BASE 0x72000000 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -107,8 +106,6 @@ /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 - #endif /* Ethernet */ @@ -159,5 +156,54 @@ */ #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ 128*1024, 0x1000) +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE (12 * 1024) +#define CONFIG_SPL_STACK (16 * 1024) + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_BSS_MAX_SIZE (2 * 1024) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_SIZE (256*1024*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0 #endif diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index af0d60249a..a9cfc10d0c 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -35,6 +35,7 @@ /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ @@ -59,8 +60,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 4c69af6af3..ce61a1621c 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -78,7 +78,6 @@ /* SPI */ #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define AT91_SPI_CLK 15000000 /* Serial port */ diff --git a/include/configs/gose.h b/include/configs/gose.h new file mode 100644 index 0000000000..c347e45346 --- /dev/null +++ b/include/configs/gose.h @@ -0,0 +1,94 @@ +/* + * include/configs/gose.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __GOSE_H +#define __GOSE_H + +#undef DEBUG +#define CONFIG_R8A7793 +#define CONFIG_RMOBILE_BOARD_STRING "Gose" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +/* STACK */ +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#endif + +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE 0x40000000 +#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000 + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF0 +#define CONFIG_SCIF_USE_EXT_CLK + +/* FLASH */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SPI +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_SPANSION + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#endif /* __GOSE_H */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h new file mode 100644 index 0000000000..e7df9ad92a --- /dev/null +++ b/include/configs/hrcon.h @@ -0,0 +1,614 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ +#define CONFIG_HRCON 1 /* HRCON board specific */ + +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + +#define CONFIG_IDENT_STRING " hrcon 0.01" + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_LAST_STAGE_INIT + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + +#define CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 + +#define CONFIG_CMD_FPGAD +#define CONFIG_CMD_IOLOOP + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.66MHz, then + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz + * We choose the A type silicon as default, so the core is 400Mhz. + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CORE_TO_CSB_3X1) +/* + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits + * in 8308's HRCWH according to the manual, but original Freescale's + * code has them and I've expirienced some problems using the board + * with BDI3000 attached when I've tried to set these bits to zero + * (UART doesn't work after the 'reset run' command). + */ +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH (\ + SICRH_ESDHC_A_SD |\ + SICRH_ESDHC_B_SD |\ + SICRH_ESDHC_C_SD |\ + SICRH_GPIO_A_GPIO |\ + SICRH_GPIO_B_GPIO |\ + SICRH_IEEE1588_A_GPIO |\ + SICRH_USB |\ + SICRH_GTM_GPIO |\ + SICRH_IEEE1588_B_GPIO |\ + SICRH_ETSEC2_GPIO |\ + SICRH_GPIOSEL_1 |\ + SICRH_TMROBI_V3P3 |\ + SICRH_TSOBI1_V2P5 |\ + SICRH_TSOBI2_V2P5) /* 0x0037f103 */ +#define CONFIG_SYS_SICRL (\ + SICRL_SPI_PF0 |\ + SICRL_UART_PF0 |\ + SICRL_IRQ_PF0 |\ + SICRL_I2C2_PF0 |\ + SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * SERDES + */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * Arbiter Setup + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of one chip NT5TU64M16HG from NANYA + */ + +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ + +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_BANK_BIT_3 \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ +#define CONFIG_SYS_DDR_TIMING_3 0 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00260802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (7 << TIMING_CFG1_CASLAT_SHIFT) \ + | (9 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x26279222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (4 << TIMING_CFG2_CPO_SHIFT) \ + | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x021848c5 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x08240100 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_16) + /* 0x43100000 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0242 << SDRAM_MODE_SD_SHIFT)) + /* ODT 150ohm CL=4, AL=0 on SDRAM */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR 0x00040000 + +/* + * FLASH on the Local Bus + */ +#if 1 +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#else +#define CONFIG_SYS_NO_FLASH +#endif + +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ + +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * FPGA + */ +#define CONFIG_SYS_FPGA0_BASE 0xE0600000 +#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ + +/* Window base at FPGA base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET) + +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_FPGA_DONE(k) 0x0010 + +#define CONFIG_SYS_FPGA_COUNT 1 + +#define CONFIG_SYS_MCLINK_MAX 3 + +#define CONFIG_SYS_FPGA_PTR \ + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 + +#define CONFIG_PCA953X /* NXP PCA9554 */ +#define CONFIG_PCA9698 /* NXP PCA9698 */ + +#define CONFIG_SYS_I2C_IHS +#define CONFIG_SYS_I2C_IHS_CH0 +#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS_CH1 +#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH2 +#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F +#define CONFIG_SYS_I2C_IHS_CH3 +#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F +#define I2C_SOFT_DECLARATIONS2 +#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F +#define I2C_SOFT_DECLARATIONS3 +#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F +#define I2C_SOFT_DECLARATIONS4 +#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F + +#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} +#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} +#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} + +#ifndef __ASSEMBLY__ +void fpga_gpio_set(unsigned int bus, int pin); +void fpga_gpio_clear(unsigned int bus, int pin); +int fpga_gpio_get(unsigned int bus, int pin); +#endif + +#define I2C_ACTIVE { } +#define I2C_TRISTATE { } +#define I2C_READ \ + (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \ + else \ + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \ + } while (0) +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \ + else \ + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \ + } while (0) +#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ + +/* + * Software (bit-bang) MII driver configuration + */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII_MULTI + +/* + * OSD Setup + */ +#define CONFIG_SYS_OSD_SCREENS 1 +#define CONFIG_SYS_DP501_DIFFERENTIAL +#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +/* enable PCIE clock */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 1 + +#define CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +/* + * Environment + */ +#if 1 +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#else +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#define CONFIG_AUTOBOOT_STOP_STR " " + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define CONFIG_HOSTNAME hrcon +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "kernel_addr=1000000\0" \ + "fdt_addr=C00000\0" \ + "fdtfile=hrcon.dtb\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp ${kernel_addr} $bootfile;" \ + "tftp ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + + +#endif /* __CONFIG_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 3ccadd0af7..bb983022ee 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -10,33 +10,10 @@ #define __KOELSCH_H #undef DEBUG -#define CONFIG_ARMV7 #define CONFIG_R8A7791 #define CONFIG_RMOBILE_BOARD_STRING "Koelsch" -#define CONFIG_SH_GPIO_PFC -#include <asm/arch/rmobile.h> - -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_DFL -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_RUN -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI - -#define CONFIG_FAT_WRITE -#define CONFIG_EXT4_WRITE +#include "rcar-gen2-common.h" #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_TEXT_BASE 0x70000000 @@ -44,35 +21,6 @@ #define CONFIG_SYS_TEXT_BASE 0xE6304000 #endif -#define CONFIG_SYS_THUMB_BUILD -#define CONFIG_SYS_GENERIC_BOARD - -/* Support File sytems */ -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT - - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_OF_LIBFDT -#define BOARD_LATE_INIT - -#define CONFIG_BAUDRATE 38400 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "" - -#define CONFIG_VERSION_VARIABLE -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_TMU_TIMER - /* STACK */ #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC @@ -85,41 +33,14 @@ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ -#define KOELSCH_SDRAM_BASE 0x40000000 -#define KOELSCH_SDRAM_SIZE (2048u * 1024 * 1024) -#define KOELSCH_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE 512 -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF0 #define CONFIG_SCIF_USE_EXT_CLK -#undef CONFIG_SYS_CONSOLE_INFO_QUIET -#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -#define CONFIG_SYS_MEMTEST_START (KOELSCH_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 504 * 1024 * 1024) -#undef CONFIG_SYS_ALT_MEMTEST -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (KOELSCH_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (KOELSCH_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ #define CONFIG_SYS_NO_FLASH @@ -128,16 +49,6 @@ #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR #define CONFIG_SPI_FLASH_SPANSION -/* ENV setting */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_ADDR 0xC0000 - -/* Common ENV setting */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) /* SH Ether */ #define CONFIG_NET_MULTI @@ -166,11 +77,8 @@ #define CONFIG_SYS_I2C_SH #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 #define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 #define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 #define CONFIG_SYS_I2C_SH_SPEED2 400000 #define CONFIG_SH_I2C_DATA_HIGH 4 #define CONFIG_SH_I2C_DATA_LOW 5 diff --git a/include/configs/lager.h b/include/configs/lager.h index a814b4cccc..37be38f533 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -2,7 +2,7 @@ * include/configs/lager.h * This file is lager board configuration. * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013, 2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -11,67 +11,16 @@ #define __LAGER_H #undef DEBUG -#define CONFIG_ARMV7 #define CONFIG_R8A7790 #define CONFIG_RMOBILE_BOARD_STRING "Lager" -#define CONFIG_SH_GPIO_PFC -#include <asm/arch/rmobile.h> - -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_DFL -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_RUN -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI - -#define CONFIG_FAT_WRITE -#define CONFIG_EXT4_WRITE +#include "rcar-gen2-common.h" #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_TEXT_BASE 0xB0000000 #else #define CONFIG_SYS_TEXT_BASE 0xE8080000 #endif -#define CONFIG_SYS_THUMB_BUILD -#define CONFIG_SYS_GENERIC_BOARD - -/* Support File sytems */ -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_OF_LIBFDT - -/* #define CONFIG_OF_LIBFDT */ -#define BOARD_LATE_INIT - -#define CONFIG_BAUDRATE 38400 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "" - -#define CONFIG_VERSION_VARIABLE -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_TMU_TIMER /* STACK */ #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) @@ -84,43 +33,16 @@ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ -#define LAGER_SDRAM_BASE 0x40000000 -#define LAGER_SDRAM_SIZE (2048u * 1024 * 1024) -#define LAGER_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE 512 -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF0 #define CONFIG_SCIF_USE_EXT_CLK -#undef CONFIG_SYS_CONSOLE_INFO_QUIET -#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -#define CONFIG_SYS_MEMTEST_START (LAGER_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 504 * 1024 * 1024) -#undef CONFIG_SYS_ALT_MEMTEST -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (LAGER_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (LAGER_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* USE SPI */ +/* SPI */ #define CONFIG_SPI #define CONFIG_SPI_FLASH_BAR #define CONFIG_SH_QSPI @@ -128,17 +50,6 @@ #define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SYS_NO_FLASH -/* ENV setting */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_ADDR 0xC0000 - -/* Common ENV setting */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) - /* SH Ether */ #define CONFIG_NET_MULTI #define CONFIG_SH_ETHER @@ -156,13 +67,9 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_RCAR -#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 86ce5f2397..955d0e278a 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -124,7 +124,6 @@ #ifdef CONFIG_SYS_USE_DATAFLASH # define CONFIG_ATMEL_DATAFLASH_SPI # define CONFIG_HAS_DATAFLASH -# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) # define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 # define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ # define AT91_SPI_CLK 15000000 diff --git a/include/configs/otc570.h b/include/configs/otc570.h index 629967d054..2390bebf91 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -174,7 +174,6 @@ #ifdef CONFIG_SYS_USE_DATAFLASH # define CONFIG_ATMEL_DATAFLASH_SPI # define CONFIG_HAS_DATAFLASH -# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) # define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 # define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ # define AT91_SPI_CLK 15000000 diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 4a71927217..0746056d0a 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -202,7 +202,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index d9c04d14b9..f0f12afb81 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -216,7 +216,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h new file mode 100644 index 0000000000..46c7526677 --- /dev/null +++ b/include/configs/rcar-gen2-common.h @@ -0,0 +1,95 @@ +/* + * include/configs/rcar-gen2-common.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __RCAR_GEN2_COMMON_H +#define __RCAR_GEN2_COMMON_H + +#include <asm/arch/rmobile.h> + +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_RUN +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI + +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_GENERIC_BOARD + +/* Support File sytems */ +#define CONFIG_FAT_WRITE +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT +#define CONFIG_EXT4_WRITE + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_OF_LIBFDT + +#define CONFIG_BAUDRATE 38400 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_TMU_TIMER +#define CONFIG_SH_GPIO_PFC + +/* console */ +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } + +#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* ENV setting */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_ADDR 0xC0000 + +/* Common ENV setting */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) + +#endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index 5436324580..e7f73872ee 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -11,7 +11,6 @@ #define __RSK7203_H #undef DEBUG -#define CONFIG_SH2A 1 #define CONFIG_CPU_SH7203 1 #define CONFIG_RSK7203 1 diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h index 4aaa3ef74b..2ecf785082 100644 --- a/include/configs/rsk7264.h +++ b/include/configs/rsk7264.h @@ -12,7 +12,6 @@ #define __RSK7264_H #undef DEBUG -#define CONFIG_SH2A 1 #define CONFIG_CPU_SH7264 1 #define CONFIG_RSK7264 1 diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h index 11fc231fa6..14c1da774d 100644 --- a/include/configs/rsk7269.h +++ b/include/configs/rsk7269.h @@ -11,7 +11,6 @@ #define __RSK7269_H #undef DEBUG -#define CONFIG_SH2A 1 #define CONFIG_CPU_SH7269 1 #define CONFIG_RSK7269 1 diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h new file mode 100644 index 0000000000..104edef102 --- /dev/null +++ b/include/configs/sama5d4_xplained.h @@ -0,0 +1,216 @@ +/* + * Configuration settings for the SAMA5D4 Xplained ultra board. + * + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART3 +#define CONFIG_USART_ID ATMEL_ID_USART3 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETEXPR + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SerialFlash */ +#define CONFIG_CMD_SF + +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#endif + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +/* #define CONFIG_LCD */ +#ifdef CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_SYS_USE_SERIALFLASH +/* bootstrap + u-boot + env + linux in serial flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0xa0000 0x60000; " \ + "sf read 0x22000000 0x100000 0x300000; " \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +/* + * We don't specify the part number, if device 0 has partition table, it means + * the first partition; it no partition table, then take whole device as a + * FAT file system. + */ +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d4_xplained.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h new file mode 100644 index 0000000000..cbdb3a2943 --- /dev/null +++ b/include/configs/sama5d4ek.h @@ -0,0 +1,214 @@ +/* + * Configuration settings for the SAMA5D4EK board. + * + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART3 +#define CONFIG_USART_ID ATMEL_ID_USART3 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETEXPR + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SerialFlash */ +#define CONFIG_CMD_SF + +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#endif + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +#define CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 18 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#ifdef CONFIG_SYS_USE_SERIALFLASH +/* bootstrap + u-boot + env + linux in serial flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0xa0000 0x60000; " \ + "sf read 0x22000000 0x100000 0x300000; " \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +/* + * We don't specify the part number, if device 0 has partition table, it means + * the first partition; it no partition table, then take whole device as a + * FAT file system. + */ +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 sama5d4ek.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index a1b5751d09..e7c35eca39 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -80,7 +80,6 @@ #define CONFIG_SPI #define CONFIG_CMD_SPI #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_CMD_EEPROM #define CONFIG_SPI_M95XXX diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index f06abbca0c..2d509a9b9c 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -10,7 +10,6 @@ #define __SH7752EVB_H #undef DEBUG -#define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7752 1 #define CONFIG_SH7752EVB 1 diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index e400db08ad..c31dd7a174 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -10,7 +10,6 @@ #define __SH7753EVB_H #undef DEBUG -#define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7753 1 #define CONFIG_SH7753EVB 1 diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 08bff1da3f..36afd5f70a 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -10,7 +10,6 @@ #define __SH7757LCR_H #undef DEBUG -#define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7757 1 #define CONFIG_SH7757LCR 1 #define CONFIG_SH7757LCR_DDR_ECC 1 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index aadf4cd2f8..20194aebb5 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -34,7 +34,7 @@ */ -#define CONFIG_SYS_TEXT_BASE 0x23f00000 +#define CONFIG_SYS_TEXT_BASE 0x21000000 /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ @@ -127,6 +127,16 @@ #define CONFIG_USB_STORAGE #endif +/* SPI EEPROM */ +#define CONFIG_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_ATMEL_SPI +#define CONFIG_SPI_FLASH_STMICRO +#define TAURUS_SPI_MASK (1 << 4) +#define TAURUS_SPI_CS_PIN AT91_PIN_PA3 + /* load address */ #define CONFIG_SYS_LOAD_ADDR 0x22000000 @@ -158,4 +168,54 @@ #define CONFIG_SYS_MALLOC_LEN \ ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (11 * 1024) +#define CONFIG_SPL_STACK (16 * 1024) + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_USE_NANDFLASH 1 +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_SIZE (256*1024*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x202A3F01 +#define CONFIG_SYS_MCKR 0x1300 +#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) +#define CONFIG_SYS_AT91_PLLB 0x10193F05 #endif diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 32f6b00bbf..79c7fc5129 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -85,7 +85,6 @@ #define CONFIG_SPI #define CONFIG_CMD_SPI #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_CMD_EEPROM #define CONFIG_SPI_M95XXX diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 3c54870783..84571f6e93 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -85,7 +85,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 #define AT91_SPI_CLK 8000000 diff --git a/include/flash.h b/include/flash.h index 5454c9ea21..30aa080b88 100644 --- a/include/flash.h +++ b/include/flash.h @@ -158,6 +158,7 @@ extern flash_info_t *flash_get_info(ulong base); #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ #define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ #define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ +#define EON_ALT_MANU 0x001C001C /* EON manuf. ID in D23..D16, D7..D0 */ /* Manufacturers inside bank 1 have ids like 0x01xx01xx */ #define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 276a01e744..8a5efe732a 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -61,6 +61,22 @@ struct ihs_osd { u16 y_pos; }; +struct ihs_mdio { + u16 control; + u16 address_data; + u16 rx_data; +}; + +struct ihs_io_ep { + u16 transmit_data; + u16 rx_tx_control; + u16 receive_data; + u16 rx_tx_status; + u16 reserved; + u16 device_address; + u16 target_address; +}; + #ifdef CONFIG_NEO struct ihs_fpga { u16 reflection_low; /* 0x0000 */ @@ -119,12 +135,50 @@ struct ihs_fpga { u16 versions; /* 0x0002 */ u16 fpga_version; /* 0x0004 */ u16 fpga_features; /* 0x0006 */ - u16 reserved_0[6]; /* 0x0008 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[4]; /* 0x000c */ + struct ihs_gpio gpio; /* 0x0014 */ + u16 mpc3w_control; /* 0x001a */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ + struct ihs_i2c i2c; /* 0x0040 */ + u16 reserved_4[10]; /* 0x004c */ + u16 mc_int; /* 0x0060 */ + u16 mc_int_en; /* 0x0062 */ + u16 mc_status; /* 0x0064 */ + u16 mc_control; /* 0x0066 */ + u16 mc_tx_data; /* 0x0068 */ + u16 mc_tx_address; /* 0x006a */ + u16 mc_tx_cmd; /* 0x006c */ + u16 mc_res; /* 0x006e */ + u16 mc_rx_cmd_status; /* 0x0070 */ + u16 mc_rx_data; /* 0x0072 */ + u16 reserved_5[69]; /* 0x0074 */ + u16 reflection_high; /* 0x00fe */ + struct ihs_osd osd; /* 0x0100 */ + u16 reserved_6[889]; /* 0x010e */ + u16 videomem[31736]; /* 0x0800 */ +}; +#endif + +#ifdef CONFIG_HRCON +struct ihs_fpga { + u16 reflection_low; /* 0x0000 */ + u16 versions; /* 0x0002 */ + u16 fpga_version; /* 0x0004 */ + u16 fpga_features; /* 0x0006 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[4]; /* 0x000c */ struct ihs_gpio gpio; /* 0x0014 */ u16 mpc3w_control; /* 0x001a */ - u16 reserved_1[18]; /* 0x001c */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ struct ihs_i2c i2c; /* 0x0040 */ - u16 reserved_2[10]; /* 0x004c */ + u16 reserved_4[10]; /* 0x004c */ u16 mc_int; /* 0x0060 */ u16 mc_int_en; /* 0x0062 */ u16 mc_status; /* 0x0064 */ @@ -135,10 +189,10 @@ struct ihs_fpga { u16 mc_res; /* 0x006e */ u16 mc_rx_cmd_status; /* 0x0070 */ u16 mc_rx_data; /* 0x0072 */ - u16 reserved_3[69]; /* 0x0074 */ + u16 reserved_5[69]; /* 0x0074 */ u16 reflection_high; /* 0x00fe */ struct ihs_osd osd; /* 0x0100 */ - u16 reserved_4[889]; /* 0x010e */ + u16 reserved_6[889]; /* 0x010e */ u16 videomem[31736]; /* 0x0800 */ }; #endif diff --git a/include/nand.h b/include/nand.h index fc735d1ec4..15e31ab538 100644 --- a/include/nand.h +++ b/include/nand.h @@ -167,3 +167,4 @@ __attribute__((noreturn)) void nand_boot(void); #define ENV_OFFSET_SIZE 8 int get_nand_env_oob(nand_info_t *nand, unsigned long *result); #endif +int spl_nand_erase_one(int block, int page); diff --git a/include/sh_tmu.h b/include/sh_tmu.h index 61afc7136d..97d578dd55 100644 --- a/include/sh_tmu.h +++ b/include/sh_tmu.h @@ -25,7 +25,7 @@ #include <asm/types.h> -#if defined(CONFIG_SH3) +#if defined(CONFIG_CPU_SH3) struct tmu_regs { u8 tocr; u8 reserved0; @@ -45,9 +45,9 @@ struct tmu_regs { u16 reserved4; u32 tcpr2; }; -#endif /* CONFIG_SH3 */ +#endif /* CONFIG_CPU_SH3 */ -#if defined(CONFIG_SH4) || defined(CONFIG_RMOBILE) +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_RMOBILE) struct tmu_regs { u32 reserved; u8 tstr; @@ -65,7 +65,7 @@ struct tmu_regs { u16 tcr2; u16 reserved5; }; -#endif /* CONFIG_SH4 */ +#endif /* CONFIG_CPU_SH4 */ static inline unsigned long get_tmu0_clk_rate(void) { diff --git a/include/spl.h b/include/spl.h index 16b3566a94..b2e5bf726f 100644 --- a/include/spl.h +++ b/include/spl.h @@ -35,6 +35,7 @@ extern struct spl_image_info spl_image; void preloader_console_init(void); u32 spl_boot_device(void); u32 spl_boot_mode(void); +void spl_set_header_raw_uboot(void); void spl_parse_image_header(const struct image_header *header); void spl_board_prepare_for_linux(void); void __noreturn jump_to_image_linux(void *arg); |
