19 files changed, 274 insertions, 73 deletions
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 2450adb7d3..1b745265dc 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -287,11 +287,6 @@
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #endif	/* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 38be10d54e..c4389cc446 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -41,6 +41,7 @@
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -134,14 +135,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
 #define CONFIG_SYS_DDR_SBE		0x00010000
 
-/* FIXME: Not used in fixed_sdram function */
-#define CONFIG_SYS_DDR_MODE		0x00000022
-#define CONFIG_SYS_DDR_CS1_BNDS	0x00000000
-#define CONFIG_SYS_DDR_CS2_BNDS	0x00000FFF	/* Not done */
-#define CONFIG_SYS_DDR_CS3_BNDS	0x00000FFF	/* Not done */
-#define CONFIG_SYS_DDR_CS4_BNDS	0x00000FFF	/* Not done */
-#define CONFIG_SYS_DDR_CS5_BNDS	0x00000FFF	/* Not done */
-
 /* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
@@ -314,11 +307,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5a14969a6c..79a52d9d1d 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -46,6 +46,7 @@
 #endif
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index eede26a66c..7ada8a222b 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -38,6 +38,7 @@
 #define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 0987448b71..cdbbea60d6 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -41,6 +41,7 @@
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -275,11 +276,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 892c52e610..083afba9a3 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -43,6 +43,7 @@
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -419,11 +420,6 @@ extern unsigned long get_clock_freq(void);
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #endif	/* CONFIG_PCI */
 
 
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 41870f1e25..f9419ccd0f 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -38,6 +38,7 @@
 #define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 0d3a5009b9..f67d489636 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -43,6 +43,7 @@
 #define CONFIG_MPC8560		1
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index ba2f1525c8..ab3e6d6948 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -38,6 +38,7 @@
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
@@ -388,11 +389,6 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE     0x80000000
-
 #endif	/* CONFIG_PCI */
 
 #ifndef CONFIG_NET_MULTI
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 5688589960..eefb06c67a 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -42,6 +42,7 @@
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -135,16 +136,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_DDR_SBE		0x00010000
 
 /*
- * FIXME: Not used in fixed_sdram function
- */
-#define CONFIG_SYS_DDR_MODE		0x00000022
-#define CONFIG_SYS_DDR_CS1_BNDS	0x00000000
-#define CONFIG_SYS_DDR_CS2_BNDS	0x00000FFF	/* Not done */
-#define CONFIG_SYS_DDR_CS3_BNDS	0x00000FFF	/* Not done */
-#define CONFIG_SYS_DDR_CS4_BNDS	0x00000FFF	/* Not done */
-#define CONFIG_SYS_DDR_CS5_BNDS	0x00000FFF	/* Not done */
-
-/*
  * Make sure required options are set
  */
 #ifndef CONFIG_SPD_EEPROM
@@ -335,11 +326,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 #define CONFIG_SYS_PCIE3_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BASE
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 678e1e151a..fe80e5d21f 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -41,6 +41,7 @@
 #define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
 #define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 #define CONFIG_ENV_OVERWRITE
@@ -278,11 +279,6 @@
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 /* For RTL8139 */
 #define KSEG1ADDR(x)	({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
 #define _IO_BASE		0x00000000
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index e5710c0073..80c8beebd8 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -49,6 +49,7 @@
 #define CONFIG_PCI1		1	/* PCIE controler 1 (ULI bridge) */
 #define CONFIG_PCI2		1	/* PCIE controler 2 (slot) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
@@ -304,11 +305,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 /* For RTL8139 */
 #define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 #define _IO_BASE		0x00000000
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index b05f43d560..2d4048a928 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -403,11 +403,6 @@
 #define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
 #define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/*  16M			*/
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #ifdef CONFIG_PCIE1
 /*
  * General PCI express
diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h
new file mode 100644
index 0000000000..d45e7a0efd
--- /dev/null
+++ b/include/configs/fx12mm.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2008
+ *
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com
+ *
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*
+   Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec,
+   see http://www.em.avnet.com
+*/
+
+#ifndef __CONFIG_FX12_H
+#define __CONFIG_FX12_H
+
+#include "../board/avnet/fx12mm/xparameters.h"
+
+/* cmd config */
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#undef CONFIG_CMD_NET
+
+/* sdram */
+#define CONFIG_SYS_SDRAM_SIZE_MB       64
+
+/* environment */
+#define CONFIG_ENV_IS_IN_FLASH  1
+#define CONFIG_ENV_SIZE         0x10000
+#define CONFIG_ENV_SECT_SIZE    0x10000
+#define CONFIG_SYS_ENV_OFFSET   0xA0000
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
+#define CONFIG_ENV_OVERWRITE 	1
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT	"FX12MM:/# " /* Monitor Command Prompt */
+#define CONFIG_PREBOOT      	"echo U-Boot is up and runnining;"
+
+/*Flash*/
+#define CONFIG_SYS_FLASH_BASE          XPAR_FLASH_2MX16_MEM0_BASEADDR
+#define CONFIG_SYS_FLASH_SIZE          (4*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT      71
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define MTDIDS_DEFAULT		"nor0=fx12mm-flash"
+#define MTDPARTS_DEFAULT	"mtdparts=fx12mm-flash:-(user)"
+
+
+#include "configs/xilinx-ppc405.h"
+
+#endif                          /* __CONFIG_H */
+
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 237a9c56a3..b943f3153b 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -235,9 +235,16 @@
  *
  * DDR Autocalibration Method_B is the default.
  */
+#if 0
+/*
+ * Needs FIX!!!
+ * Disable autocalibration for now, because of the unresolved problem
+ * with kilauea board using 200MHz PLB/DDR2 frequency
+ */
 #define	CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration */
 #define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
 #undef	CONFIG_PPC4xx_DDR_METHOD_A
+#endif
 
 #define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 54f3e66cee..aefd30a1ed 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -387,11 +387,6 @@
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
 #endif	/* CONFIG_PCI */
 
 
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 14d1c882b2..09a990111b 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -308,11 +308,6 @@
 #define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
 #define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/* 16M */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE     0x80000000
-
 #define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h
new file mode 100644
index 0000000000..5036c62546
--- /dev/null
+++ b/include/configs/xilinx-ppc405-generic.h
@@ -0,0 +1,58 @@
+/*
+ *
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * (C) Copyright 2008
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_GEN_H
+#define __CONFIG_GEN_H
+
+#include "../board/xilinx/ppc405-generic/xparameters.h"
+
+/* sdram */
+#define CONFIG_SYS_SDRAM_SIZE_MB	256
+
+/* environment */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_SYS_ENV_OFFSET		0x3F0000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
+#define CONFIG_ENV_OVERWRITE		1
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT	"xlx-ppc405:/# " /* Monitor Command Prompt */
+#define CONFIG_PREBOOT		"echo U-Boot is up and runnining;"
+
+/*Flash*/
+#define CONFIG_SYS_FLASH_BASE			XPAR_FLASH_MEM0_BASEADDR
+#define CONFIG_SYS_FLASH_SIZE		(32*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define MTDIDS_DEFAULT			"nor0=ppc405-flash"
+#define MTDPARTS_DEFAULT		"mtdpartsa=ppc405-flash:-(user)"
+
+#include <configs/xilinx-ppc405.h>
+#endif			/* __CONFIG_H */
diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h
new file mode 100644
index 0000000000..74584705cc
--- /dev/null
+++ b/include/configs/xilinx-ppc405.h
@@ -0,0 +1,126 @@
+/*
+ *
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * (C) Copyright 2008
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* cpu parameter */
+#define CONFIG_4xx		1
+#define CONFIG_405		1
+#define CONFIG_XILINX_405	1
+
+/* memory map */
+#define CONFIG_SYS_SDRAM_BASE	0x0
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN	(192 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128 * 1024)
+
+/* u-boot commands configuration */
+#include <config_cmd_default.h>
+
+/*Misc*/
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END	0x00C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_LOAD_ADDR	0x01000000 /* default load address */
+#define CONFIG_SYS_EXTBDINFO	1	/* Extended board_into (bd_t) */
+#define CONFIG_SYS_HZ		1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING		/* add command line history */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+#define CONFIG_LOOPW			/* enable loopw command */
+#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE		/* include version env variable */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+					/* Initial Memory map for Linux */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SHIFT	2
+
+/* stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x800000 /* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_END		0x2000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+		CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_FLASH_CF		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/* serial communication */
+#ifdef XPAR_UARTLITE_0_BASEADDR
+#define CONFIG_XILINX_UARTLITE
+#define CONFIG_SERIAL_BASE		XPAR_UARTLITE_0_BASEADDR
+#define CONFIG_BAUDRATE			XPAR_UARTLITE_0_BAUDRATE
+#define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+#else
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		XPAR_UARTNS550_0_BASEADDR
+#define CONFIG_SYS_NS16550_CLK		XPAR_UARTNS550_0_CLOCK_FREQ_HZ
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 115200 }
+#endif
+#endif
+
+/* cmd config */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_IMLS
+
+#endif