diff options
Diffstat (limited to 'include/configs')
105 files changed, 1221 insertions, 7305 deletions
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h deleted file mode 100644 index 304a12bea9..0000000000 --- a/include/configs/CPCI750.h +++ /dev/null @@ -1,609 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2004 esd gmbh Hannover - * - * - * from db64360.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - ************************************************************************/ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#ifndef __ASSEMBLY__ -#include <../board/Marvell/include/core.h> -#endif -/*-----------------------------------------------------*/ - -#include "../board/esd/cpci750/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_750FX /* we have a 750FX (override local.h) */ - -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ - -#define CONFIG_MV64360_ECC /* enable ECC support */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_PRE_INIT -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CONFIG_SYS_BOARD_NAME "CPCI750" -#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" - -/*#define CONFIG_SYS_HUSH_PARSER*/ -#define CONFIG_SYS_HUSH_PARSER - - -#define CONFIG_CMDLINE_EDITING /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ - -/* Define which ETH port will be used for connecting the network */ -#define CONFIG_SYS_ETH_PORT ETH_0 - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define MV_ETH_DEVS 1 -#define CONFIG_ETHER_PORT 0 - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#define CONFIG_BOOTDELAY 5 /* autoboot disabled */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS - -/* ----------------------------------------------------------------------------- - * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus - */ - -#define CONFIG_IPADDR "192.168.0.185" - -#define CONFIG_SERIAL "AA000001" -#define CONFIG_SERVERIP "10.0.0.79" -#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* ----------------------------------------------------------------------------- */ - - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - - -#define CONFIG_DOS_PARTITION - -#define CONFIG_USE_CPCIDVI - -#ifdef CONFIG_USE_CPCIDVI -#define CONFIG_VIDEO -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VIDEO_LOGO -#define CONFIG_I8042_KBD -#define CONFIG_SYS_ISA_IO 0 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */ - -#define CONFIG_PRAM 0 - -#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -/*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ - -/* -#define CONFIG_SYS_DRAM_TEST - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ - -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_TCLK 133000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - - /* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#undef CONFIG_SYS_INIT_RAM_LOCK -/* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ -/* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR -/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/ -#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CONFIG_SYS_SDRAM2_BASE 0x20000000 -#define CONFIG_SYS_SDRAM3_BASE 0x30000000 -#define CONFIG_SYS_SDRAM4_BASE 0x40000000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE 0xfff00000 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \ - CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \ - CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the cpci750 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ - -#undef MARVEL_STANDARD_CFG -#ifndef MARVEL_STANDARD_CFG -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -/*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ -#define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ - -#define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ -#define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ -#define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ -#define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ -#define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ - -#define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */ -#define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */ -#define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#endif - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */ -#define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* MPP Control MV64360 Appendix P P. 632*/ -#define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */ -#define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */ -#define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */ -#define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */ -/* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */ - - -#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ - -/* setup new config_value for MV64360 DDR-RAM To_do !! */ -/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ -/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ - /* GB has high prio. - idma has low prio - MPSC has low prio - pci has low prio 1 and 2 - cpu has high prio - Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices - ECC disable - non registered DRAM */ - /* 31:26 25:22 21:20 19 18 17 16 */ - /* 100001 0000 010 0 0 0 0 */ - /* refresh_count=0x400 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 0 1 0x400 */ -# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) - -#if defined (CONFIG_750CX) -#define CONFIG_SYS_PCI_IDSEL 0x0 -#else -#define CONFIG_SYS_PCI_IDSEL 0x30 -#endif - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* no reset for ide supported */ -#define CONFIG_IDE_PREINIT /* check for units */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ -#ifndef __ASSEMBLY__ -int ata_device(int dev); -#endif -#define ATA_DEVICE(dev) ata_device(dev) -#define CONFIG_ATAPI 1 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) - * IBAT4 and DBAT4 - * FIXME: ingo disable BATs for Linux Kernel - */ -/* #undef SETUP_HIGH_BATS_FX750 */ /* don't initialize BATS 4-7 */ -#define SETUP_HIGH_BATS_FX750 /* initialize BATS 4-7 */ - -#ifdef SETUP_HIGH_BATS_FX750 -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* IBAT6 and DBAT6 */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* IBAT7 and DBAT7 */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#else /* set em out of range for Linux !!!!!!!!!!! */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U - -/* IBAT6 and DBAT6 */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U - -/* IBAT7 and DBAT7 */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U - -#endif -/* FIXME: ingo end: disable BATs for Linux Kernel */ - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ - -#if 0 -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ -#endif - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x050 -#define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -/*#define CONFIG_SYS_L2*/ -#undef CONFIG_SYS_L2 - -/* #ifdef CONFIG_750CX*/ -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - -#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) -#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) -#define CONFIG_SYS_PLD_VER 0xf0e00000 - -#define CONFIG_OF_LIBFDT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h deleted file mode 100644 index b77c8b2894..0000000000 --- a/include/configs/DB64360.h +++ /dev/null @@ -1,579 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2002 Datentechnik AG - Project: Dino - * - * - * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $ - * - ************************************************************************/ - -/************************************************************************* - * - * History: - * - * $Log: DB64360.h,v $ - * Revision 1.3 2003/04/26 04:58:13 brad - * Cosmetic changes and compiler warning cleanups - * - * Revision 1.2 2003/04/23 15:48:15 ingo - * mem. map output added - * - * Revision 1.1 2003/04/17 09:31:42 ias - * keymile changes 17_04_2003 - * - * Revision 1.10 2003/03/06 12:25:04 ias - * 750 FX CPU HID settings updated - * - * Revision 1.9 2003/03/03 16:14:36 ias - * cleanup compiler warnings of printf fuctions - * - * Revision 1.8 2003/03/03 15:11:44 ias - * Marvell MPSC-UART is working - * - * Revision 1.7 2003/02/26 12:15:45 ssu - * adapted default parameters to new board flash address - * - * Revision 1.6 2003/02/25 14:55:42 ssu - * changed default environment parameters - * - * Revision 1.5 2003/02/21 17:14:23 ias - * added extended SPD handling - * - * Revision 1.4 2003/01/14 09:16:08 ias - * PPCBoot for Marvel Beta 0.9 - * - * Revision 1.3 2002/12/03 13:56:26 ias - * Environment in flash support added - * - * Revision 1.2 2002/11/29 16:53:29 ias - * Flash support for STM added - * - * Revision 1.1 2002/11/29 13:36:31 ias - * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board - * - working DDRRAM (only 32MByte of 128MB Modul) - * - working I2C Driver for SPD EEPROM read - * - working DUART 16650 for Serial Console - * - working "console" - * - * - * - ************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64360/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -/* first ethernet */ -#define CONFIG_ETHADDR 64:36:00:00:00:01 - /* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:36:00:00:00:02 -/* in the atlantis 64360 we have only 2 ETH port on the board, -if we use PCI it has its own MAC addr */ - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64360_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_SYS_BOARD_NAME "DB64360" -#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)" - -/*#define CONFIG_SYS_HUSH_PARSER */ -#undef CONFIG_SYS_HUSH_PARSER - - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define MV_ETH_DEVS 2 - -/* #undef CONFIG_ETHER_PORT_MII */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64360:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini" - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=db64360-1" -#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" -*/ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CONFIG_SYS_DRAM_TEST - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ - -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ - -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64360 core) */ -#define CONFIG_SYS_TCLK 133000000 - - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_750FX_HID0 0x8000c084 -#define CONFIG_SYS_750FX_HID1 0x54800000 -#define CONFIG_SYS_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CONFIG_SYS_SDRAM2_BASE 0x20000000 -#define CONFIG_SYS_SDRAM3_BASE 0x30000000 -#define CONFIG_SYS_SDRAM4_BASE 0x40000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 - -#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64360 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CONFIG_SYS_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CONFIG_SYS_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ -#define CONFIG_SYS_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64360*/ -#define CONFIG_SYS_MPP_CONTROL_0 0x02222222 -#define CONFIG_SYS_MPP_CONTROL_1 0x11333011 -#define CONFIG_SYS_MPP_CONTROL_2 0x40431111 -#define CONFIG_SYS_MPP_CONTROL_3 0x00000044 - -/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64360 DDR-RAM !! */ -# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#define CONFIG_SYS_INIT_CHAN1 -#define CONFIG_SYS_INIT_CHAN2 - -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CONFIG_SYS_PCI_IDSEL 0x0 -#else -#define CONFIG_SYS_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h deleted file mode 100644 index abc443499c..0000000000 --- a/include/configs/DB64460.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64460/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -#define CONFIG_ETHADDR 64:46:00:00:00:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:46:00:00:00:02 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 64:46:00:00:00:03 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64460_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_SYS_BOARD_NAME "DB64460" -#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)" - -/*#define CONFIG_SYS_HUSH_PARSER */ -#undef CONFIG_SYS_HUSH_PARSER - - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define MV_ETH_DEVS 3 - -/* #undef CONFIG_ETHER_PORT_MII */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64460:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini" - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=db64460-1" -#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" -*/ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CONFIG_SYS_DRAM_TEST - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ - -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ - -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64460 core) */ -#define CONFIG_SYS_TCLK 133000000 - - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_750FX_HID0 0x8000c084 -#define CONFIG_SYS_750FX_HID1 0x54800000 -#define CONFIG_SYS_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CONFIG_SYS_SDRAM2_BASE 0x20000000 -#define CONFIG_SYS_SDRAM3_BASE 0x30000000 -#define CONFIG_SYS_SDRAM4_BASE 0x40000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 - -#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64460 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CONFIG_SYS_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CONFIG_SYS_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */ -#define CONFIG_SYS_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64460*/ -#define CONFIG_SYS_MPP_CONTROL_0 0x02222222 -#define CONFIG_SYS_MPP_CONTROL_1 0x11333011 -#define CONFIG_SYS_MPP_CONTROL_2 0x40431111 -#define CONFIG_SYS_MPP_CONTROL_3 0x00000044 - -/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64460 DDR-RAM !! */ -# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#define CONFIG_SYS_INIT_CHAN1 -#define CONFIG_SYS_INIT_CHAN2 - -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CONFIG_SYS_PCI_IDSEL 0x0 -#else -#define CONFIG_SYS_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h deleted file mode 100644 index 6a3a11cb7f..0000000000 --- a/include/configs/HWW1U1A.h +++ /dev/null @@ -1,460 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * HardwareWall HWW-1U-1A airborne unit configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High-level system configuration options */ -#define CONFIG_BOOKE /* Power/PowerPC Book-E */ -#define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */ -#define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */ -#define CONFIG_FSL_LAW /* FreeScale Local Access Window */ -#define CONFIG_P2020 /* FreeScale P2020 */ -#define CONFIG_HWW1U1A /* eXMeritus HardwareWall HWW-1U-1A */ -#define CONFIG_MP /* Multiprocessing support */ -#define CONFIG_HWCONFIG /* Use hwconfig from environment */ - -#define CONFIG_L2_CACHE /* L2 cache enabled */ -#define CONFIG_BTB /* Branch predition enabled */ - -#define CONFIG_PANIC_HANG /* No board reset on panic */ -#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r() */ -#define CONFIG_CMD_REGINFO /* Dump various CPU regs */ - -/* - * Allow the use of 36-bit physical addresses. Device-trees with 64-bit - * addresses have known compatibility issues with some existing kernels. - */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */ - -/* Reserve plenty of RAM for malloc (we have 2GB+) */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - -/* How much L2 cache do we map so we can use it as RAM */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -/* This is our temporary global data area just above the stack */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* The stack grows down from the global data area */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Enable IRQs and watchdog with a 1000Hz system decrementer */ -#define CONFIG_CMD_IRQ - -/* -------------------------------------------------------------------- */ - -/* - * Clock crystal configuration: - * (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR) - * (2) CCB: Multiplier from SYS_CLK - * (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock) - */ -#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/ -#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/ - - -/* -------------------------------------------------------------------- */ - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM - * 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1 - * 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused) - * 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3 - * 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH - * 0xe800_0000 0xefff_ffff 128M Spansion FLASH - * 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0) - * 0xffe0_0000 0xffef_ffff 1M CCSR - * 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller - */ - -/* Virtual Memory Map */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */ - -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* Physical Memory Map */ -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf /* for ASM code */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xffd00000 /* for ASM code */ -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf /* for ASM code */ -#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0xffe00000 /* for ASM code */ - - -/* -------------------------------------------------------------------- */ - -/* U-Boot image (MONITOR_BASE == TEXT_BASE) */ -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc /* Top address in flash */ -#define CONFIG_SYS_TEXT_BASE 0xeff80000 /* Start of U-Boot image */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN 0x80000 /* 512kB (4 flash sectors) */ - -/* - * U-Boot Environment Image: The two sectors immediately below U-Boot - * form the U-Boot environment (regular and redundant). - */ -#define CONFIG_ENV_IS_IN_FLASH /* The environment image is stored in FLASH */ -#define CONFIG_ENV_OVERWRITE /* Allow "protected" variables to be erased */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (1 flash sector) */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) - -/* Only use 8kB of each environment sector for data */ -#define CONFIG_ENV_SIZE 0x2000 /* 8kB */ -#define CONFIG_ENV_SIZE_REDUND 0x2000 /* 8kB */ - - -/* -------------------------------------------------------------------- */ - -/* Serial Console Configuration */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Echo back characters received during a serial download */ -#define CONFIG_LOADS_ECHO - -/* Allow a serial-download to temporarily change baud */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE - - -/* -------------------------------------------------------------------- */ - -/* PCI and PCI-Express Support */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCI_PNP /* Scan PCI busses */ -#define CONFIG_CMD_PCI /* Enable the "pci" command */ -#define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */ -#define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */ -#define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */ - -/* Enable 2 of the 3 PCI-E controllers */ -#define CONFIG_PCIE3 -#undef CONFIG_PCIE2 -#define CONFIG_PCIE1 - -/* Display human-readable names when initializing */ -#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB" -#define CONFIG_SYS_PCIE2_NAME "Unused" -#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531" - -/* - * PCI bus addresses - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 - - -/* -------------------------------------------------------------------- */ - -/* Generic FreeScale hardware I2C support */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } -#define CONFIG_CMD_I2C - -/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */ -#define CONFIG_CMD_DATE -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_BUS_NUM 0 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* Turn off RTC square-wave output to save battery */ -#define CONFIG_SYS_RTC_DS1337_NOOSC - -/* - * AT24C128N EEPROM at I2C0-0x53. - * - * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages - * of 64 bytes per page. The chip uses 2-byte addresses and has a max write - * cycle time of 20ms according to the datasheet. - * - * NOTE: Our environment is stored on regular direct-attached FLASH, this - * chip is only used as a write-protected backup for certain key settings - * such as the serial# and macaddr values. (EG: "env import") - */ -#define CONFIG_CMD_EEPROM -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21 - -/* - * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554). You - * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command - * will not be able to access the chip. - */ -#define CONFIG_PCA953X -#define CONFIG_CMD_PCA953X -#define CONFIG_CMD_PCA953X_INFO -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f - - -/* -------------------------------------------------------------------- */ - -/* FreeScale DDR2/3 SDRAM Controller */ -#define CONFIG_SYS_FSL_DDR2 /* Our SDRAM slot is DDR2 */ -#define CONFIG_DDR_ECC /* Enable ECC by default */ -#define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */ -#define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */ -#define CONFIG_VERY_BIG_RAM /* Allow 2GB+ of RAM */ -#define CONFIG_CMD_SDRAM - -/* Standard P2020 DDR controller parameters */ -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* Make sure to tell the DDR controller to preinitialze all of RAM */ -#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER - - -/* -------------------------------------------------------------------- */ - -/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -/* Flash banks (2x 128MB) */ -#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull) -#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS } - -/* - * Flash access modes and timings (values are the defaults after a RESET). - * - * NOTE: These could probably be optimized but are more than sufficient for - * this particular system for the moment. - */ -#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V) -#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - -/* Configure both flash banks */ -#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS)) -#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS)) -#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB) -#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB) - -/* Flash timeouts (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */ - -/* Quiet flash testing */ -#define CONFIG_SYS_FLASH_QUIET_TEST - -/* Make program/erase count down from 45/5 (9....8....7....) */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 - - -/* -------------------------------------------------------------------- */ - -/* Ethernet Device Support */ -#define CONFIG_MII /* Enable MII PHY code */ -#define CONFIG_MII_DEFAULT_TSEC /* ??? Copied from P2020DS */ -#define CONFIG_PHY_GIGE /* Support Gigabit PHYs */ -#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */ - -/* Turn on various helpful networking commands */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING - -/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */ -#define CONFIG_TSEC_ENET -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 -#define CONFIG_TSEC3 -#define CONFIG_TSEC1_NAME "owt0" -#define CONFIG_TSEC2_NAME "owt1" -#define CONFIG_TSEC3_NAME "peer" -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 -#define TSEC3_PHY_ADDR 4 -#define TSEC3_PHY_ADDR_CPUA 4 -#define TSEC3_PHY_ADDR_CPUB 5 - -/* PCI-E dual-port E1000 (external ethernet ports) */ -#define CONFIG_E1000 -#define CONFIG_E1000_SPI -#define CONFIG_E1000_SPI_GENERIC -#define CONFIG_CMD_E1000 - -/* We need the SPI infrastructure to poke the E1000's EEPROM */ -#define CONFIG_SPI -#define CONFIG_SPI_X -#define CONFIG_CMD_SPI -#define MAX_SPI_BYTES 32 - - -/* -------------------------------------------------------------------- */ - -/* USB Thumbdrive Device Support */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_CMD_USB - -/* Partition and Filesystem support */ -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - - -/* -------------------------------------------------------------------- */ - -/* Command line configuration. */ -#define CONFIG_CMDLINE_EDITING /* Enable command editing */ -#define CONFIG_COMMAND_HISTORY /* Enable command history */ -#define CONFIG_AUTO_COMPLETE /* Enable command completion */ -#define CONFIG_SYS_LONGHELP /* Enable detailed command help */ -#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */ -#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */ -#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */ -#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */ -#define CONFIG_SYS_HUSH_PARSER /* Enable a fancier shell */ - -/* A little extra magic here for the prompt */ -#define CONFIG_SYS_PROMPT hww1u1a_get_ps1() -#ifndef __ASSEMBLY__ -const char *hww1u1a_get_ps1(void); -#endif - -/* Include a bunch of default commands we probably want */ -#include <config_cmd_default.h> - -/* Other helpful shell-like commands */ -#define CONFIG_MD5 -#define CONFIG_SHA1 -#define CONFIG_CMD_MD5SUM -#define CONFIG_CMD_SHA1SUM -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_SETEXPR - - -/* -------------------------------------------------------------------- */ - -/* Image manipulation and booting */ - -/* We use the OpenFirmware-esque "Flattened Device Tree" */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMD_ELF -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB */ - -/* This is the default address for commands with an optional address arg */ -#define CONFIG_LOADADDR 100000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 - -/* Test memory starting from the default load address to just below 2GB */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_END 0x7f000000 - -#define CONFIG_BOOTDELAY 20 -#define CONFIG_BOOTCOMMAND "echo Not yet flashed" -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1" - -/* Extra environment parameters */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethprime=e1000#0\0" \ - "ethrotate=no\0" \ - "setbootargs=setenv bootargs " \ - "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \ - "perf_mode=performance\0" \ - "hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=ulpi\0" \ - "flkernel=0xe8000000\0" \ - "flinitramfs=0xe8800000\0" \ - "fldevicetree=0xeff20000\0" \ - "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \ - "flboot=run preboot; run flbootm\0" \ - "restore_eeprom=i2c dev 0 && " \ - "eeprom read $loadaddr 0x0000 0x2000 && " \ - "env import -c $loadaddr 0x2000\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h deleted file mode 100644 index 16af4bbcad..0000000000 --- a/include/configs/ICU862.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <mpc8xx_irq.h> - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_ICU862 1 -#define CONFIG_MPC862 1 - -#define CONFIG_SYS_TEXT_BASE 0x40F00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#ifdef CONFIG_100MHz -#define MPC8XX_FACT 24 /* Multiply by 24 */ -#define MPC8XX_XIN 4165000 /* 4.165 MHz in */ -#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) - /* define if cant' use get_gclk_freq */ -#else -#if 1 /* for 50MHz version of processor */ -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */ -#else /* for 80MHz version of processor */ -#define MPC8XX_FACT 20 /* Multiply by 20 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */ -#endif -#endif - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 -#if 1 -#define CONFIG_SYS_DISCOVER_PHY 1 -#else -#undef CONFIG_SYS_DISCOVER_PHY -#endif - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if 0 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00F40000 - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */ -#define SCCR_MASK 0 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01) -#else /* up to 50 MHz we use a 1:1 clock */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 ) -#endif /* CONFIG_100MHz */ - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ -#define CONFIG_SYS_RCCR 0x0020 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * PCMCIA Power Switch - * - * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to - * control the voltages on the PCMCIA slot which is connected to Port B - *----------------------------------------------------------------------- - */ - /* Output pins */ -#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */ -#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */ -#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */ -#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */ -#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */ -#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \ - TPS2205_VPP_PGM | TPS2205_VPP_VCC | \ - TPS2205_SHDN) - - /* Input pins */ -#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */ -#define TPS2205_INPUTS ( TPS2205_OC ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_SYS_OR0_PRELIM 0xFF000954 /* Real values for the board */ -#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */ - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */ - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13a01114 - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h deleted file mode 100644 index 8ccb0ff9d8..0000000000 --- a/include/configs/IDS8247.h +++ /dev/null @@ -1,462 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, <hs@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_IDS8247 1 -#define CPU_ID_STR "MPC8247" -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=ttyS0,115200\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/IDS8247/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ffa00000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_MISC_INIT_R 1 - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000080) -#define I2C_TRISTATE (iop->pdir &= ~0x00000080) -#define I2C_READ ((iop->pdat & 0x00000080) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ - else iop->pdat &= ~0x00000080 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ - else iop->pdat &= ~0x00000100 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#if 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X -#endif - -/* - * select serial console configuration - * use the extern UART for the console - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 14745600 - -#define CONFIG_SYS_UART_BASE 0xE0000000 -#define CONFIG_SYS_UART_SIZE 0x10000 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000) - - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" - - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#define CONFIG_ETHER_ON_FCC1 -#define FCC_ENET - -/* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK9 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH0_SIZE 8 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Environment in flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_SYS_NAND0_BASE 0xE1000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -#endif /* CONFIG_CMD_NAND */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ - -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) -#define CONFIG_SYS_HID0_FINAL 0 -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR 0 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 16 bit FLASH - * 1 60x GPCM 8 bit NAND - * 2 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit UART - * - */ - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ - -#define CONFIG_SYS_MPTPR 0x6600 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_SCY_6_CLK ) - -#if defined(CONFIG_CMD_NAND) -/* Bank 1 - NAND Flash -*/ -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE -#define CONFIG_SYS_NAND_SIZE 0x8000 - -#define CONFIG_SYS_OR_TIMING_NAND 0x000036 - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND ) -#endif - -/* Bank 2 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 - -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2 - - -/* SDRAM initialization values -*/ -#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_2C |\ - PSDMR_WRC_3C |\ - PSDMR_CL_3) - -/* Bank 3 - UART -*/ - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) - -#endif /* __CONFIG_H */ diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h deleted file mode 100644 index d45be0f609..0000000000 --- a/include/configs/MHPC.h +++ /dev/null @@ -1,369 +0,0 @@ -/* - * (C) Copyright 2001 - * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Configuation settings for the miniHiPerCam. - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_MHPC 1 /* on a miniHiPerCam */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */ -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#undef CONFIG_UCODE_PATCH - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE) -#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */ -#define LCD_VIDEO_COLS 640 -#define LCD_VIDEO_ROWS 480 -#define LCD_VIDEO_FG 255 -#define LCD_VIDEO_BG 0 - -#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */ -#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */ -#define CONFIG_VIDEO_LOGO - -#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */ -#define VIDEO_TSTC_FCT serial_stub_tstc -#define VIDEO_GETC_FCT serial_stub_getc - -#define CONFIG_BR0_WORKAROUND 1 - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_REGINFO - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical memory map - */ -#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfe000000 - -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=mhpc-0" -#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)" -*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */ -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_SEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 12-18 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define MPC8XX_SPEED 50000000L -#define MPC8XX_XIN 5000000L /* ref clk */ -#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ - -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */ -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001) - - -/*----------------------------------------------------------------------- - * MAMR settings for SDRAM - 16-14 - * => 0xC080200F - *----------------------------------------------------------------------- - * periodic timer for refresh - */ -#define CONFIG_SYS_MAMR_PTA 0xC0 -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK) - -/* - * BR0 and OR0 (FLASH) used to re-map FLASH - */ - -/* allow for max 8 MB of Flash */ -#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/ -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/ -#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/ - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V ) - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ -#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */ - -/* SDRAM timing: drive GPL5 high on first cycle */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS) - -#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2/OR2 - DIMM - */ -#define CONFIG_SYS_OR2 (OR_ACS_DIV4) -#define CONFIG_SYS_BR2 (BR_MS_UPMA) - -/* - * BR3/OR3 - DIMM - */ -#define CONFIG_SYS_OR3 (OR_ACS_DIV4) -#define CONFIG_SYS_BR3 (BR_MS_UPMA) - -/* - * BR4/OR4 - */ -#define CONFIG_SYS_OR4 0 -#define CONFIG_SYS_BR4 0 - -/* - * BR5/OR5 - */ -#define CONFIG_SYS_OR5 0 -#define CONFIG_SYS_BR5 0 - -/* - * BR6/OR6 - */ -#define CONFIG_SYS_OR6 0 -#define CONFIG_SYS_BR6 0 - -/* - * BR7/OR7 - */ -#define CONFIG_SYS_OR7 0 -#define CONFIG_SYS_BR7 0 - - -/*----------------------------------------------------------------------- - * Debug Entry Mode - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index c5e2f164ce..c29429d368 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -29,6 +29,9 @@ #define CONFIG_SYS_TEXT_BASE 0xFFF90000 #endif +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_SYS_CLK_FREQ 33333400 #if 0 /* temporary disabled because OS/9 does not like dcache on startup */ @@ -133,6 +136,7 @@ #endif #ifdef CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_I2C_ENV_EEPROM_BUS 0 #define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */ #define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */ #endif diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h deleted file mode 100644 index 92128b9588..0000000000 --- a/include/configs/TOP5200.h +++ /dev/null @@ -1,402 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de - * - * TOP5200 differences from IceCube: - * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks - * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins - * 1 SDRAM/DDRAM Bank up to 256 MB - * local VPD I2C Bus is software driven and uses - * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL - * FLASH is re-located at 0xff000000 - * Internal regs are at 0xf0000000 - * Reset jumps to 0x00000100 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */ - -/* - * allowed and functional CONFIG_SYS_TEXT_BASE values: - * 0xff000000 low boot at 0x00000100 (default board setting) - * 0xfff00000 high boot at 0xfff00100 (board needs modification) - * 0x00100000 RAM load and test - */ -#define CONFIG_SYS_TEXT_BASE 0xff000000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -# define CONFIG_PCI 1 -# define CONFIG_PCI_PNP 1 -# define CONFIG_PCI_SCAN_SHOW 1 -# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -# define CONFIG_PCI_MEM_BUS 0x40000000 -# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -# define CONFIG_PCI_MEM_SIZE 0x10000000 - -# define CONFIG_PCI_IO_BUS 0x50000000 -# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -# define CONFIG_PCI_IO_SIZE 0x01000000 - -#endif - -/* USB */ -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) - -# define CONFIG_USB_OHCI -# define CONFIG_USB_CLOCK 0x0001bbbb -# if defined (CONFIG_EVAL5200) -# define CONFIG_USB_CONFIG 0x00005100 -# else -# define CONFIG_USB_CONFIG 0x00001000 -# endif -# define CONFIG_DOS_PARTITION -# define CONFIG_USB_STORAGE - -#endif - -/* IDE */ -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) -# define CONFIG_DOS_PARTITION -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_REGINFO - -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_USB -#define CONFIG_CMD_PCI -#endif - - -/* - * MUST be low boot - HIGHBOOT is not supported anymore - */ -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#else -# error "CONFIG_SYS_TEXT_BASE must be 0xff000000" -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -/* - * EEPROM configuration - */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_SIZE 0x2000 - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ - -#if defined(CONFIG_SYS_I2C_SOFT) -# define CONFIG_SYS_I2C -# define CONFIG_SYS_I2C_SOFT_SPEED 100000 -# define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/**/ -# define SDA0 0x40 -# define SCL0 0x80 -# define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00)) -# define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08)) -# define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c)) -# define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20)) -# define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04)) -# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);} -# define I2C_READ ((DVI0&SDA0)?1:0) -# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;} -# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;} -# define I2C_DELAY {udelay(5);} -# define I2C_ACTIVE {DDR0|=SDA0;} -# define I2C_TRISTATE {DDR0&=~SDA0;} - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_FACT_ADDR 0x57 -#endif - -#if defined (CONFIG_HARD_I2C) -# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -# define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_FACT_ADDR 0x54 -#endif - -/* - * Flash configuration, expect one 16 Megabyte Bank at most - */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0) - -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ - -/* - * DRAM configuration - will be read from VPD later... TODO! - */ -#if 0 -/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */ -#define CONFIG_SYS_DRAM_DDR 0 -#define CONFIG_SYS_DRAM_EMODE 0 -#define CONFIG_SYS_DRAM_MODE 0x008D -#define CONFIG_SYS_DRAM_CONTROL 0x514F0000 -#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00 -#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004 -#define CONFIG_SYS_DRAM_TAP_DEL 0x08 -#define CONFIG_SYS_DRAM_RAM_SIZE 0x19 -#endif -#if 1 -/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */ -#define CONFIG_SYS_DRAM_DDR 0 -#define CONFIG_SYS_DRAM_EMODE 0 -#define CONFIG_SYS_DRAM_MODE 0x00CD -#define CONFIG_SYS_DRAM_CONTROL 0x514F0000 -#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00 -#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004 -#define CONFIG_SYS_DRAM_TAP_DEL 0x08 -#define CONFIG_SYS_DRAM_RAM_SIZE 0x19 -#endif - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ -#define CONFIG_ENV_OFFSET 0x1000 -#define CONFIG_ENV_SIZE 0x0700 - -/* - * VPD settings - */ -#define CONFIG_SYS_FACT_OFFSET 0x1800 -#define CONFIG_SYS_FACT_SIZE 0x0800 - -/* - * Memory map - * - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 - */ -#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x1f -#define CONFIG_PHY_TYPE 0x79c874 -/* - * GPIO configuration: - * PSC1,2,3 predefined as UART - * PCI disabled - * Ethernet 100 with MD - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */ - #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */ - #define RTC(reg) (0xf0010000+reg) - /* setup CS2 for M48T08. Must MAP 64kB */ - #define CONFIG_SYS_CS2_START RTC(0) - #define CONFIG_SYS_CS2_SIZE 0x10000 - /* setup CS2 configuration register: */ - /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */ - /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */ - #define CONFIG_SYS_CS2_CFG 0x00047800 -#else - #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0x7f000000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET 1 -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h deleted file mode 100644 index da68503a69..0000000000 --- a/include/configs/TOP860.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * (C) Copyright 2003 - * EMK Elektronik GmbH <www.emk-elektronik.de> - * Reinhard Meyer <r.meyer@emk-elektronik.de> - * - * Configuation settings for the TOP860 board. - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * TOP860 is a simple module: - * 16-bit wide FLASH on CS0 (2MB or more) - * 32-bit wide DRAM on CS2 (either 4MB or 16MB) - * FEC with Am79C874 100-Base-T and Fiber Optic - * Ports available, but we choose SMC1 for Console - * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set - * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock - * - * This config has been copied from MBX.h / MBX860T.h - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/*----------------------------------------------------------------------- - * CPU and BOARD type - */ -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_MPC860T 1 /* even better... an FEC! */ -#define CONFIG_TOP860 1 /* ...on a TOP860 module */ - -#define CONFIG_SYS_TEXT_BASE 0x80000000 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_IDENT_STRING " EMK TOP860" - -/*----------------------------------------------------------------------- - * CLOCK settings - */ -#define CONFIG_SYSCLK 49152000 -#define CONFIG_SYS_XTAL 32768 -#define CONFIG_EBDF 1 -#define CONFIG_COM 3 -#define CONFIG_RTC_MPC8xx - -/*----------------------------------------------------------------------- - * Physical memory map as defined by EMK - */ -#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register */ -#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH in final mapping */ -#define CONFIG_SYS_DRAM_BASE 0x00000000 /* DRAM in final mapping */ -#define CONFIG_SYS_FLASH_MAX 0x00400000 /* max FLASH to expect */ -#define CONFIG_SYS_DRAM_MAX 0x01000000 /* max DRAM to expect */ - -/*----------------------------------------------------------------------- - * derived values - */ -#define CONFIG_SYS_MF (CONFIG_SYSCLK/CONFIG_SYS_XTAL) -#define CONFIG_SYS_CPUCLOCK CONFIG_SYSCLK -#define CONFIG_SYS_BRGCLOCK CONFIG_SYSCLK -#define CONFIG_SYS_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF) -#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_CFI - -/*----------------------------------------------------------------------- - * Command interpreter - */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_BAUDRATE 9600 - -/* - * Allow partial commands to be matched to uniqueness. - */ -#define CONFIG_SYS_MATCH_PARTIAL_CMD - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_BEDBUG - - -#define CONFIG_SOURCE 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 -#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */ - - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */ - - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test Command - */ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Environment handler - * only the first 6k in EEPROM are available for user. Of that we use 256b - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ -#define CONFIG_ENV_OFFSET 0x1000 -#define CONFIG_ENV_SIZE 0x0700 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_FACT_OFFSET 0x1800 -#define CONFIG_SYS_FACT_SIZE 0x0800 -#define CONFIG_SYS_I2C_FACT_ADDR 0x57 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_SIZE 0x2000 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 -#define CONFIG_ENV_OVERWRITE -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/**/ -#define SDA 0x00010 -#define SCL 0x00020 -#define __I2C_DIR immr->im_cpm.cp_pbdir -#define __I2C_DAT immr->im_cpm.cp_pbdat -#define __I2C_PAR immr->im_cpm.cp_pbpar -#define __I2C_ODR immr->im_cpm.cp_pbodr -#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ - __I2C_ODR &= ~(SDA|SCL); \ - __I2C_DAT |= (SDA|SCL); \ - __I2C_DIR|=(SDA|SCL); } -#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) -#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } -#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } -#define I2C_DELAY { udelay(5); } -#define I2C_ACTIVE { __I2C_DIR |= SDA; } -#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/*----------------------------------------------------------------------- - * defines we need to get FEC running - */ -#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ -#define FEC_ENET 1 /* eth.c needs it that way... */ -#define CONFIG_SYS_DISCOVER_PHY 1 -#define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 -#define CONFIG_PHY_ADDR 31 - -/*----------------------------------------------------------------------- - * adresses - */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x80000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -/*----------------------------------------------------------------------- - * Debug Enable Register - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 /* used in start.S */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set up PLPRCR (PLL, Low-Power, and Reset Control Register) - * 12 MF calculated Multiplication factor - * 4 0 0000 - * 1 SPLSS 0 System PLL lock status sticky - * 1 TEXPS 1 Timer expired status - * 1 0 0 - * 1 TMIST 0 Timers interrupt status - * 1 0 0 - * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL) - * 2 LPM 00 Low-power modes - * 1 CSR 0 Checkstop reset enable - * 1 LOLRE 0 Loss-of-lock reset enable - * 1 FIOPD 0 Force I/O pull down - * 5 0 00000 - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20)) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * set up SYPCR: - * 16 SWTC 0xffff Software watchdog timer count - * 8 BMT 0xff Bus monitor timing - * 1 BME 1 Bus monitor enable - * 3 0 000 - * 1 SWF 1 Software watchdog freeze - * 1 SWE 0/1 Software watchdog enable - * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET) - * 1 SWP 0/1 Software watchdog prescale (1=/2048) - */ -#if defined (CONFIG_WATCHDOG) - #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else - #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * set up SIUMCR - * 1 EARB 0 External arbitration - * 3 EARP 000 External arbitration request priority - * 4 0 0000 - * 1 DSHW 0 Data show cycles - * 2 DBGC 00 Debug pin configuration - * 2 DBPC 00 Debug port pins configuration - * 1 0 0 - * 1 FRC 0 FRZ pin configuration - * 1 DLK 0 Debug register lock - * 1 OPAR 0 Odd parity - * 1 PNCS 0 Parity enable for non memory controller regions - * 1 DPC 0 Data parity pins configuration - * 1 MPRE 0 Multiprocessor reservation enable - * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT) - * 1 AEME 0 Async external master enable - * 1 SEME 0 Sync external master enable - * 1 BSC 0 Byte strobe configuration - * 1 GB5E 0 GPL_B5 enable - * 1 B2DD 0 Bank 2 double drive - * 1 B3DD 0 Bank 3 double drive - * 4 0 0000 - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC11) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * set up SCCR (System Clock and Reset Control Register) - * 1 0 0 - * 2 COM 11 Clock output module (00=full, 01=half, 11=off) - * 3 0 000 - * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2) - * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512) - * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK) - * 1 CRQEN 0 CPM request enable - * 1 PRQEN 0 Power management request enable - * 2 0 00 - * 2 EBDF xx External bus division factor - * 2 0 00 - * 2 DFSYNC 00 Division factor for SYNCLK - * 2 DFBRG 00 Division factor for BRGCLK - * 3 DFNL 000 Division factor low frequency - * 3 DFNH 000 Division factor high frequency - * 5 0 00000 - */ -#define SCCR_MASK 0 -#ifdef CONFIG_EBDF - #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01) -#else - #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS) -#endif - -/*----------------------------------------------------------------------- - * Chip Select 0 - FLASH - *----------------------------------------------------------------------- - * Preliminary Values - */ -/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR) -#define CONFIG_SYS_OR0_PRELIM (-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V ) - -/*----------------------------------------------------------------------- - * misc - *----------------------------------------------------------------------- - * - */ -/* - * Set the autoboot delay in seconds. A delay of -1 disables autoboot - */ -#define CONFIG_BOOTDELAY 5 - -/* - * Pass the clock frequency to the Linux kernel in units of MHz - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_PREBOOT \ - "echo;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Set default IP stuff just to get bootstrap entries into the - * environment so that we can source the full default environment. - */ -#define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.200 -#define CONFIG_IPADDR 10.0.4.111 - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 69c0336cae..cdccbef1f6 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2005 + * (C) Copyright 2003-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004-2006 @@ -19,6 +19,8 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index cc2204586e..0d5a2b96f1 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 4fd070f27d..e765a03cfb 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h deleted file mode 100644 index 7fd12d3fbc..0000000000 --- a/include/configs/TQM8260.h +++ /dev/null @@ -1,620 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Imported from global configuration: - * CONFIG_MPC8255 - * CONFIG_MPC8265 - * CONFIG_200MHz - * CONFIG_266MHz - * CONFIG_300MHz - * CONFIG_L2_CACHE - * CONFIG_BUSMODE_60x - */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - - -#if 0 -#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ -#else -#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ -#endif - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=tqm8260/uImage\0" \ - "kernel_addr=400C0000\0" \ - "ramdisk_addr=40240000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ -#if (CONFIG_TQM8260 <= 100) - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00020000) -#define I2C_TRISTATE (iop->pdir &= ~0x00020000) -#define I2C_READ ((iop->pdat & 0x00020000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#else - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ -# ifndef CONFIG_300MHz -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -# else -# define CONFIG_8260_CLKIN 83333000 /* in Hz */ -# endif -#endif /* CONFIG_MPC8255 */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH1_BASE 0x60000000 -#define CONFIG_SYS_FLASH0_SIZE 32 -#define CONFIG_SYS_FLASH1_SIZE 32 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x08000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else /* ! MPC8255 && !MPC8265 */ -# if defined(CONFIG_266MHz) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -# elif defined(CONFIG_300MHz) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) -# else -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__) -# endif -#endif /* CONFIG_MPC8255 */ - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_BUSMODE_60x -#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ - BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ -#else -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ -#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - - /* SDRAM on TQM8260 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - -/* Bank 2 - Local bus SDRAM - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL - -#define SDRAM_BASE2_PRELIM 0x80000000 - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h deleted file mode 100644 index 9c7e16305d..0000000000 --- a/include/configs/TQM8272.h +++ /dev/null @@ -1,735 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_TQM8272 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ -#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ - -#define STK82xx_150 1 /* on a STK82xx.150 */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_EARLY_INIT_R 1 - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyCPM0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "hostname=tqm8272\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=$(consdev),$(baudrate)\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 300000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/tqm8272/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40100000\0" \ - "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ - "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ - "cp.b 300000 40000000 40000;" \ - "setenv filesize;saveenv\0" \ - "cphwib=cp.b 4003fc00 33fc00 400\0" \ - "upd=run load cphwib update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_I2C 1 - -#if CONFIG_I2C -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_I2C_X - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -#else -#undef CONFIG_SYS_I2C -#undef CONFIG_HARD_I2C -#undef CONFIG_SYS_I2C_SOFT -#endif - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#define CONFIG_SYS_FCC_ETHERNET - -#if defined(CONFIG_SYS_FCC_ETHERNET) -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#else -#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#if STK82xx_150 -#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */ -#define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */ -#endif - -#if STK82xx_100 -#define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */ -#define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */ -#endif - -#if 1 -#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDC_PIN -#else -#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;} - -#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;} -#endif - -#define MIIDELAY udelay(1) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - -#if CONFIG_I2C - #define CONFIG_CMD_I2C - #define CONFIG_CMD_DATE - #define CONFIG_CMD_DTT - #define CONFIG_CMD_EEPROM -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if 0 -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * CAN stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CAN_BASE 0x51000000 -#define CONFIG_SYS_CAN_SIZE 1 -#define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMC |\ - BRx_V) - -#define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\ - ORxU_BI) - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */ - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_SYS_UPDATE_FLASH_SIZE - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND 0x20000 - -/* Where is the Hardwareinformation Block (from Monitor Sources) */ -#define MON_RES_LENGTH (0x0003FC00) -#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH) -#define HWIB_INFO_LEN 512 -#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) -#define CIB_INFO_LEN 512 - -#define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_SYS_NAND_CS_DIST 0x80 -#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20 -#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40 - -#define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMB |\ - BRx_V) - -#define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_8IDLE) - -#define CONFIG_SYS_NAND_SIZE 1 -#define CONFIG_SYS_NAND0_BASE 0x50000000 -#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) - -#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ - CONFIG_SYS_NAND1_BASE, \ - CONFIG_SYS_NAND2_BASE, \ - CONFIG_SYS_NAND3_BASE, \ - } - -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) -#define WRITE_NAND_UPM(d, adr, off) do \ -{ \ - volatile unsigned char *addr = (unsigned char *) (adr + off); \ - WRITE_NAND(d, addr); \ -} while(0) - -#endif /* CONFIG_CMD_NAND */ - -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_PCI_SCAN_SHOW -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if 0 -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -#define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00) -#define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00) -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 60x UPMB 8 bit NAND - * 3 60x UPMC 8 bit CAN - * - */ - -/* Initialize SDRAM - */ -#undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ - -#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_8_CLK |\ - ORxG_TRLX) - -/* SDRAM on TQM8272 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 /* Low Value */ -/* #define CONFIG_SYS_PSRT 0x10 Fast Value */ -#define CONFIG_SYS_LSRT 0x20 /* Local Bus */ -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - -/* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - - -/* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A4 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\ - PSDMR_SDAM_A17_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A4 |\ - PSDMR_RFRC_6_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ -#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ -#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ -#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ -#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ -#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ - -#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ -#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ -#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ -#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ -#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ -#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ - -#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ -#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ -#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ -#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ -#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ -#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ - -#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ -#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ -#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ -#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ -#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ -#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index ca3750d407..bbdc3f81fc 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 659c9ad1c3..5fc87f2138 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 906d79b0c8..589d168eba 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ #define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 44d456e165..60acb564e8 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 855b0cddc4..ebc5571632 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 8109379ae9..f4ce07f20e 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index da4af93d25..97db519d53 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -20,6 +20,8 @@ #define CONFIG_MPC860 1 #define CONFIG_MPC860T 1 #define CONFIG_MPC862 1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index ec3a57b961..25d60a74ef 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -20,6 +20,8 @@ #define CONFIG_MPC860 1 #define CONFIG_MPC860T 1 #define CONFIG_MPC862 1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index cb8b84d3a1..928b879609 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index d1e6c5b2bb..598020c867 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2006 @@ -22,6 +22,8 @@ #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index f57820d8f5..54b7028c56 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_AC14XX 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the ifm AC14xx board: * diff --git a/include/configs/alt.h b/include/configs/alt.h index 7238f68820..7bd649fb42 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -31,10 +31,17 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE #define CONFIG_CMD_SF #define CONFIG_CMD_SPI +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else #define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_GENERIC_BOARD @@ -59,7 +66,11 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_TMU_TIMER +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#endif #define STACK_AREA_SIZE 0xC000 #define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) @@ -162,4 +173,14 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ +/* Filesystems */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + +/* USB */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + #endif /* __ALT_H */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 476430ddd0..560e3bf775 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -314,6 +314,18 @@ #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST +#ifndef CONFIG_SPL_USBETH_SUPPORT +/* Fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 + +/* To support eMMC booting */ +#define CONFIG_STORAGE_EMMC +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#endif + #ifdef CONFIG_MUSB_HOST #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE @@ -325,8 +337,8 @@ #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" /* USB TI's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x0403 -#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_VENDOR_NUM 0x0451 +#define CONFIG_G_DNL_PRODUCT_NUM 0xD022 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" #endif /* CONFIG_MUSB_GADGET */ @@ -352,10 +364,10 @@ "boot part 0 1;" \ "rootfs part 0 2;" \ "MLO fat 0 1;" \ - "MLO.raw mmc 0x100 0x100;" \ - "u-boot.img.raw mmc 0x300 0x400;" \ - "spl-os-args.raw mmc 0x80 0x80;" \ - "spl-os-image.raw mmc 0x900 0x2000;" \ + "MLO.raw raw 0x100 0x100;" \ + "u-boot.img.raw raw 0x300 0x400;" \ + "spl-os-args.raw raw 0x80 0x80;" \ + "spl-os-image.raw raw 0x900 0x2000;" \ "spl-os-args fat 0 1;" \ "spl-os-image fat 0 1;" \ "u-boot.img fat 0 1;" \ @@ -382,7 +394,7 @@ "fdt ram 0x80F80000 0x80000;" \ "ramdisk ram 0x81000000 0x4000000\0" #define DFUARGS \ - "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ + "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_NAND diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index fcb4033c01..0fbfa3fb4c 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -304,8 +304,8 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index c5d64ca59e..8719f763dd 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -313,8 +313,8 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 070782774d..4472c3e555 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -11,6 +11,9 @@ #define CONFIG_AM43XX +#define CONFIG_CMD_FAT +#define CONFIG_CMD_SAVEENV + #define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_CACHELINE_SIZE 32 @@ -82,7 +85,11 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" @@ -103,7 +110,7 @@ #ifdef CONFIG_QSPI_BOOT #define CONFIG_SYS_TEXT_BASE 0x30000000 -#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_IS_IN_FAT #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED diff --git a/include/configs/aria.h b/include/configs/aria.h index c36cf33f07..2f9677c332 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_ARIA 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the ARIA board: * diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h index 20aea8572d..e6a08df4ba 100644 --- a/include/configs/aristainetos.h +++ b/include/configs/aristainetos.h @@ -77,7 +77,7 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 3 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 20)<<8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 1bf8390722..6e8c56c1dd 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -83,12 +83,15 @@ /* * I2C configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DW_I2C -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW #define CONFIG_I2C_ENV_EEPROM_BUS 2 #define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SPEED1 100000 +#define CONFIG_SYS_I2C_SPEED2 100000 #define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_SLAVE1 0 +#define CONFIG_SYS_I2C_SLAVE2 0 #define CONFIG_SYS_I2C_BASE 0xE001D000 #define CONFIG_SYS_I2C_BASE1 0xE001E000 #define CONFIG_SYS_I2C_BASE2 0xE001F000 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 6f4d97f2fd..1919cde79f 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -321,8 +321,8 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h new file mode 100644 index 0000000000..918032bd75 --- /dev/null +++ b/include/configs/cm_t3517.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2013 CompuLab, Ltd. + * Author: Igor Grinberg <grinberg@compulab.co.il> + * + * Configuration settings for the CompuLab CM-T3517 board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_CM_T3517 /* working with CM-T3517 */ +#define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * This is needed for the DMA stuff. + * Although the default iss 64, we still define it + * to be on the safe side once the default is changed. + */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_OF_LIBFDT +/* + * The early kernel mapping on ARM currently only maps from the base of DRAM + * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. + * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, + * so that leaves DRAM base to DRAM base + 0x4000 available. + */ +#define CONFIG_SYS_BOOTMAPSZ 0x4000 + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +#define CONFIG_OMAP_GPIO + +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* USB */ +#define CONFIG_USB_MUSB_AM35X + +#ifndef CONFIG_USB_MUSB_AM35X +#define CONFIG_USB_OMAP3 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 +#else /* !CONFIG_USB_MUSB_AM35X */ +#define CONFIG_MUSB_HOST +#define CONFIG_MUSB_PIO_ONLY +#endif /* CONFIG_USB_MUSB_AM35X */ + +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ + "1920k(u-boot),256k(u-boot-env),"\ + "4m(kernel),-(fs)" + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_GPIO + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 400000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0 +#define CONFIG_I2C_MULTI_BUS + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "baudrate=115200\0" \ + "console=ttyO2,115200n8\0" \ + "mpurate=auto\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ + "mmcrootfstype=ext4\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 2a0000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_CMD_BOOTZ +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_TIMESTAMP +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "CM-T3517 # " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define CONFIG_SYS_CS0_SIZE (256 << 20) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) +#endif /* CONFIG_CMD_NET */ + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Status LED */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED +#define CONFIG_GPIO_LED +#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ +#define GREEN_LED_DEV 0 +#define STATUS_LED_BIT GREEN_LED_GPIO +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BOOT GREEN_LED_DEV + +/* GPIO banks */ +#ifdef CONFIG_STATUS_LED +#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ +#endif + +/* Display Configuration */ +#define CONFIG_OMAP3_GPIO_2 +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_VIDEO_OMAP3 +#define LCD_BPP LCD_COLOR16 + +#define CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASHIMAGE_GUARD +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_SCF0403_LCD + +#define CONFIG_OMAP3_SPI + +#endif /* __CONFIG_H */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 200b744e4f..fef267f70b 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -26,6 +26,12 @@ #define CONFIG_PHYSMEM #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL #define CONFIG_LMB #define CONFIG_OF_LIBFDT @@ -43,6 +49,7 @@ #define CONFIG_FIT #undef CONFIG_ZLIB #undef CONFIG_GZIP +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /*----------------------------------------------------------------------- * Watchdog Configuration @@ -88,21 +95,16 @@ /*----------------------------------------------------------------------- * Serial Configuration */ -#define CONFIG_CONS_INDEX 1 +#define CONFIG_COREBOOT_SERIAL #define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 1843200 -#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE #define CONFIG_SYS_NS16550_PORT_MAPPED -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,eserial0\0" \ - "stdout=vga,eserial0,cbmem\0" \ - "stderr=vga,eserial0,cbmem\0" +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial,cbmem\0" \ + "stderr=vga,serial,cbmem\0" #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV @@ -221,7 +223,7 @@ #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x02000000 +#define CONFIG_SYS_LOAD_ADDR 0x20000000 /*----------------------------------------------------------------------- * SDRAM Configuration @@ -256,7 +258,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024) - +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 7ab6d51642..ca624619a0 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -298,8 +298,8 @@ #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ @@ -341,8 +341,8 @@ 0x400000) #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index 2a8cb3940b..76ec168c20 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -22,6 +22,8 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 6ba9bb7a1b..b258cb93c4 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -75,6 +75,7 @@ #define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION diff --git a/include/configs/hymod.h b/include/configs/hymod.h deleted file mode 100644 index c973365e12..0000000000 --- a/include/configs/hymod.h +++ /dev/null @@ -1,728 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen <Murray.Jensen@cmst.csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for Hymod board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_HYMOD 1 /* ...on a Hymod board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ -#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ - -#ifdef CONFIG_ETHER_ON_FCC - -#if (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK11 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ -# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ -# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ - -#elif (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ -# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) -#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) -#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ - else iop->pdat &= ~MDIO_DATA_PINMASK - -#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ - else iop->pdat &= ~MDIO_CLCK_PINMASK - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - - -/* other options */ -#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ -#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifdef DEBUG -#define CONFIG_8260_CLKIN 33333333 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#endif - -#if defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 115200 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -/* default ip addresses - these will be overridden */ -#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ -#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ - -#define CONFIG_LAST_STAGE_INIT - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_XIMG - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ -#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press <SPACE> to stop\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 -#endif - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ -#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ -# if defined(CONFIG_KGDB_USE_EXTC) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -# else -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -# endif -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -/* - * Hymod specific configurable options - */ -#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0x7e - -/* these are for the ST M24C02 2kbit serial i2c eeprom */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ - -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ - -/* - * standard dtt sensor configuration - bottom bit will determine local or - * remote sensor of the ADM1021, the rest determines index into - * CONFIG_SYS_DTT_ADM1021 array below. - * - * On HYMOD board, the remote sensor should be connected to the MPC8260 - * temperature diode thingy, but an errata said this didn't work and - * should be disabled - so it isn't connected. - */ -#if 0 -#define CONFIG_DTT_SENSORS { 0, 1 } -#else -#define CONFIG_DTT_SENSORS { 0 } -#endif - -/* - * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). - * there will be one entry in this array for each two (dummy) sensors in - * CONFIG_DTT_SENSORS. - * - * For HYMOD board: - * - only one ADM1021 - * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) - * - conversion rate 0x02 = 0.25 conversions/second - * - ALERT ouput disabled - * - local temp sensor enabled, min set to 0 deg, max set to 85 deg - * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) - */ -#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#ifdef DEBUG -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0010) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0101) -#endif -/* no slaves so just duplicate the master hrcw */ -#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FPGA_BASE 0x80000000 -/* - * unfortunately, CONFIG_SYS_MONITOR_LEN must include the - * (very large i.e. 256kB) environment flash sector - */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#ifdef DEBUG -#define CONFIG_SYS_HID0_FINAL 0 -#else -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#endif -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#ifdef DEBUG -#define CONFIG_SYS_RMR 0 -#else -#define CONFIG_SYS_RMR RMR_CSRE -#endif - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ - SIUMCR_APPC10|SIUMCR_MMR11) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) - * 2 60x SDRAM 64 bit SDRAM - * 3 Local UPMC 8 bit Main Xilinx configuration - * 4 Local GPCM 32 bit Main Xilinx register mode - * 5 Local UPMB 32 bit Main Xilinx port mode - * 6 Local UPMC 8 bit Mezz Xilinx configuration - */ - -/* - * Bank 0 - FLASH - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The flash memory is two Intel StrataFlash chips, each configured for - * 16 bit operation and connected to give a 32 bit wide port." - * - * "The chip select logic is configured to respond to both *CS0 and *CS1. - * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. - * It is suggested that bank 0 be read-only and bank 1 be read/write. The - * FLASH will then appear as ROM during boot." - * - * Initially, we are only going to use bank 0 in read/write mode. - */ - -/* 32 bit, read-write, GPCM on 60x bus */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\ - BRx_PS_32|BRx_MS_GPCM_P|BRx_V) -/* up to 32 Mb */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) - -/* - * Bank 2 - SDRAM - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a - * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous - * dynamic random access memory organised as 4 banks by 4096 rows by 512 - * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." - * - * "The locations in SDRAM are accessed using multiplexed address pins to - * specify row and column. The pins also act to specify commands. The state - * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP - * pin may function as a row address or as the AUTO PRECHARGE control line, - * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 - * address lines to be configured to the required multiplexing scheme." - */ - -#define CONFIG_SYS_SDRAM_SIZE 64 - -/* 64 bit, read-write, SDRAM on 60x bus */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\ - BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) -/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\ - ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) - -/* - * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: - * - * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 - * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 - * as bank select, A7 is output on SDA10 during an ACTIVATE command, - * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, - * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE - * command is 2 clocks, earliest timing for PRECHARGE after last data - * was read is 1 clock, earliest timing for PRECHARGE after last data - * was written is 1 clock, CAS Latency is 2. - */ - -#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ - PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ - PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ - PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ - PSDMR_WRC_1C|PSDMR_CL_2) - -/* - * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh - * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register - * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer - * Prescaler, hence the P instead of the R). The refresh timer period is given - * by (note that there was a change in the 8260 UM Errata): - * - * TimerPeriod = (PSRT + 1) / Fmptc - * - * where Fmptc is the BusClock divided by PTP. i.e. - * - * TimerPeriod = (PSRT + 1) / (BusClock / PTP) - * - * or - * - * TImerPeriod = (PTP * (PSRT + 1)) / BusClock - * - * The requirement for the Toshiba TC59SM716FTL-10 is that there must be - * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 - * = 15.625 usecs. - * - * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 - * appear to be reasonable. - */ - -#ifdef DEBUG -#define CONFIG_SYS_PSRT 39 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 -#else -#define CONFIG_SYS_PSRT 31 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#endif - -/* - * Banks 3,4,5 and 6 - FPGA access - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made - * for configuring an optional FPGA on the mezzanine interface. - * - * Access to the FPGAs may be divided into several catagories: - * - * 1. Configuration - * 2. Register mode access - * 3. Port mode access - * - * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be - * configured only (mode 1). Consequently there are four access types. - * - * To improve interface performance and simplify software design, the four - * possible access types are separately mapped to different memory banks. - * - * All are accessed using the local bus." - * - * Device Mode Memory Bank Machine Port Size Access - * - * Main Configuration 3 UPMC 8bit R/W - * Main Register 4 GPCM 32bit R/W - * Main Port 5 UPMB 32bit R/W - * Mezzanine Configuration 6 UPMC 8bit W/O - * - * "Note that mezzanine mode 1 access is write-only." - */ - -/* all the bank sizes must be a power of two, greater or equal to 32768 */ -#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) -#define FPGA_MAIN_CFG_SIZE 32768 -#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) -#define FPGA_MAIN_REG_SIZE 32768 -#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) -#define FPGA_MAIN_PORT_SIZE 32768 -#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) -#define FPGA_MEZZ_CFG_SIZE 32768 - -/* 8 bit, read-write, UPMC */ -#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) - -/* 32 bit, read-write, GPCM */ -#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) -/* up to 32Kbyte */ -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) - -/* 32 bit, read-write, UPMB */ -#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) -/* up to 32Kbyte */ -#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) - -/* 8 bit, write-only, UPMC */ -#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) - -/*----------------------------------------------------------------------- - * MBMR - Machine B Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ - -/*----------------------------------------------------------------------- - * MCMR - Machine C Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ - -/* - * FPGA I/O Port/Bit information - */ - -#define FPGA_MAIN_PROG_PORT IOPIN_PORTA -#define FPGA_MAIN_PROG_PIN 4 /* PA4 */ -#define FPGA_MAIN_INIT_PORT IOPIN_PORTA -#define FPGA_MAIN_INIT_PIN 5 /* PA5 */ -#define FPGA_MAIN_DONE_PORT IOPIN_PORTA -#define FPGA_MAIN_DONE_PIN 6 /* PA6 */ - -#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA -#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ -#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA -#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ -#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA -#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ -#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA -#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ - -/* - * FPGA Interrupt configuration - */ -#define FPGA_MAIN_IRQ SIU_INT_IRQ2 - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 970460d5f2..5a5f9400c3 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -27,7 +27,7 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x00908000 -#define CONFIG_SPL_MAX_SIZE (64 * 1024) +#define CONFIG_SPL_MAX_SIZE 0x10000 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" #define CONFIG_SPL_STACK 0x0091FFB8 #define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -46,7 +46,7 @@ #if defined(CONFIG_SPL_MMC_SUPPORT) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) #endif @@ -58,7 +58,7 @@ /* Define the payload for FAT/EXT support */ #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_LIBDISK_SUPPORT #endif diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 3502d10472..d83e07e242 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -17,14 +17,15 @@ /* U-Boot general configuration */ #define CONFIG_SYS_PROMPT "K2E EVM # " -#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" - -#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0" -#define KS2_ADDR_MON "addr_mon=0x0c140000\0" -#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0" -#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0" -#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0" +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "addr_mon=0x0c140000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "name_fdt=uImage-k2e-evm.dtb\0" \ + "name_mon=skern-k2e-evm.bin\0" \ + "name_ubi=k2e-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2e-evm.gph\0" \ + "name_fs=arago-console-image-k2e-evm.cpio.gz\0" #include <configs/ks2_evm.h> @@ -34,4 +35,9 @@ /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_2K +/* Network */ +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 9 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 8aa616da0e..ffddf1391c 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -17,14 +17,15 @@ /* U-Boot general configuration */ #define CONFIG_SYS_PROMPT "K2HK EVM # " -#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" - -#define KS2_FDT_NAME "name_fdt=k2hk-evm.dtb\0" -#define KS2_ADDR_MON "addr_mon=0x0c5f0000\0" -#define KS2_NAME_MON "name_mon=skern-k2hk-evm.bin\0" -#define NAME_UBOOT "name_uboot=u-boot-spi-k2hk-evm.gph\0" -#define NAME_UBI "name_ubi=k2hk-evm-ubifs.ubi\0" +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "addr_mon=0x0c5f0000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "name_fdt=uImage-k2hk-evm.dtb\0" \ + "name_mon=skern-k2hk-evm.bin\0" \ + "name_ubi=k2hk-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ + "name_fs=arago-console-image-k2hk-evm.cpio.gz\0" #include <configs/ks2_evm.h> @@ -35,6 +36,7 @@ #define CONFIG_SYS_NAND_PAGE_2K /* Network */ -#define CONFIG_DRIVER_TI_KEYSTONE_NET +#define CONFIG_KSNET_NETCP_V1_0 +#define CONFIG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h new file mode 100644 index 0000000000..805164a679 --- /dev/null +++ b/include/configs/k2l_evm.h @@ -0,0 +1,43 @@ +/* + * Configuration header file for TI's k2l-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2L_EVM_H +#define __CONFIG_K2L_EVM_H + +/* Platform type */ +#define CONFIG_SOC_K2L +#define CONFIG_K2L_EVM + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2L EVM # " + +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "addr_mon=0x0c140000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0" \ + "name_fdt=uImage-k2l-evm.dtb\0" \ + "name_mon=skern-k2l-evm.bin\0" \ + "name_ubi=k2l-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2l-evm.gph\0" \ + "name_fs=arago-console-image-k2l-evm.cpio.gz\0" + +#include <configs/ks2_evm.h> + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c100000 + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_4K + +/* Network */ +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 5 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + +#endif /* __CONFIG_K2L_EVM_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index e015e9091b..3ccadd0af7 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -38,7 +38,12 @@ #define CONFIG_FAT_WRITE #define CONFIG_EXT4_WRITE +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else #define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_GENERIC_BOARD @@ -69,8 +74,13 @@ #define CONFIG_TMU_TIMER /* STACK */ -#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffc -#define STACK_AREA_SIZE 0xC000 +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC +#endif + +#define STACK_AREA_SIZE 0xC000 #define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 137d9b0d32..dd5050fbe9 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -91,6 +91,8 @@ #define CONFIG_SYS_SPI2_NUM_CS 4 /* Network Configuration */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_MARVELL #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS @@ -98,11 +100,52 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 32 #define CONFIG_NET_MULTI -#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5 #define CONFIG_SYS_SGMII_REFCLK_MHZ 312 #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 #define CONFIG_SYS_SGMII_RATESCALE 2 +/* Keyston Navigator Configuration */ +#define CONFIG_TI_KSNAV +#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS +#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE +#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE +#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE +#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE +#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE +#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE +#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE +#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE +#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE +#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE +#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE +#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM +#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM + +/* NETCP pktdma */ +#define CONFIG_KSNAV_PKTDMA_NETCP +#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE +#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE +#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM +#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM +#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM +#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE +#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE +#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE + +/* Keystone net */ +#define CONFIG_DRIVER_TI_KEYSTONE_NET +#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR +#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE +#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE +#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE +#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES + +/* SerDes */ +#define CONFIG_TI_KEYSTONE_SERDES + /* AEMIF */ #define CONFIG_TI_AEMIF #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE @@ -153,6 +196,20 @@ "1024k(bootloader)ro,512k(params)ro," \ "-(ubifs)" +/* USB Configuration */ +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_KEYSTONE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_FS_FAT +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE +#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE +#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE +#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE + /* U-Boot command configuration */ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV @@ -166,9 +223,13 @@ #define CONFIG_CMD_UBIFS #define CONFIG_CMD_SF #define CONFIG_CMD_EEPROM +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC /* U-Boot general configuration */ #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_MISC_INIT_R #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_PBSIZE 2048 #define CONFIG_SYS_MAXARGS 16 @@ -186,30 +247,25 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_EXTRA_ENV_SETTINGS \ - "boot=ramfs\0" \ + CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "boot=ubi\0" \ "tftp_root=/\0" \ "nfs_root=/export\0" \ "mem_lpae=1\0" \ "mem_reserve=512M\0" \ "addr_fdt=0x87000000\0" \ "addr_kern=0x88000000\0" \ - KS2_ADDR_MON \ "addr_uboot=0x87000000\0" \ "addr_fs=0x82000000\0" \ "addr_ubi=0x82000000\0" \ "addr_secdb_key=0xc000000\0" \ "fdt_high=0xffffffff\0" \ - KS2_FDT_NAME \ - "name_fs=arago-console-image.cpio.gz\0" \ - "name_kern=uImage\0" \ - KS2_NAME_MON \ - NAME_UBOOT \ - NAME_UBI \ + "name_kern=uImage-keystone-evm.bin\0" \ "run_mon=mon_install ${addr_mon}\0" \ "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ "init_net=run args_all args_net\0" \ "init_ubi=run args_all args_ubi; " \ - "ubi part ubifs; ubifsmount boot;" \ + "ubi part ubifs; ubifsmount ubi:boot;" \ "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \ "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ @@ -223,7 +279,6 @@ "burn_uboot_nand=nand erase 0 0x100000; " \ "nand write ${addr_uboot} 0 ${filesize}\0" \ "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ - KS2_ARGS_UBI \ "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ "${nfs_options} ip=dhcp\0" \ @@ -265,8 +320,4 @@ #include <asm/arch/clock.h> #define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) -/* Maximum memory size for relocated U-boot at the end of the DDR3 memory - which is NOT applicable for DDR ECC test */ -#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */ - #endif /* __CONFIG_KS2_EVM_H */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 699135fc0e..a814b4cccc 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -39,7 +39,11 @@ #define CONFIG_FAT_WRITE #define CONFIG_EXT4_WRITE +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0xB0000000 +#else #define CONFIG_SYS_TEXT_BASE 0xE8080000 +#endif #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_GENERIC_BOARD @@ -70,8 +74,12 @@ #define CONFIG_TMU_TIMER /* STACK */ -#define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc -#define STACK_AREA_SIZE 0xC000 +#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC +#endif +#define STACK_AREA_SIZE 0xC000 #define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index efe770b81b..5c209913e5 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -171,6 +171,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "consdev=ttyAMA0\0" \ "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ "bootdev=/dev/mmcblk0p2\0" \ "rootdev=/dev/mmcblk0p3\0" \ "netdev=eth0\0" \ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index cd85a6c9e8..b775ebd0ed 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -172,9 +172,6 @@ #define CONFIG_BOOTFILE "uImage" -#define xstr(s) str(s) -#define str(s) #s - /* Setup MTD for NAND on the SOM */ #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ @@ -201,13 +198,13 @@ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "baudrate=115200\0" \ "consoledev=ttyO2\0" \ - "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ + "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ "loadaddr=0x82000000\0" \ "load=tftp ${loadaddr} ${u-boot}\0" \ "load_k=tftp ${loadaddr} ${bootfile}\0" \ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ "loadmlo=tftp ${loadaddr} ${mlo}\0" \ - "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \ + "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ "mmcargs=root=/dev/mmcblk0p2 rw " \ "rootfstype=ext3 rootwait\0" \ "mmcboot=echo Booting from mmc ...; " \ @@ -221,7 +218,7 @@ "bootm ${loadaddr}\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \ + "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ "uboot_addr=0x80000\0" \ "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ "nand write ${loadaddr} ${uboot_addr} 80000\0" \ @@ -372,8 +369,8 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" /* NAND boot config */ #define CONFIG_SYS_NAND_PAGE_COUNT 64 diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 6c19817f86..0b9cbae5ba 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -15,6 +15,9 @@ #define __CONFIG_H #define CONFIG_MECP5123 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the MECP5123 board: * diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 7de245b33c..41ae0a53f8 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -12,6 +12,9 @@ #define __CONFIG_H #define CONFIG_MPC5121ADS 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the MPC5121ADS board: * diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 135a3f51f0..e0528ce4b9 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -29,5 +29,6 @@ #endif #define CONFIG_MP +#define CONFIG_MXC_GPT_HCLK #endif diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 0ab31279cc..235dd6d33f 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -32,6 +32,9 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } + #include "mx6sabre_common.h" #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 2d93d6c700..c81e9e9747 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -260,4 +260,21 @@ #define CONFIG_CMD_CACHE #endif +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index e666ebb998..938030d56d 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -32,23 +32,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ #endif -/* Framebuffer */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IPUV3_CLK 260000000 -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #define CONFIG_CMD_PCI #ifdef CONFIG_CMD_PCI #define CONFIG_PCI diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index fddedf1a8e..4fcaf515c7 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -190,7 +190,6 @@ #define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ @@ -210,4 +209,9 @@ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index eb96fc17f3..dea8227aeb 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -148,7 +148,8 @@ /* I2C */ #ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MXS +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXS #define CONFIG_HARD_I2C #ifndef CONFIG_SYS_I2C_SPEED #define CONFIG_SYS_I2C_SPEED 400000 diff --git a/include/configs/novena.h b/include/configs/novena.h new file mode 100644 index 0000000000..879141a7ca --- /dev/null +++ b/include/configs/novena.h @@ -0,0 +1,298 @@ +/* + * Configuration settings for the Novena U-boot. + * + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* System configurations */ +#define CONFIG_MX6 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_FIT +#define CONFIG_KEYBOARD +#define CONFIG_MXC_GPIO +#define CONFIG_OF_LIBFDT +#define CONFIG_REGEX +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_NO_FLASH + +#include "configs/mx6_common.h" +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include <config_cmd_default.h> + +/* U-Boot Commands */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_I2C +#define CONFIG_CMD_FUSE +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SATA +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_TIME +#define CONFIG_CMD_USB +#define CONFIG_VIDEO + +/* U-Boot general configurations */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER + +/* U-Boot environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SIZE (16 * 1024) +/* + * Environment is on MMC, starting at offset 512KiB from start of the card. + * Please place first partition at offset 1MiB from the start of the card + * as recommended by GNU/fdisk. See below for details: + * http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET (512 * 1024) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_BOOTARGS "console=ttymxc1,115200 " +#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_LOADADDR 0x18000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_HOSTNAME novena + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE 0xF0000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) + +/* SPL */ +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" /* common IMX6 SPL configuration */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Ethernet Configuration */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0x7 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_ARP_TIMEOUT 200UL +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C EEPROM */ +#ifdef CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_SPD_BUS_NUM 2 +#endif + +/* MMC Configs */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* OCOTP Configs */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* PCI express */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) +#endif + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* SATA Configs */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_INDEX 1 + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +/* Gadget part */ +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#endif + +/* Video output */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* Extra U-Boot environment. */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "consdev=ttymxc1\0" \ + "baudrate=115200\0" \ + "bootdev=/dev/mmcblk0p1\0" \ + "rootdev=/dev/mmcblk0p2\0" \ + "netdev=eth0\0" \ + "kernel_addr_r=0x18000000\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "addargs=run addcons addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "update_sd_spl_filename=SPL\0" \ + "update_sd_uboot_filename=u-boot.img\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if dhcp ${update_sd_spl_filename} ; then " \ + "mmc write ${loadaddr} 2 0x200 ; " \ + "fi ; " \ + "if dhcp ${update_sd_uboot_filename} ; then " \ + "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\ + "fi ; " \ + "fi\0" \ + +#endif /* __CONFIG_H */ diff --git a/include/configs/o2d.h b/include/configs/o2d.h index eff1bcef3b..b2905b2697 100644 --- a/include/configs/o2d.h +++ b/include/configs/o2d.h @@ -43,8 +43,8 @@ #define CONFIG_BOARD_NAME "o2d" #define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT xstr(126) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(126) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -56,7 +56,7 @@ "ramtop=fc55ffff\0" \ "jffbot=fc560000\0" \ "jfftop=fcffffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=fc03ffff\0" \ "kernel_addr=0xfc060000\0" \ "ramdisk_addr=0xfc160000\0" \ diff --git a/include/configs/o2d300.h b/include/configs/o2d300.h index 1af53834f7..a8222d9f97 100644 --- a/include/configs/o2d300.h +++ b/include/configs/o2d300.h @@ -44,8 +44,8 @@ #define CONFIG_BOARD_NAME "o2d300" #define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT xstr(126) -#define BOARD_POST_CRC32_END xstr(0x02000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(126) +#define BOARD_POST_CRC32_END __stringify(0x02000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -63,7 +63,7 @@ "ramtop=fc57ffff\0" \ "jffbot=fc580000\0" \ "jfftop=fd39ffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=fc03ffff\0" \ "halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0" \ "halbot=fd3a0000\0" \ diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index 133dc6f8cd..18388d150b 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -17,6 +17,8 @@ * High Level Configuration Options */ #define CONFIG_MPC5200 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */ @@ -114,9 +116,6 @@ #undef CONFIG_BOOTARGS -#define xstr(s) str(s) -#define str(s) #s - #if !defined(CONFIG_CONSOLE_DEV) #define CONFIG_CONSOLE_DEV "ttyPSC1" #endif @@ -158,7 +157,7 @@ "kernel_addr_r=600000\0" \ "initrd_high=0x03e00000\0" \ "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \ - "memtest=mtest 0x00100000 "xstr(CONFIG_SYS_MEMTEST_END)" 0 1\0" \ + "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ @@ -182,7 +181,7 @@ "unlock=yes\0" \ "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \ "setenv bootdelay 1;" \ - "crc32 "xstr(CONFIG_SYS_TEXT_BASE)" " \ + "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \ BOARD_POST_CRC32_END";" \ "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0" diff --git a/include/configs/o2dnt2.h b/include/configs/o2dnt2.h index 3636c0e1d4..1b765a7e4e 100644 --- a/include/configs/o2dnt2.h +++ b/include/configs/o2dnt2.h @@ -43,8 +43,8 @@ #define CONFIG_BOARD_NAME "o2dnt2" #define CONFIG_BOARD_BOOTCMD "run flash_self" -#define CONFIG_BOARD_MEM_LIMIT xstr(126) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(126) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -56,7 +56,7 @@ "ramtop=fc55ffff\0" \ "jffbot=fc560000\0" \ "jfftop=fce5ffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=fc03ffff\0" \ "calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \ "calbot=fce60000\0" \ diff --git a/include/configs/o2i.h b/include/configs/o2i.h index 8fe1da58bb..c0fcedaf10 100644 --- a/include/configs/o2i.h +++ b/include/configs/o2i.h @@ -37,8 +37,8 @@ #define CONFIG_BOARD_NAME "o2i" #define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT xstr(62) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(62) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -52,7 +52,7 @@ "jfftop=ffebffff\0" \ "kernel_addr=0xff060000\0" \ "ramdisk_addr=0xff160000\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=ff03ffff\0" \ "autoload=no\0" \ "dhcp_boot=run dhcpcmd; run flash_mtd\0" \ diff --git a/include/configs/o2mnt.h b/include/configs/o2mnt.h index c2164b5efb..eb63cb0c85 100644 --- a/include/configs/o2mnt.h +++ b/include/configs/o2mnt.h @@ -39,8 +39,8 @@ #define CONFIG_BOARD_NAME "o2mnt" #define CONFIG_BOARD_BOOTCMD "${newcmd}" -#define CONFIG_BOARD_MEM_LIMIT xstr(62) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(62) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #ifndef CONFIG_IFM_SENSOR_TYPE #define CONFIG_IFM_SENSOR_TYPE "O2M110" @@ -56,7 +56,7 @@ "ramtop=ffc5ffff\0" \ "jffbot=ffc60000\0" \ "jfftop=ffffffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=ff03ffff\0" \ "kernel_addr=0xff060000\0" \ "ramdisk_addr=0xff260000\0" \ diff --git a/include/configs/o3dnt.h b/include/configs/o3dnt.h index 05cd360815..77907507b3 100644 --- a/include/configs/o3dnt.h +++ b/include/configs/o3dnt.h @@ -44,8 +44,8 @@ #define CONFIG_BOARD_NAME "o3dnt" #define CONFIG_BOARD_BOOTCMD "run flash_self" -#define CONFIG_BOARD_MEM_LIMIT xstr(62) -#define BOARD_POST_CRC32_END xstr(0x01000000) +#define CONFIG_BOARD_MEM_LIMIT __stringify(62) +#define BOARD_POST_CRC32_END __stringify(0x01000000) #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_IFM_DEFAULT_ENV_SETTINGS \ @@ -57,7 +57,7 @@ "ramtop=fc55ffff\0" \ "jffbot=fc560000\0" \ "jfftop=fce5ffff\0" \ - "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \ + "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ "ubotop=fc03ffff\0" \ "calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \ "calbot=fce60000\0" \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index b7638fb8a6..27bf89c114 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -75,8 +75,8 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" /* Partition tables */ #define CONFIG_EFI_PARTITION diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 50929aaea2..2daf13c642 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -87,7 +87,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif /* __OMAP3_EVM_QUICK_MMC_H */ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 006c9a9c0d..b2b3750c1e 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -29,8 +29,6 @@ #define CONFIG_REVISION_TAG 1 -#define CONFIG_SUPPORT_RAW_INITRD - /* define to enable boot progress via leds */ #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index b17e495f5f..c58636a541 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -35,6 +35,13 @@ /* TWL4030 LED */ #define CONFIG_TWL4030_LED +/* USB EHCI */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + /* Initialize GPIOs by default */ #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */ #define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */ @@ -44,6 +51,7 @@ /* commands to include */ #define CONFIG_CMD_CACHE +#define CONFIG_CMD_USB #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_NFS /* NFS support */ @@ -131,8 +139,9 @@ "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "nand read ${loadaddr} linux; " \ - "bootm ${loadaddr}\0" \ + "if nand read ${loadaddr} linux; then " \ + "bootm ${loadaddr};" \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 071880fe75..d7696bd203 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -47,7 +47,7 @@ #define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 2 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)<<8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 25000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h deleted file mode 100644 index a210e293a9..0000000000 --- a/include/configs/p3mx.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Based on original work by - * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards - * - * The defines: - * CONFIG_P3M750 or - * CONFIG_P3M7448 - * are written into include/config.h by the "make xxx_config" command - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_P3Mx /* used for both board versions */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#if defined (CONFIG_P3M750) -#define CONFIG_750FX /* 750GL/GX/FX */ -#define CONFIG_HIGH_BATS /* High BATs supported */ -#define CONFIG_SYS_BOARD_NAME "P3M750" -#define CONFIG_SYS_BUS_CLK 100000000 -#define CONFIG_SYS_TCLK 100000000 -#elif defined (CONFIG_P3M7448) -#define CONFIG_74xx -#define CONFIG_SYS_BOARD_NAME "P3M7448" -#define CONFIG_SYS_BUS_CLK 133333333 -#define CONFIG_SYS_TCLK 133333333 -#endif -#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ - -/* which initialization functions to call for this board */ -#define CONFIG_SYS_BOARD_ASM_INIT 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#ifdef CONFIG_P3M750 -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#if defined (CONFIG_P3M750) -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */ -#define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */ -#elif defined (CONFIG_P3M7448) -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */ -#define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */ -#endif -#define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */ -#define CONFIG_SYS_MONITOR_BASE 0xfff00000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -#define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */ -#define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */ - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ - /* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#undef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x42000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_MPSC /* MV64460 Serial */ -#define CONFIG_MPSC_PORT 0 -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Ethernet - *----------------------------------------------------------------------*/ -/* Change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CONFIG_SYS_ETH_PORT ETH_0 -#define MV_ETH_DEVS 2 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#if defined (CONFIG_P3M750) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */ -#elif defined (CONFIG_P3M7448) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ -#endif -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_MV64460_ECC - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */ - -/* I2C RTC */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#undef CONFIG_PCI /* include pci support */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ -#endif /* CONFIG_PCI */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI_IDSEL 0x30 - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "u-boot=p3mx/u-boot/u-boot.bin\0" \ - "load=tftp 100000 ${u-boot}\0" \ - "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "serverip=11.0.0.152\0" - -#if defined (CONFIG_P3M750) -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "hostname=p3m750\0" \ - "bootfile=/tftpboot/p3mx/vxWorks.st\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc180000\0" \ - "vxfile=p3m750/vxWorks\0" \ - "vxuser=ddg\0" \ - "vxpass=ddg\0" \ - "vxtarget=target\0" \ - "vxflags=0x8\0" \ - "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \ - "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \ - "f=${vxflags}\0" -#elif defined (CONFIG_P3M7448) -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "hostname=p3m7448\0" -#endif - -#if defined (CONFIG_P3M750) -#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx" -#elif defined (CONFIG_P3M7448) -#define CONFIG_BOOTCOMMAND " " -#endif - -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_PCI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_SDRAM - - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * Marvell MV64460 config settings - *----------------------------------------------------------------------*/ -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */ -#if defined (CONFIG_P3M750) -#define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/ -#elif defined (CONFIG_P3M7448) -#define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */ -#endif - -/* - * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered) - * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered) - * MPP[2] NC - * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered) - * MPP[4] PCI Monarch# GPIO IN Connected to P12 - * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered) - * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14 - * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14 - * MPP[8] Reserved Do not use - * MPP[9] Reserved Do not use - * MPP[10] Reserved Do not use - * MPP[11] Reserved Do not use - * MPP[12] Phy 0 Interrupt Int IN - * MPP[13] Phy 1 Interrupt Int IN - * MPP[14] NC - * MPP[15] NC - * MPP[16] PCI Interrupt C Int IN Connected to P11 - * MPP[17] PCI Interrupt D Int IN Connected to P11 - * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24] - * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic - * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog - * MPP[21] NC - * MPP[22] GP LED Green GPIO OUT - * MPP[23] GP LED Red GPIO OUT - * MPP[24] Watchdog NMI# Int OUT - * MPP[25] NC - * MPP[26] NC - * MPP[27] PCI Interrupt A Int IN Connected to P11 - * MPP[28] NC - * MPP[29] PCI Interrupt B Int IN Connected to P11 - * MPP[30] Module reset GPIO OUT Board reset - * MPP[31] PCI EReady GPIO IN Connected to P12 - */ -#define CONFIG_SYS_MPP_CONTROL_0 0x00303022 -#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 -#define CONFIG_SYS_MPP_CONTROL_2 0x00004000 -#define CONFIG_SYS_MPP_CONTROL_3 0x00000004 -#define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* set rest out of range for Linux !!!!!!!!!!! */ - -/* IBAT5 and DBAT5 */ -#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* IBAT6 and DBAT6 */ -#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* IBAT7 and DBAT7 */ -#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ -#define CONFIG_SYS_L2 - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#ifndef __ASSEMBLY__ -#include <../board/Marvell/include/core.h> -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index f92496571b..1c04a58e9f 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -29,8 +29,6 @@ #endif #endif -#define CONFIG_SYS_LITTLE_ENDIAN - #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 553eb8f967..17d7bcab00 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -13,6 +13,8 @@ #define __CONFIG_H #define CONFIG_PDM360NG 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD /* * Memory map for the PDM360NG board: diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h index a28d7b579a..005a853f56 100644 --- a/include/configs/ph1_ld4.h +++ b/include/configs/ph1_ld4.h @@ -28,14 +28,10 @@ * SoC UART : enable CONFIG_UNIPHIER_SERIAL * On-board UART: enable CONFIG_SYS_NS16550_SERIAL */ -#if 1 -#define CONFIG_UNIPHIER_SERIAL -#else +#if 0 #define CONFIG_SYS_NS16550_SERIAL #endif -#define CONFIG_SYS_UNIPHIER_UART_CLK 36864000 - #define CONFIG_SMC911X #define CONFIG_DDR_NUM_CH0 1 diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h index b79967f7da..7dd6fd2a92 100644 --- a/include/configs/ph1_pro4.h +++ b/include/configs/ph1_pro4.h @@ -28,14 +28,10 @@ * SoC UART : enable CONFIG_UNIPHIER_SERIAL * On-board UART: enable CONFIG_SYS_NS16550_SERIAL */ -#if 1 -#define CONFIG_UNIPHIER_SERIAL -#else +#if 0 #define CONFIG_SYS_NS16550_SERIAL #endif -#define CONFIG_SYS_UNIPHIER_UART_CLK 73728000 - #define CONFIG_SMC911X #define CONFIG_DDR_NUM_CH0 2 diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h index 9d391f1d74..1062aace38 100644 --- a/include/configs/ph1_sld8.h +++ b/include/configs/ph1_sld8.h @@ -28,14 +28,10 @@ * SoC UART : enable CONFIG_UNIPHIER_SERIAL * On-board UART: enable CONFIG_SYS_NS16550_SERIAL */ -#if 1 -#define CONFIG_UNIPHIER_SERIAL -#else +#if 0 #define CONFIG_SYS_NS16550_SERIAL #endif -#define CONFIG_SYS_UNIPHIER_UART_CLK 80000000 - #define CONFIG_SMC911X #define CONFIG_DDR_NUM_CH0 1 diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index d9475e950b..ca27f9ad78 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -82,6 +82,16 @@ #define CONFIG_MMC_SDHCI_IO_ACCESSORS #define CONFIG_BCM2835_SDHCI +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_DWC2_REG_ADDR 0x20980000 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MISC_INIT_R +#endif + /* Console UART */ #define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK 3000000 @@ -129,13 +139,7 @@ /* Some things don't make sense on this HW or yet */ #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS #undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_PING /* Environment */ #define ENV_DEVICE_SETTINGS \ @@ -176,7 +180,10 @@ "ramdisk_addr_r=0x02100000\0" \ #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 0dfb7e7918..5b77db2698 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -230,8 +230,8 @@ #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index c46baf254f..dfbf3cb786 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -276,8 +276,8 @@ #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 1ce0965912..0d5dba18b1 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -148,8 +148,8 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_FS_FAT diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 49504dcafb..83a1bcdfbe 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -22,7 +22,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R +#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_SYS_NO_FLASH #define CONFIG_CLOCKS @@ -157,6 +157,21 @@ #define CONFIG_BAUDRATE 115200 /* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_STORAGE +/* + * NOTE: User must define either of the following to select which + * of the two USB controllers available on SoCFPGA to use. + * The DWC2 driver doesn't support multiple USB controllers. + * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS + * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS + */ +#endif + +/* * U-Boot environment */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV @@ -167,16 +182,21 @@ /* * SPL + * + * SRAM Memory layout: + * + * 0xFFFF_0000 ...... Start of SRAM + * 0xFFFF_xxxx ...... Top of stack (grows down) + * 0xFFFF_yyyy ...... Malloc area + * 0xFFFF_zzzz ...... Global Data + * 0xFFFF_FF00 ...... End of SRAM */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_STACK_SIZE (4 * 1024) -#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */ -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) +#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ #define CONFIG_CRC32_VERIFY diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 60d7e20e83..942738c138 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -55,10 +55,8 @@ #if defined(CONFIG_CMD_NET) #define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII -#define CONFIG_EPHY0_PHY_ADDR 0 /* PHY */ -#define CONFIG_EPHY1_PHY_ADDR 4 #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 #define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index c0eba3721d..a11f4ed2e1 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -37,8 +37,8 @@ #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" /* I2C driver configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DW_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW #if defined(CONFIG_SPEAR600) #define CONFIG_SYS_I2C_BASE 0xD0200000 #elif defined(CONFIG_SPEAR300) diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 5611ecc85f..e0ec52dcde 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -11,10 +11,10 @@ /* * A10 specific configuration */ -#define CONFIG_SUN4I /* sun4i SoC generation */ #define CONFIG_CLK_FULL_SPEED 1008000000 #define CONFIG_SYS_PROMPT "sun4i# " +#define CONFIG_MACH_TYPE 4104 #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index 6066371a17..09f7533575 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -11,10 +11,10 @@ /* * High Level Configuration Options */ -#define CONFIG_SUN5I /* sun5i SoC generation */ #define CONFIG_CLK_FULL_SPEED 1008000000 #define CONFIG_SYS_PROMPT "sun5i# " +#define CONFIG_MACH_TYPE 4138 #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h new file mode 100644 index 0000000000..b7144745c9 --- /dev/null +++ b/include/configs/sun6i.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> + * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * Configuration settings for the Allwinner A31 (sun6i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A31 specific configuration + */ + +#define CONFIG_SYS_PROMPT "sun6i# " + +/* + * Include common sunxi configuration where most the settings are + */ +#include <configs/sunxi-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index a902b84574..0193826a9d 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -12,10 +12,10 @@ /* * A20 specific configuration */ -#define CONFIG_SUN7I /* sun7i SoC generation */ #define CONFIG_CLK_FULL_SPEED 912000000 #define CONFIG_SYS_PROMPT "sun7i# " +#define CONFIG_MACH_TYPE 4283 #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h new file mode 100644 index 0000000000..6f1fc48cf0 --- /dev/null +++ b/include/configs/sun8i.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2014 Chen-Yu Tsai <wens@csie.org> + * + * Configuration settings for the Allwinner A23 (sun8i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A23 specific configuration + */ +#define CONFIG_SYS_PROMPT "sun8i# " + +/* + * Include common sunxi configuration where most the settings are + */ +#include <configs/sunxi-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 0c117bc5e7..ce038eddf0 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -27,6 +27,14 @@ #define CONFIG_SYS_TEXT_BASE 0x4a000000 +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM) +# define CONFIG_CMD_DM +# define CONFIG_DM_GPIO +# define CONFIG_DM_SERIAL +# define CONFIG_DW_SERIAL +# define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#endif + /* * Display CPU information */ @@ -36,12 +44,15 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_CLK 24000000 -#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE -#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE -#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE -#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE +#ifndef CONFIG_DM_SERIAL +# define CONFIG_SYS_NS16550_REG_SIZE -4 +# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE +# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE +# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE +# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE +# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE +#endif /* DRAM Base */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -77,6 +88,7 @@ #define CONFIG_INITRD_TAG /* mmc config */ +#if !defined(CONFIG_UART0_PORT_F) #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_CMD_MMC @@ -84,6 +96,7 @@ #define CONFIG_MMC_SUNXI_SLOT 0 #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ +#endif /* 4MB of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) @@ -92,8 +105,8 @@ * Miscellaneous configurable options */ #define CONFIG_CMD_ECHO -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_GENERIC_BOARD @@ -181,6 +194,7 @@ /* GPIO */ #define CONFIG_SUNXI_GPIO +#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_CMD_GPIO /* Ethernet support */ @@ -225,16 +239,28 @@ "pxefile_addr_r=0x43200000\0" \ "ramdisk_addr_r=0x43300000\0" +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + #ifdef CONFIG_AHCI #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) #else #define BOOT_TARGET_DEVICES_SCSI(func) #endif +#ifdef CONFIG_USB_EHCI +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ + BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ - func(USB, usb, 0) \ + BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 8d2db27ecb..d687717dfb 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -305,8 +305,8 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index a55bde2368..2fddef3cab 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -178,8 +178,8 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index e86c36443b..aeabb1b7d5 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -144,8 +144,8 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 80976e7e3b..5ed86d9365 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -19,12 +19,23 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC +#ifndef CONFIG_SPL_BUILD +# define CONFIG_DM +# define CONFIG_CMD_DM +# define CONFIG_DM_GPIO +# define CONFIG_DM_SERIAL +# define CONFIG_OMAP_SERIAL +# define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#endif + #include <asm/arch/omap.h> /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) +#endif #define CONFIG_SYS_NS16550_CLK 48000000 /* Network defines. */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 85171dbb4c..a8790c2f8f 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -174,6 +174,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_ECHO #define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD /* * Common filesystems support. When we have removable storage we @@ -232,13 +233,13 @@ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ /* FAT sd card locations. */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #ifdef CONFIG_SPL_OS_BOOT /* FAT */ -#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" /* RAW SD card / eMMC */ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 3b19d3d6ba..3c634ee680 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -18,6 +18,15 @@ #include <asm/arch/cpu.h> #include <asm/arch/omap3.h> +#ifndef CONFIG_SPL_BUILD +# define CONFIG_DM +# define CONFIG_CMD_DM +# define CONFIG_DM_GPIO +# define CONFIG_DM_SERIAL +# define CONFIG_OMAP_SERIAL +# define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#endif + /* The chip has SDRC controller */ #define CONFIG_SDRC @@ -28,16 +37,20 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#ifdef CONFIG_SPL_BUILD +# define CONFIG_SYS_NS16550_SERIAL +# define CONFIG_SYS_NS16550_REG_SIZE (-4) +# define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#endif #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} /* Select serial console configuration */ #define CONFIG_CONS_INDEX 3 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SERIAL3 3 +#endif /* Physical Memory Map */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index b0f199e3f4..1c93aab1a7 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -167,6 +167,9 @@ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) +/* SPL: Allow to use an EXT partition */ +#define CONFIG_SPL_EXT_SUPPORT + #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ #endif diff --git a/include/configs/top9000.h b/include/configs/top9000.h deleted file mode 100644 index a96a9cb416..0000000000 --- a/include/configs/top9000.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * (C) Copyright 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - * - * Configuation settings for the TOP9000 CPU module with AT91SAM9XE. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * top9000 with at91sam9xe256 or at91sam9xe512 - * - * Initial Bootloader is in embedded flash. - * Vital Product Data, U-Boot Environment are in I2C-EEPROM. - * U-Boot is in embedded flash, a backup U-Boot can be in NAND flash. - * kernel and file system are either in NAND flash or on a micro SD card. - * NAND flash is optional. - * I2C EEPROM is never optional. - * SPI FRAM is optional. - * SPI ENC28J60 is optional. - * 16 or 32 bit wide SDRAM. - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SoC must be defined first, before hardware.h is included */ -#define CONFIG_AT91SAM9XE -#include <asm/hardware.h> - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires - * adapting the initial boot program. - */ -#define CONFIG_SYS_TEXT_BASE 0x20000000 /* start of SDRAM */ - -/* Command line configuration */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG -#define CONFIG_CMD_ASKENV -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_PROMPT "TOP9000> " -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CACHE - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ - -/* Misc CPU related */ -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_AT91RESET_EXTRST /* assert external reset */ - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 - -/* SD/MMC card */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9 -#define CONFIG_CMD_MMC - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_SYS_PHY_ID 1 -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 - -/* real time clock */ -#define CONFIG_RTC_AT91SAM9_RTT -#define CONFIG_CMD_DATE - -#if defined(CONFIG_AT91SAM9XE) -/* - * NOR flash - use embedded flash of SAM9XE256/512 - * U-Boot will not fit into 128K ! - * 2010.09 will not fit into 256K with all options enabled ! - * - * Layout: - * 16kB 1st Bootloader - * Rest U-Boot - * the first sector (16kB) of EFLASH cannot be unprotected - * with u-boot commands - */ -# define CONFIG_AT91_EFLASH -# define CONFIG_SYS_FLASH_BASE ATMEL_BASE_FLASH -# define CONFIG_SYS_MAX_FLASH_SECT 32 -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -# define CONFIG_SYS_FLASH_PROTECTION -# define CONFIG_EFLASH_PROTSECTORS 1 /* protect first sector */ -#endif - -/* SPI */ -#define CONFIG_ATMEL_SPI -#define CONFIG_CMD_SPI - -/* RAMTRON FRAM */ -#define CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI0 /* SPI used for FRAM is SPI0 */ -#define FRAM_SPI_BUS 0 -#define FRAM_CS_NUM 0 -#define CONFIG_SPI_FRAM_RAMTRON -#define CONFIG_SF_DEFAULT_SPEED 1000000 /* be conservative here... */ -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "FM25H20" - -/* Microchip ENC28J60 (second LAN) */ -#if defined(CONFIG_EVAL9000) -# define CONFIG_ENC28J60 -# define CONFIG_ATMEL_SPI1 /* SPI used for ENC28J60 is SPI1 */ -# define ENC_SPI_BUS 1 -# define ENC_CS_NUM 0 -# define ENC_SPI_CLOCK 1000000 -#endif /* CONFIG_EVAL9000 */ - -/* - * SDRAM: 1 bank, min 32, max 128 MB - * Initialized before u-boot gets started. - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01e00000) -#define CONFIG_SYS_LOAD_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x01000000) -/* - * Initial stack pointer: 16k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE) - -/* - * NAND flash: 256 MB (optional) - * - * Layout: - * 640kB: u-boot (includes space for spare sectors, handled by - * initial loader) - * 2MB: kernel - * rest: file system - */ -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 -#define CONFIG_CMD_NAND - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "top9000" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_USB - -/* I2C support must always be enabled */ -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F - -#define I2C0_PORT AT91_PIO_PORTA -#define SDA0_PIN 23 -#define SCL0_PIN 24 -#define I2C1_PORT AT91_PIO_PORTB -#define SDA1_PIN 12 -#define SCL1_PIN 13 -#define I2C_SOFT_DECLARATIONS void iic_init(void);\ - int iic_read(void);\ - void iic_sda(int);\ - void iic_scl(int); -#define I2C_ACTIVE -#define I2C_TRISTATE -#define I2C_INIT iic_init() -#define I2C_READ iic_read() -#define I2C_SDA(bit) iic_sda(bit) -#define I2C_SCL(bit) iic_scl(bit) -#define I2C_DELAY udelay(3) -/* EEPROM configuration */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_SIZE 0x2000 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -/* later: #define CONFIG_I2C_ENV_EEPROM_BUS 0 */ -/* ENV is always in I2C-EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0x1000 -#define CONFIG_ENV_SIZE 0x0f00 -/* VPD settings */ -#define CONFIG_SYS_I2C_FACT_ADDR 0x57 -#define CONFIG_SYS_FACT_OFFSET 0x1F00 -#define CONFIG_SYS_FACT_SIZE 0x0100 -/* later: #define CONFIG_MISC_INIT_R */ -/* define the next only if you want to allow users to enter VPD data */ -#define CONFIG_SYS_FACT_ENTRY -#ifndef __ASSEMBLY__ -extern void read_factory_r(void); -#endif - -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -/* - * add filesystem commands if we have at least 1 storage - * media with filesystem - */ -#if defined(CONFIG_NAND_ATMEL) \ - || defined(CONFIG_USB_ATMEL) \ - || defined(CONFIG_MMC) -# define CONFIG_DOS_PARTITION -# define CONFIG_CMD_FAT -# define CONFIG_CMD_EXT2 -/* later: #define CONFIG_CMD_JFFS2 */ -#endif - -/* add NET commands if we have at least 1 LAN */ -#if defined(CONFIG_MACB) || defined(CONFIG_ENC28J60) -# define CONFIG_CMD_PING -# define CONFIG_CMD_DHCP -# define CONFIG_CMD_MII -/* is this really needed ? */ -# define CONFIG_RESET_PHY_R -/* BOOTP options */ -# define CONFIG_BOOTP_BOOTFILESIZE -# define CONFIG_BOOTP_BOOTPATH -# define CONFIG_BOOTP_GATEWAY -# define CONFIG_BOOTP_HOSTNAME -#endif - -/* linux in NAND flash */ -#define CONFIG_BOOTCOUNT_LIMIT 1 -#define CONFIG_BOOTCOMMAND \ - "nand read 0x21000000 0xA0000 0x200000; bootm" -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 " \ - "root=/dev/mtdblock2 " \ - "mtdparts=atmel_nand:" \ - "640k(uboot)ro," \ - "2M(linux)," \ - "16M(root)," \ - "-(rest) " \ - "rw "\ - "rootfstype=jffs2" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -#endif diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index d97a9613ae..c94eee19a2 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -9,13 +9,26 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_MX6 + +/* SPL */ +/* #if defined(CONFIG_SPL_BUILD) */ + +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_EXT_SUPPORT + +/* common IMX6 SPL configuration */ +#include "imx6_spl.h" + +/* #endif */ + #include "mx6_common.h" #include <asm/arch/imx-regs.h> #include <asm/imx-common/gpio.h> #include <linux/sizes.h> -#define CONFIG_MX6 - #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #define PHYS_SDRAM_SIZE (512u * SZ_1M) #elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) @@ -57,7 +70,7 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(3, 19) << 8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 50000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 6ddf3d5d5e..6e7a7fbf28 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -348,8 +348,8 @@ #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h index 18fe277cad..b18ae6dfae 100644 --- a/include/configs/uniphier-common.h +++ b/include/configs/uniphier-common.h @@ -33,18 +33,17 @@ are defined. Select only one of them." # define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000) #endif +#ifdef CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE #define CONFIG_SYS_NS16550_CLK 12288000 #define CONFIG_SYS_NS16550_REG_SIZE -2 +#endif #define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE #define CONFIG_SMC911X_32_BIT -#define CONFIG_SYS_UNIPHIER_SERIAL_BASE0 0x54006800 -#define CONFIG_SYS_UNIPHIER_SERIAL_BASE1 0x54006900 -#define CONFIG_SYS_UNIPHIER_SERIAL_BASE2 0x54006a00 -#define CONFIG_SYS_UNIPHIER_SERIAL_BASE3 0x54006b00 +#define CONFIG_SYS_MALLOC_F_LEN 0x7000 /*----------------------------------------------------------------------- * MMU and Cache Setting diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 9fb501a341..809017c5fe 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -78,6 +78,15 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + /* Ethernet Configuration */ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 259205e881..d3d3e694cd 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -242,8 +242,6 @@ * Default environment and default scripts * to update uboot and load kernel */ -#define xstr(s) str(s) -#define str(s) #s #define CONFIG_HOSTNAME woodburn #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -263,9 +261,9 @@ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ "loadaddr=80800000\0" \ "kernel_addr_r=80800000\0" \ - "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ - "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ - "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ + "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ + "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ + "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \ "flash_self=run ramargs addip addtty addmtd addmisc;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ @@ -279,9 +277,9 @@ "run ramargs addip addtty addmtd addmisc;" \ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ "else echo Images not loades;fi\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ + "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ "update=protect off ${uboot_addr} +80000;" \ "erase ${uboot_addr} +80000;" \ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ diff --git a/include/configs/x600.h b/include/configs/x600.h index 71373e98f9..04187c0a31 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -83,8 +83,8 @@ #define CONFIG_SPEAR_GPIO /* I2C config options */ -#define CONFIG_HARD_I2C -#define CONFIG_DW_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW #define CONFIG_SYS_I2C_BASE 0xD0200000 #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02 @@ -181,26 +181,24 @@ #define CONFIG_UBI_PART ubi0 #define CONFIG_UBIFS_VOLUME rootfs -#define xstr(s) str(s) -#define str(s) #s - #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" #define CONFIG_EXTRA_ENV_SETTINGS \ "u-boot_addr=1000000\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \ + "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\ - "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ - "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};" \ + "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ " ${filesize};" \ - "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ "upd=run load update\0" \ - "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \ - "part=" xstr(CONFIG_UBI_PART) "\0" \ - "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \ + "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ + "part=" __stringify(CONFIG_UBI_PART) "\0" \ + "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ " ${filesize}\0" \ @@ -223,11 +221,12 @@ "saveenv;boot\0" \ "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ "root=ubi0:rootfs rootfstype=ubifs\0" \ - "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ "kernel_fs=/boot/uImage \0" \ "kernel_addr=1000000\0" \ - "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ - "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ + __stringify(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ "dtb_addr=1800000\0" \ "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 0b4dd665b8..2bc1562cec 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -268,10 +268,10 @@ #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" #endif /* Disable dcache for SPL just for sure */ @@ -283,8 +283,8 @@ /* Address in RAM where the parameters must be copied by SPL. */ #define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000 -#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "system.dtb" -#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "system.dtb" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" /* Not using MMC raw mode - just for compilation purpose */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 |
