diff options
Diffstat (limited to 'include/configs/CPC45.h')
| -rw-r--r-- | include/configs/CPC45.h | 262 |
1 files changed, 131 insertions, 131 deletions
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index a338af0e5c..91d262a22c 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -48,7 +48,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" @@ -89,60 +89,60 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #if 1 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ #endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif /* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 #if defined(CONFIG_BOOT_ROM) -#define CFG_FLASH_BASE 0xFF000000 +#define CONFIG_SYS_FLASH_BASE 0xFF000000 #else -#define CFG_FLASH_BASE 0xFF800000 +#define CONFIG_SYS_FLASH_BASE 0xFF800000 #endif -#define CFG_RESET_ADDRESS 0xFFF00100 +#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 -#define CFG_EUMB_ADDR 0xFCE00000 +#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 -#define CFG_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ /* Maximum amount of RAM. */ -#define CFG_MAX_RAM_SIZE 0x10000000 +#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE +#undef CONFIG_SYS_RAMBOOT #else -#define CFG_RAMBOOT +#define CONFIG_SYS_RAMBOOT #endif @@ -152,48 +152,48 @@ /* Size in bytes reserved for initial data */ -#define CFG_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_END 0x1000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) /* * NS16550 Configuration */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) -#define DUART_DCR (CFG_EUMB_ADDR + 0x4511) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) +#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511) /* * I2C configuration */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* * RTC configuration */ #define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* * EEPROM configuration */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 /* * Low Level Configuration Settings @@ -203,48 +203,48 @@ */ #define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_HZ 1000 +#define CONFIG_SYS_HZ 1000 /* Bit-field values for MCCR1. */ -#define CFG_ROMNAL 0 -#define CFG_ROMFAL 8 - -#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ -#define CFG_BANK1_ROW 0 -#define CFG_BANK2_ROW 0 -#define CFG_BANK3_ROW 0 -#define CFG_BANK4_ROW 0 -#define CFG_BANK5_ROW 0 -#define CFG_BANK6_ROW 0 -#define CFG_BANK7_ROW 0 +#define CONFIG_SYS_ROMNAL 0 +#define CONFIG_SYS_ROMFAL 8 + +#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ +#define CONFIG_SYS_BANK1_ROW 0 +#define CONFIG_SYS_BANK2_ROW 0 +#define CONFIG_SYS_BANK3_ROW 0 +#define CONFIG_SYS_BANK4_ROW 0 +#define CONFIG_SYS_BANK5_ROW 0 +#define CONFIG_SYS_BANK6_ROW 0 +#define CONFIG_SYS_BANK7_ROW 0 /* Bit-field values for MCCR2. */ -#define CFG_REFINT 0x2ec +#define CONFIG_SYS_REFINT 0x2ec /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#define CFG_BSTOPRE 160 +#define CONFIG_SYS_BSTOPRE 160 /* Bit-field values for MCCR3. */ -#define CFG_REFREC 2 /* Refresh to activate interval */ -#define CFG_RDLAT 0 /* Data latancy from read command */ +#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ +#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */ /* Bit-field values for MCCR4. */ -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CFG_ACTORW 2 -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 0 -#define CFG_REGDIMM 0 +#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ +#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ +#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ +#define CONFIG_SYS_ACTORW 2 +#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 +#define CONFIG_SYS_EXTROM 0 +#define CONFIG_SYS_REGDIMM 0 /* Memory bank settings. * Only bits 20-29 are actually used from these vales to set the @@ -253,79 +253,79 @@ * address. Refer to the MPC8240 book. */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0xff -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ +#define CONFIG_SYS_BANK0_START 0x00000000 +#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) +#define CONFIG_SYS_BANK0_ENABLE 1 +#define CONFIG_SYS_BANK1_START 0x3ff00000 +#define CONFIG_SYS_BANK1_END 0x3fffffff +#define CONFIG_SYS_BANK1_ENABLE 0 +#define CONFIG_SYS_BANK2_START 0x3ff00000 +#define CONFIG_SYS_BANK2_END 0x3fffffff +#define CONFIG_SYS_BANK2_ENABLE 0 +#define CONFIG_SYS_BANK3_START 0x3ff00000 +#define CONFIG_SYS_BANK3_END 0x3fffffff +#define CONFIG_SYS_BANK3_ENABLE 0 +#define CONFIG_SYS_BANK4_START 0x3ff00000 +#define CONFIG_SYS_BANK4_END 0x3fffffff +#define CONFIG_SYS_BANK4_ENABLE 0 +#define CONFIG_SYS_BANK5_START 0x3ff00000 +#define CONFIG_SYS_BANK5_END 0x3fffffff +#define CONFIG_SYS_BANK5_ENABLE 0 +#define CONFIG_SYS_BANK6_START 0x3ff00000 +#define CONFIG_SYS_BANK6_END 0x3fffffff +#define CONFIG_SYS_BANK6_ENABLE 0 +#define CONFIG_SYS_BANK7_START 0x3ff00000 +#define CONFIG_SYS_BANK7_END 0x3fffffff +#define CONFIG_SYS_BANK7_ENABLE 0 + +#define CONFIG_SYS_ODCR 0xff +#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ /* currently accessed page in memory */ /* see 8240 book for details */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ #define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ /* Warining: environment is not EMBEDDED in the ppcboot code. * It's stored in flash separately. */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x7F8000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000) #define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ #define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */ @@ -333,9 +333,9 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 +#define CONFIG_SYS_CACHELINE_SIZE 32 #if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* @@ -472,7 +472,7 @@ #define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define PCI_ENET0_IOADDR 0x82000000 #define PCI_ENET0_MEMADDR 0x82000000 @@ -486,8 +486,8 @@ #define CONFIG_I82365 -#define CFG_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE -#define CFG_PCMCIA_MEM_SIZE 0x1000 +#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE +#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000 #define CONFIG_PCMCIA_SLOT_A @@ -502,20 +502,20 @@ #undef CONFIG_IDE_RESET /* reset for IDE not supported */ #define CONFIG_IDE_LED /* LED for IDE is supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR +#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR -#define CFG_ATA_DATA_OFFSET CFG_PCMCIA_MEM_SIZE +#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE /* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) /* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x400) +#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400) #define CONFIG_DOS_PARTITION |
