diff options
Diffstat (limited to 'include/asm-sh')
| -rw-r--r-- | include/asm-sh/cpu_sh2.h | 40 | ||||
| -rw-r--r-- | include/asm-sh/cpu_sh4.h | 4 | ||||
| -rw-r--r-- | include/asm-sh/cpu_sh7203.h | 41 | ||||
| -rw-r--r-- | include/asm-sh/cpu_sh7723.h | 209 | ||||
| -rw-r--r-- | include/asm-sh/cpu_sh7785.h | 156 | ||||
| -rw-r--r-- | include/asm-sh/processor.h | 5 |
6 files changed, 454 insertions, 1 deletions
diff --git a/include/asm-sh/cpu_sh2.h b/include/asm-sh/cpu_sh2.h new file mode 100644 index 0000000000..8bc9bc64c5 --- /dev/null +++ b/include/asm-sh/cpu_sh2.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * Copyright (C) 2008 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH2_H_ +#define _ASM_CPU_SH2_H_ + +/* cache control */ +#define CCR_CACHE_STOP 0x00000008 +#define CCR_CACHE_ENABLE 0x00000005 +#define CCR_CACHE_ICI 0x00000008 + +#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 +#define CACHE_OC_WAY_SHIFT 13 +#define CACHE_OC_NUM_ENTRIES 256 +#define CACHE_OC_ENTRY_SHIFT 4 + +#if defined(CONFIG_CPU_SH7203) +# include <asm/cpu_sh7203.h> +#else +# error "Unknown SH2 variant" +#endif + +#endif /* _ASM_CPU_SH2_H_ */ diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h index 5a8a5a149c..b6cc6cfbd9 100644 --- a/include/asm-sh/cpu_sh4.h +++ b/include/asm-sh/cpu_sh4.h @@ -35,10 +35,14 @@ # include <asm/cpu_sh7750.h> #elif defined (CONFIG_CPU_SH7722) # include <asm/cpu_sh7722.h> +#elif defined (CONFIG_CPU_SH7723) +# include <asm/cpu_sh7723.h> #elif defined (CONFIG_CPU_SH7763) # include <asm/cpu_sh7763.h> #elif defined (CONFIG_CPU_SH7780) # include <asm/cpu_sh7780.h> +#elif defined (CONFIG_CPU_SH7785) +# include <asm/cpu_sh7785.h> #else # error "Unknown SH4 variant" #endif diff --git a/include/asm-sh/cpu_sh7203.h b/include/asm-sh/cpu_sh7203.h new file mode 100644 index 0000000000..77dcac43d3 --- /dev/null +++ b/include/asm-sh/cpu_sh7203.h @@ -0,0 +1,41 @@ +#ifndef _ASM_CPU_SH7203_H_ +#define _ASM_CPU_SH7203_H_ + +/* Cache */ +#define CCR1 0xFFFC1000 +#define CCR CCR1 + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PETCR 0xA4050106 + +/* Port Data Registers */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 + +/* BSC */ + +/* SDRAM controller */ + +/* SCIF */ +#define SCSMR_0 0xFFFE8000 +#define SCIF0_BASE SCSMR_0 + +/* Timer(CMT) */ +#define CMSTR 0xFFFEC000 +#define CMCSR_0 0xFFFEC002 +#define CMCNT_0 0xFFFEC004 +#define CMCOR_0 0xFFFEC006 +#define CMCSR_1 0xFFFEC008 +#define CMCNT_1 0xFFFEC00A +#define CMCOR_1 0xFFFEC00C + +/* On chip oscillator circuits */ +#define FRQCR 0xA415FF80 +#define WTCNT 0xA415FF84 +#define WTCSR 0xA415FF86 + +#endif /* _ASM_CPU_SH7203_H_ */ diff --git a/include/asm-sh/cpu_sh7723.h b/include/asm-sh/cpu_sh7723.h new file mode 100644 index 0000000000..6dac6e9a01 --- /dev/null +++ b/include/asm-sh/cpu_sh7723.h @@ -0,0 +1,209 @@ +/* + * (C) Copyright 2008 Renesas Solutions Corp. + * + * SH7723 Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH7723_H_ +#define _ASM_CPU_SH7723_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000090d + +/* EXP */ +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 + +/* MMU */ +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define PASCR 0xFF000070 +#define IRMCR 0xFF000078 + +/* CACHE */ +#define CCR 0xFF00001C +#define RAMCR 0xFF000074 + +/* INTC */ + +/* BSC */ +#define CMNCR 0xFEC10000 +#define CS0BCR 0xFEC10004 +#define CS2BCR 0xFEC10008 +#define CS4BCR 0xFEC10010 +#define CS5ABCR 0xFEC10014 +#define CS5BBCR 0xFEC10018 +#define CS6ABCR 0xFEC1001C +#define CS6BBCR 0xFEC10020 +#define CS0WCR 0xFEC10024 +#define CS2WCR 0xFEC10028 +#define CS4WCR 0xFEC10030 +#define CS5AWCR 0xFEC10034 +#define CS5BWCR 0xFEC10038 +#define CS6AWCR 0xFEC1003C +#define CS6BWCR 0xFEC10040 +#define RBWTCNT 0xFEC10054 + +/* SBSC */ +#define SBSC_SDCR 0xFE400008 +#define SBSC_SDWCR 0xFE40000C +#define SBSC_SDPCR 0xFE400010 +#define SBSC_RTCSR 0xFE400014 +#define SBSC_RTCNT 0xFE400018 +#define SBSC_RTCOR 0xFE40001C +#define SBSC_RFCR 0xFE400020 + +/* DMAC */ + +/* CPG */ +#define FRQCR 0xA4150000 +#define VCLKCR 0xA4150004 +#define SCLKACR 0xA4150008 +#define SCLKBCR 0xA415000C +#define IRDACLKCR 0xA4150018 +#define PLLCR 0xA4150024 +#define DLLFRQ 0xA4150050 + +/* LOW POWER MODE */ +#define STBCR 0xA4150020 +#define MSTPCR0 0xA4150030 +#define MSTPCR1 0xA4150034 +#define MSTPCR2 0xA4150038 + +/* RWDT */ +#define RWTCNT 0xA4520000 +#define RWTCSR 0xA4520004 +#define WTCNT RWTCNT + +/* TMU */ +#define TSTR 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 + +/* TPU */ + +/* CMT */ +#define CMSTR 0xA44A0000 +#define CMCSR 0xA44A0060 +#define CMCNT 0xA44A0064 +#define CMCOR 0xA44A0068 + +/* MSIOF */ + +/* SCIF */ +#define SCIF0_BASE 0xFFE00000 +#define SCIF1_BASE 0xFFE10000 +#define SCIF2_BASE 0xFFE20000 +#define SCIF3_BASE 0xa4e30000 +#define SCIF4_BASE 0xa4e40000 +#define SCIF5_BASE 0xa4e50000 + +/* RTC */ +/* IrDA */ +/* KEYSC */ +/* USB */ +/* IIC */ +/* FLCTL */ +/* VPU */ +/* VIO(CEU) */ +/* VIO(VEU) */ +/* VIO(BEU) */ +/* 2DG */ +/* LCDC */ +/* VOU */ +/* TSIF */ +/* SIU */ +/* ATAPI */ + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PDCR 0xA4050106 +#define PECR 0xA4050108 +#define PFCR 0xA405010A +#define PGCR 0xA405010C +#define PHCR 0xA405010E +#define PJCR 0xA4050110 +#define PKCR 0xA4050112 +#define PLCR 0xA4050114 +#define PMCR 0xA4050116 +#define PNCR 0xA4050118 +#define PQCR 0xA405011A +#define PRCR 0xA405011C +#define PSCR 0xA405011E +#define PTCR 0xA4050140 +#define PUCR 0xA4050142 +#define PVCR 0xA4050144 +#define PWCR 0xA4050146 +#define PXCR 0xA4050148 +#define PYCR 0xA405014A +#define PZCR 0xA405014C +#define PSELA 0xA405014E +#define PSELB 0xA4050150 +#define PSELC 0xA4050152 +#define PSELD 0xA4050154 +#define HIZCRA 0xA4050158 +#define HIZCRB 0xA405015A +#define HIZCRC 0xA405015C +#define HIZCRD 0xA405015E +#define MSELCRA 0xA4050180 +#define MSELCRB 0xA4050182 +#define PULCR 0xA4050184 +#define DRVCRA 0xA405018A +#define DRVCRB 0xA405018C + +/* I/O Port */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 +#define PDDR 0xA4050126 +#define PEDR 0xA4050128 +#define PFDR 0xA405012A +#define PGDR 0xA405012C +#define PHDR 0xA405012E +#define PJDR 0xA4050130 +#define PKDR 0xA4050132 +#define PLDR 0xA4050134 +#define PMDR 0xA4050136 +#define PNDR 0xA4050138 +#define PQDR 0xA405013A +#define PRDR 0xA405013C +#define PSDR 0xA405013E +#define PTDR 0xA4050160 +#define PUDR 0xA4050162 +#define PVDR 0xA4050164 +#define PWDR 0xA4050166 +#define PYDR 0xA4050168 +#define PZDR 0xA405016A + +/* UBC */ +/* H-UDI */ + +#endif /* _ASM_CPU_SH7723_H_ */ diff --git a/include/asm-sh/cpu_sh7785.h b/include/asm-sh/cpu_sh7785.h new file mode 100644 index 0000000000..4a4dfc9042 --- /dev/null +++ b/include/asm-sh/cpu_sh7785.h @@ -0,0 +1,156 @@ +#ifndef _ASM_CPU_SH7785_H_ +#define _ASM_CPU_SH7785_H_ + +/* + * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com> + * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#define CACHE_OC_NUM_WAYS 1 +#define CCR_CACHE_INIT 0x0000090b + +/* Exceptions */ +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 + +/* Cache Controller */ +#define CCR 0xFF00001C +#define QACR0 0xFF000038 +#define QACR1 0xFF00003C +#define RAMCR 0xFF000074 + +/* Watchdog Timer and Reset */ +#define WTCNT WDTCNT +#define WDTST 0xFFCC0000 +#define WDTCSR 0xFFCC0004 +#define WDTBST 0xFFCC0008 +#define WDTCNT 0xFFCC0010 +#define WDTBCNT 0xFFCC0018 + +/* Timer Unit */ +#define TSTR TSTR0 +#define TOCR 0xFFD80000 +#define TSTR0 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 +#define TCPR2 0xFFD8002C +#define TSTR1 0xFFDC0004 +#define TCOR3 0xFFDC0008 +#define TCNT3 0xFFDC000C +#define TCR3 0xFFDC0010 +#define TCOR4 0xFFDC0014 +#define TCNT4 0xFFDC0018 +#define TCR4 0xFFDC001C +#define TCOR5 0xFFDC0020 +#define TCNT5 0xFFDC0024 +#define TCR5 0xFFDC0028 + +/* Serial Communication Interface with FIFO */ +#define SCIF1_BASE 0xffeb0000 + +/* LBSC */ +#define MMSELR 0xfc400020 +#define LBSC_BASE 0xff800000 +#define BCR (LBSC_BASE + 0x1000) +#define CS0BCR (LBSC_BASE + 0x2000) +#define CS1BCR (LBSC_BASE + 0x2010) +#define CS2BCR (LBSC_BASE + 0x2020) +#define CS3BCR (LBSC_BASE + 0x2030) +#define CS4BCR (LBSC_BASE + 0x2040) +#define CS5BCR (LBSC_BASE + 0x2050) +#define CS6BCR (LBSC_BASE + 0x2060) +#define CS0WCR (LBSC_BASE + 0x2008) +#define CS1WCR (LBSC_BASE + 0x2018) +#define CS2WCR (LBSC_BASE + 0x2028) +#define CS3WCR (LBSC_BASE + 0x2038) +#define CS4WCR (LBSC_BASE + 0x2048) +#define CS5WCR (LBSC_BASE + 0x2058) +#define CS6WCR (LBSC_BASE + 0x2068) +#define CS5PCR (LBSC_BASE + 0x2070) +#define CS6PCR (LBSC_BASE + 0x2080) + +/* PCI Controller */ +#define SH7780_PCIECR 0xFE000008 +#define SH7780_PCIVID 0xFE040000 +#define SH7780_PCIDID 0xFE040002 +#define SH7780_PCICMD 0xFE040004 +#define SH7780_PCISTATUS 0xFE040006 +#define SH7780_PCIRID 0xFE040008 +#define SH7780_PCIPIF 0xFE040009 +#define SH7780_PCISUB 0xFE04000A +#define SH7780_PCIBCC 0xFE04000B +#define SH7780_PCICLS 0xFE04000C +#define SH7780_PCILTM 0xFE04000D +#define SH7780_PCIHDR 0xFE04000E +#define SH7780_PCIBIST 0xFE04000F +#define SH7780_PCIIBAR 0xFE040010 +#define SH7780_PCIMBAR0 0xFE040014 +#define SH7780_PCIMBAR1 0xFE040018 +#define SH7780_PCISVID 0xFE04002C +#define SH7780_PCISID 0xFE04002E +#define SH7780_PCICP 0xFE040034 +#define SH7780_PCIINTLINE 0xFE04003C +#define SH7780_PCIINTPIN 0xFE04003D +#define SH7780_PCIMINGNT 0xFE04003E +#define SH7780_PCIMAXLAT 0xFE04003F +#define SH7780_PCICID 0xFE040040 +#define SH7780_PCINIP 0xFE040041 +#define SH7780_PCIPMC 0xFE040042 +#define SH7780_PCIPMCSR 0xFE040044 +#define SH7780_PCIPMCSRBSE 0xFE040046 +#define SH7780_PCI_CDD 0xFE040047 +#define SH7780_PCICR 0xFE040100 +#define SH7780_PCILSR0 0xFE040104 +#define SH7780_PCILSR1 0xFE040108 +#define SH7780_PCILAR0 0xFE04010C +#define SH7780_PCILAR1 0xFE040110 +#define SH7780_PCIIR 0xFE040114 +#define SH7780_PCIIMR 0xFE040118 +#define SH7780_PCIAIR 0xFE04011C +#define SH7780_PCICIR 0xFE040120 +#define SH7780_PCIAINT 0xFE040130 +#define SH7780_PCIAINTM 0xFE040134 +#define SH7780_PCIBMIR 0xFE040138 +#define SH7780_PCIPAR 0xFE0401C0 +#define SH7780_PCIPINT 0xFE0401CC +#define SH7780_PCIPINTM 0xFE0401D0 +#define SH7780_PCIMBR0 0xFE0401E0 +#define SH7780_PCIMBMR0 0xFE0401E4 +#define SH7780_PCIMBR1 0xFE0401E8 +#define SH7780_PCIMBMR1 0xFE0401EC +#define SH7780_PCIMBR2 0xFE0401F0 +#define SH7780_PCIMBMR2 0xFE0401F4 +#define SH7780_PCIIOBR 0xFE0401F8 +#define SH7780_PCIIOBMR 0xFE0401FC +#define SH7780_PCICSCR0 0xFE040210 +#define SH7780_PCICSCR1 0xFE040214 +#define SH7780_PCICSAR0 0xFE040218 +#define SH7780_PCICSAR1 0xFE04021C +#define SH7780_PCIPDR 0xFE040220 + +#endif /* _ASM_CPU_SH7780_H_ */ diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index 388aa69c64..938a89cff5 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -1,6 +1,9 @@ #ifndef _ASM_SH_PROCESSOR_H_ #define _ASM_SH_PROCESSOR_H_ -#if defined CONFIG_SH3 +#if defined(CONFIG_SH2) || \ + defined (CONFIG_SH2A) +# include <asm/cpu_sh2.h> +#elif defined (CONFIG_SH3) # include <asm/cpu_sh3.h> #elif defined (CONFIG_SH4) || \ defined (CONFIG_SH4A) |
