diff options
Diffstat (limited to 'include/asm-arm')
| -rw-r--r-- | include/asm-arm/arch-arm1136/clocks.h | 8 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm1136/i2c.h | 1 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm1136/mem.h | 199 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm1136/omap2420.h | 19 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm1136/rev.h | 58 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm1136/sys_info.h | 8 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm1136/sys_proto.h | 3 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/hardware.h | 4 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_gen_module.h | 22 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_mem_module.h | 27 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_registers.h | 19 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91rm9200/AT91RM9200.h | 927 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91rm9200/hardware.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/mach-types.h | 1508 | ||||
| -rw-r--r-- | include/asm-arm/u-boot.h | 7 |
15 files changed, 2155 insertions, 657 deletions
diff --git a/include/asm-arm/arch-arm1136/clocks.h b/include/asm-arm/arch-arm1136/clocks.h index bd1b088326..2a95af1810 100644 --- a/include/asm-arm/arch-arm1136/clocks.h +++ b/include/asm-arm/arch-arm1136/clocks.h @@ -57,8 +57,7 @@ #define II_MPU_DIV 0x2 /* mpu = core/2 */ #define II_DSP_DIV 0x343 /* dsp & iva divider */ #define II_GFX_DIV 0x2 -#define II_BUS_DIV 0x04600C26 -#define II_BUS_DIV_ES1 0x04601026 +#define II_BUS_DIV 0x04601026 #define II_DPLL_300 0x01832100 /****************************************************************************; @@ -87,8 +86,7 @@ #define III_MPU_DIV 0x2 /* mpu = core/2 */ #define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ #define III_GFX_DIV 0x2 -#define III_BUS_DIV 0x08300c44 -#define III_BUS_DIV_ES1 0x08301044 +#define III_BUS_DIV 0x08301044 #define III_DPLL_266 0x01885500 /* set defaults for boot up */ @@ -98,7 +96,6 @@ # define DSP_DIV II_DSP_DIV # define GFX_DIV II_GFX_DIV # define BUS_DIV II_BUS_DIV -# define BUS_DIV_ES1 II_BUS_DIV_ES1 # define DPLL_VAL II_DPLL_300 #elif PRCM_CONFIG_III # define DPLL_OUT III_DPLL_OUT_X2 @@ -106,7 +103,6 @@ # define DSP_DIV III_DSP_DIV # define GFX_DIV III_GFX_DIV # define BUS_DIV III_BUS_DIV -# define BUS_DIV_ES1 III_BUS_DIV_ES1 # define DPLL_VAL III_DPLL_266 #endif diff --git a/include/asm-arm/arch-arm1136/i2c.h b/include/asm-arm/arch-arm1136/i2c.h index 3e37f4dab0..7248950e52 100644 --- a/include/asm-arm/arch-arm1136/i2c.h +++ b/include/asm-arm/arch-arm1136/i2c.h @@ -33,6 +33,7 @@ #define I2C_BUF (I2C_BASE + 0x14) #define I2C_CNT (I2C_BASE + 0x18) #define I2C_DATA (I2C_BASE + 0x1c) +#define I2C_SYSC (I2C_BASE + 0x20) #define I2C_CON (I2C_BASE + 0x24) #define I2C_OA (I2C_BASE + 0x28) #define I2C_SA (I2C_BASE + 0x2c) diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-arm1136/mem.h index 2ead7d83b9..c81f1c4370 100644 --- a/include/asm-arm/arch-arm1136/mem.h +++ b/include/asm-arm/arch-arm1136/mem.h @@ -13,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -25,8 +25,8 @@ #ifndef _OMAP24XX_MEM_H_ #define _OMAP24XX_MEM_H_ -#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ +#define SDRC_CS0_OSET 0x0 +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ #ifndef __ASSEMBLY__ /* struct's for holding data tables for current boards, they are getting used @@ -40,8 +40,7 @@ struct sdrc_data_s { u32 sdrc_rfr_ctrl; u32 sdrc_mr_0_ddr; u32 sdrc_mr_0_sdr; - u32 sdrc_dlla_ctrl; - u32 sdrc_dllb_ctrl; + u32 sdrc_dllab_ctrl; } /*__attribute__ ((packed))*/; typedef struct sdrc_data_s sdrc_data_t; @@ -49,129 +48,109 @@ typedef enum { STACKED = 0, IP_DDR = 1, COMBO_DDR = 2, - IP_SDR = 3, + IP_SDR = 3, } mem_t; #endif /* Slower full frequency range default timings for x32 operation*/ -#define H4_2420_SDRC_SHARING 0x00000100 +#define H4_2420_SDRC_SHARING 0x00000100 #define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ #define H4_2420_SDRC_MR_0_SDR 0x00000031 #define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ #define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ #define H4_2420_SDRC_MR_0_DDR 0x00000032 -#ifndef CONFIG_OPTIMIZE_DDR -# define H4_2420_SDRC_ACTIM_CTRLA_0 0x9bead909 -# define H4_2420_SDRC_ACTIM_CTRLB_0 0x00000014 -# define H4_2420_SDRC_RFR_CTRL_ES1 0x00002401 -# define H4_2420_SDRC_RFR_CTRL 0x0002da01 -#endif -#define H4_2420_SDRC_DLLA_CTRL 0x00007307 /* load value at 100Mhz */ -#define H4_2420_SDRC_DLLB_CTRL 0x00007307 - #define H4_2422_SDRC_SHARING 0x00004b00 #define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */ -#ifndef CONFIG_OPTIMIZE_DDR -# define H4_2422_SDRC_ACTIM_CTRLA_0 0x9BEAD909 -# define H4_2422_SDRC_ACTIM_CTRLB_0 0x00000020 -# define H4_2422_SDRC_RFR_CTRL_ES1 0x00002401 -# define H4_2422_SDRC_RFR_CTRL 0x0002da01 -#endif #define H4_2422_SDRC_MR_0_DDR 0x00000032 -#define H4_2422_SDRC_DLLA_CTRL 0x00007307 -#define H4_2422_SDRC_DLLB_CTRL 0x00007307 -/* optimized timings */ +/* ES1 work around timings */ +#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ +#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 +#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ + +/* optimized timings good for current shipping parts */ #define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 #define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e -#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settigs */ -#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ -#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 /* this is not optimal yet */ -#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 - -#ifdef CONFIG_OPTIMIZE_DDR -# ifdef PRCM_CONFIG_II -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# elif PRCM_CONFIG_III -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz -# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_133MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz -# endif -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_2420_SDRC_ACTIM_CTRLA_0 -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_2420_SDRC_ACTIM_CTRLB_0 -# define H4_2422_SDRC_RFR_CTRL_ES1 H4_2420_SDRC_RFR_CTRL_ES1 -# define H4_2422_SDRC_RFR_CTRL H4_2420_SDRC_RFR_CTRL +#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ +#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ +#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 +#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/ +#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */ + +#ifdef PRCM_CONFIG_II +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +#elif PRCM_CONFIG_III +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz #endif /* GPMC settings */ -#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ -#ifdef CFG_NAND_BOOT -#define H4_24XX_GPMC_CONFIG1_0 0x0 -#define H4_24XX_GPMC_CONFIG2_0 0x00141400 -#define H4_24XX_GPMC_CONFIG3_0 0x00141400 -#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -#define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -#define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -#else -#define H4_24XX_GPMC_CONFIG1_0 0x3 -#define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 -#define H4_24XX_GPMC_CONFIG3_0 0x00050502 -#define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 -#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -#endif -#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) - -#define H4_24XX_GPMC_CONFIG1_1 0x00011000 -#define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 -#define H4_24XX_GPMC_CONFIG3_1 0x00080802 -#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -#define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F -#define H4_24XX_GPMC_CONFIG6_1 0x000003C2 -#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif - -#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ -#ifdef CFG_NAND_BOOT -#define H4_24XX_GPMC_CONFIG1_0 0x0 -#define H4_24XX_GPMC_CONFIG2_0 0x00141400 -#define H4_24XX_GPMC_CONFIG3_0 0x00141400 -#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -#define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -#define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -#else -#define H4_24XX_GPMC_CONFIG1_0 0x3 -#define H4_24XX_GPMC_CONFIG2_0 0x00151501 -#define H4_24XX_GPMC_CONFIG3_0 0x00060602 -#define H4_24XX_GPMC_CONFIG4_0 0x10081008 -#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -#define H4_24XX_GPMC_CONFIG6_0 0x000004c4 -#endif -#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) - -#define H4_24XX_GPMC_CONFIG1_1 0x00011000 -#define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 -#define H4_24XX_GPMC_CONFIG3_1 0x00080803 -#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -#define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F -#define H4_24XX_GPMC_CONFIG6_1 0x000004C4 -#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif - -#ifdef CONFIG_APTIX /* SDRC-SDR for Aptix x16 */ -#define VAL_H4_SDRC_SHARING_16 0x00002400 /* No-Tristate, 16bit on D31-D16, CS1=dont care */ -#define VAL_H4_SDRC_SHARING 0x00000100 -#define VAL_H4_SDRC_MCFG_0_16 0x00901000 /* SDR-SDRAM,External,x16 bit */ -#define VAL_H4_SDRC_MCFG_0 0x01702011 -#define VAL_H4_SDRC_MR_0 0x00000029 /* Burst=2, Serial Mode, CAS 3*/ -#define VAL_H4_SDRC_RFR_CTRL_0 0x00001703 /* refresh time */ -#define VAL_H4_SDRC_DCDL2_CTRL 0x5A59B485 -#endif - -#endif +#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ +# ifdef CFG_NAND_BOOT +# define H4_24XX_GPMC_CONFIG1_0 0x0 +# define H4_24XX_GPMC_CONFIG2_0 0x00141400 +# define H4_24XX_GPMC_CONFIG3_0 0x00141400 +# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 +# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 +# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 +# else /* else NOR */ +# define H4_24XX_GPMC_CONFIG1_0 0x3 +# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 +# define H4_24XX_GPMC_CONFIG3_0 0x00050502 +# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 +# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F +# endif /* endif CFG_NAND_BOOT */ +# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) +# define H4_24XX_GPMC_CONFIG1_1 0x00011000 +# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 +# define H4_24XX_GPMC_CONFIG3_1 0x00080802 +# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F +# define H4_24XX_GPMC_CONFIG6_1 0x000003C2 +# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) +#endif /* endif PRCM_CONFIG_II */ + +#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ +# ifdef CFG_NAND_BOOT +# define H4_24XX_GPMC_CONFIG1_0 0x0 +# define H4_24XX_GPMC_CONFIG2_0 0x00141400 +# define H4_24XX_GPMC_CONFIG3_0 0x00141400 +# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 +# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 +# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 +# else /* NOR boot */ +# define H4_24XX_GPMC_CONFIG1_0 0x3 +# define H4_24XX_GPMC_CONFIG2_0 0x00151501 +# define H4_24XX_GPMC_CONFIG3_0 0x00060602 +# define H4_24XX_GPMC_CONFIG4_0 0x10081008 +# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F +# define H4_24XX_GPMC_CONFIG6_0 0x000004c4 +# endif /* endif CFG_NAND_BOOT */ +# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) +# define H4_24XX_GPMC_CONFIG1_1 0x00011000 +# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 +# define H4_24XX_GPMC_CONFIG3_1 0x00080803 +# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F +# define H4_24XX_GPMC_CONFIG6_1 0x000004C4 +# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) +#endif /* endif CFG_PRCM_III */ + +#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h index a2a97981b6..d833035a4b 100644 --- a/include/asm-arm/arch-arm1136/omap2420.h +++ b/include/asm-arm/arch-arm1136/omap2420.h @@ -31,13 +31,31 @@ * 2420 specific Section */ +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 +/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */ + +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 + /* CONTROL */ #define OMAP2420_CTRL_BASE (0x48000000) #define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) +/* device type */ +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + /* TAP information */ #define OMAP2420_TAP_BASE (0x48014000) #define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) /* GPMC */ #define OMAP2420_GPMC_BASE (0x6800A000) @@ -70,6 +88,7 @@ #define OMAP2420_SDRC_BASE 0x68009000 #define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) #define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) #define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) #define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) #define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) diff --git a/include/asm-arm/arch-arm1136/rev.h b/include/asm-arm/arch-arm1136/rev.h deleted file mode 100644 index 6fceb092d5..0000000000 --- a/include/asm-arm/arch-arm1136/rev.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_REV_H_ -#define _OMAP24XX_REV_H_ - -typedef struct h4_system_data { - /* base board info */ - u32 base_b_rev; /* rev from base board i2c */ - /* cpu board info */ - u32 cpu_b_rev; /* rev from cpu board i2c */ - u32 cpu_b_mux; /* mux type on daughter board */ - u32 cpu_b_ddr_type; /* mem type */ - u32 cpu_b_ddr_speed; /* ddr speed rating */ - u32 cpu_b_switches; /* boot ctrl switch settings */ - /* cpu info */ - u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ - u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ -} h4_sys_data; - -#define CDB_DDR_COMBO /* combo part on cpu daughter card */ -#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_2420 0x2420 -#define CPU_2422 0x2422 - -#define CPU_2422_ES1 1 -#define CPU_2422_ES2 2 -#define CPU_2420_ES1 1 -#define CPU_2420_ES2 2 - -#endif diff --git a/include/asm-arm/arch-arm1136/sys_info.h b/include/asm-arm/arch-arm1136/sys_info.h index ef301ba61a..53c231a5e4 100644 --- a/include/asm-arm/arch-arm1136/sys_info.h +++ b/include/asm-arm/arch-arm1136/sys_info.h @@ -39,7 +39,8 @@ typedef struct h4_system_data { u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ } h4_sys_data; -#define SDR_DISCRETE 4 +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ #define DDR_STACKED 3 /* stacked part on 2422 */ #define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ #define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ @@ -50,16 +51,19 @@ typedef struct h4_system_data { #define DDR_165 165 /* future parts */ #define CPU_2420 0x2420 -#define CPU_2422 0x2422 +#define CPU_2422 0x2422 /* 2420 + 64M stacked */ +#define CPU_2423 0x2423 /* 2420 + 96M stacked */ #define CPU_2422_ES1 1 #define CPU_2422_ES2 2 #define CPU_2420_ES1 1 #define CPU_2420_ES2 2 +#define CPU_2420_2422_ES1 1 #define CPU_2420_CHIPID 0x0B5D9000 #define CPU_24XX_ID_MASK 0x0FFFF000 #define CPU_242X_REV_MASK 0xF0000000 +#define CPU_242X_PID_MASK 0x000F0000 #define BOARD_H4_MENELAUS 1 #define BOARD_H4_SDP 2 diff --git a/include/asm-arm/arch-arm1136/sys_proto.h b/include/asm-arm/arch-arm1136/sys_proto.h index 2cd8455dec..9d8e5b2622 100644 --- a/include/asm-arm/arch-arm1136/sys_proto.h +++ b/include/asm-arm/arch-arm1136/sys_proto.h @@ -44,10 +44,11 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); u32 get_board_type(void); void display_board_info(u32); void update_mux(u32,u32); +u32 get_sdr_cs_size(u32 offset); u32 running_in_sdram(void); u32 running_in_sram(void); u32 running_in_flash(void); u32 running_from_internal_boot(void); - +u32 get_device_type(void); #endif diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h index 5064697858..3056ca7f67 100644 --- a/include/asm-arm/arch-arm720t/hardware.h +++ b/include/asm-arm/arch-arm720t/hardware.h @@ -32,6 +32,10 @@ /* include IMPA7 specific hardware file if there was one */ #elif defined(CONFIG_EP7312) /* include EP7312 specific hardware file if there was one */ +#elif defined(CONFIG_ARMADILLO) +/* include armadillo specific hardware file if there was one */ +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +/* include IntegratorCP/CM720T specific hardware file if there was one */ #else #error No hardware file defined for this configuration #endif diff --git a/include/asm-arm/arch-arm720t/netarm_gen_module.h b/include/asm-arm/arch-arm720t/netarm_gen_module.h index 90d9da8174..13656a3ad2 100644 --- a/include/asm-arm/arch-arm720t/netarm_gen_module.h +++ b/include/asm-arm/arch-arm720t/netarm_gen_module.h @@ -1,6 +1,9 @@ /* * include/asm-armnommu/arch-netarm/netarm_gen_module.h * + * Copyright (C) 2005 + * Art Shipkowski, Videon Central, Inc., <art@videon-central.com> + * * Copyright (C) 2000, 2001 NETsilicon, Inc. * Copyright (C) 2000, 2001 Red Hat, Inc. * @@ -27,6 +30,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * author(s) : Joe deBlaquiere + * + * Modified to support NS7520 by Art Shipkowski. */ #ifndef __NETARM_GEN_MODULE_REGISTERS_H @@ -49,7 +54,9 @@ #define NETARM_GEN_TIMER2_STATUS (0x1c) #define NETARM_GEN_PORTA (0x20) +#ifndef CONFIG_NETARM_NS7520 #define NETARM_GEN_PORTB (0x24) +#endif #define NETARM_GEN_PORTC (0x28) #define NETARM_GEN_INTR_ENABLE (0x30) @@ -128,8 +135,14 @@ /* PORT C Register ( 0xFFB0_0028 ) */ +#ifndef CONFIG_NETARM_NS7520 #define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) #define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) +#else +#define NETARM_GEN_PORT_MODE(x) ((x)<<24) +#define NETARM_GEN_PORT_DIR(x) ((x)<<16) +#define NETARM_GEN_PORT_CSF(x) ((x)<<8) +#endif /* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ @@ -143,10 +156,15 @@ #define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) #define NETARM_GEN_TSTAT_INTPEN (0x40000000) +#if ~defined(CONFIG_NETARM_NS7520) #define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) +#else +#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF) +#endif /* prescale to msecs conversion */ +#if !defined(CONFIG_NETARM_PLL_BYPASS) #define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ NETARM_GEN_TSTAT_CTC_MASK ) + \ 1 ) ) / (NETARM_XTAL_FREQ/1000) ) @@ -155,9 +173,7 @@ NETARM_GEN_TSTAT_CTC_MASK ) | \ NETARM_GEN_TCTL_USE_PRESCALE ) -#if 0 -/* ifdef CONFIG_NETARM_PLL_BYPASS else */ -#error test +#else #define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ NETARM_GEN_TSTAT_CTC_MASK ) + \ 1 ) ) / (NETARM_XTAL_FREQ/1000) ) diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h index 7c63d176a9..f0529fd09b 100644 --- a/include/asm-arm/arch-arm720t/netarm_mem_module.h +++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h @@ -1,6 +1,9 @@ /* * include/asm-armnommu/arch-netarm/netarm_mem_module.h * + * Copyright (C) 2005 + * Art Shipkowski, Videon Central, Inc., <art@videon-central.com> + * * Copyright (C) 2000, 2001 NETsilicon, Inc. * Copyright (C) 2000, 2001 Red Hat, Inc. * @@ -27,6 +30,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * author(s) : Joe deBlaquiere + * + * Modified to support NS7520 by Art Shipkowski. */ #ifndef __NETARM_MEM_MODULE_REGISTERS_H @@ -154,4 +159,26 @@ #define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000) #define NETARM_MEM_OPT_WRITE_SYNC (0x00000001) +#ifdef CONFIG_NETARM_NS7520 +/* The NS7520 has a second options register for each chip select */ +#define NETARM_MEM_CS0_OPTIONS_B (0x18) +#define NETARM_MEM_CS1_OPTIONS_B (0x28) +#define NETARM_MEM_CS2_OPTIONS_B (0x38) +#define NETARM_MEM_CS3_OPTIONS_B (0x48) +#define NETARM_MEM_CS4_OPTIONS_B (0x58) + +/* Option B Registers (0xFFC0_00x8) */ +#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) +#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) +#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) +#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) +#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) + +#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) +#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) +#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) +#endif + #endif diff --git a/include/asm-arm/arch-arm720t/netarm_registers.h b/include/asm-arm/arch-arm720t/netarm_registers.h index 029c7f4c74..fa8812879a 100644 --- a/include/asm-arm/arch-arm720t/netarm_registers.h +++ b/include/asm-arm/arch-arm720t/netarm_registers.h @@ -1,6 +1,9 @@ /* * linux/include/asm-arm/arch-netarm/netarm_registers.h * + * Copyright (C) 2005 + * Art Shipkowski, Videon Central, Inc., <art@videon-central.com> + * * Copyright (C) 2000, 2001 NETsilicon, Inc. * Copyright (C) 2000, 2001 WireSpeed Communications Corporation * @@ -27,6 +30,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * author(s) : Joe deBlaquiere + * + * Modified to support NS7520 by Art Shipkowski. */ #ifndef __NET_ARM_REGISTERS_H @@ -38,6 +43,8 @@ /* the input crystal/clock frequency ( in Hz ) */ #define NETARM_XTAL_FREQ_25MHz (18432000) #define NETARM_XTAL_FREQ_33MHz (23698000) +#define NETARM_XTAL_FREQ_48MHz (48000000) +#define NETARM_XTAL_FREQ_55MHz (55000000) #define NETARM_XTAL_FREQ_EMLIN1 (20000000) /* the frequency of SYS_CLK */ @@ -60,12 +67,22 @@ #define NETARM_PLL_COUNT_VAL 4 #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz -#else /* CONFIG_NETARM_NET50 */ +#elif defined(CONFIG_NETARM_NET50) /* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ #define NETARM_PLL_COUNT_VAL 8 #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz +#else /* CONFIG_NETARM_NS7520 */ + +#define NETARM_PLL_COUNT_VAL 0 + +#if defined(CONFIG_BOARD_UNC20) +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz +#else +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz +#endif + #endif /* #include "arm_registers.h" */ diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index f7e6d555df..97d470484c 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -25,12 +25,13 @@ #ifndef AT91RM9200_H #define AT91RM9200_H -typedef volatile unsigned int AT91_REG;/* Hardware register definition */ +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ -/* ***************************************************************************** */ -/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ -/* ***************************************************************************** */ -typedef struct _AT91S_TC { +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/******************************************************************************/ +typedef struct _AT91S_TC +{ AT91_REG TC_CCR; /* Channel Control Register */ AT91_REG TC_CMR; /* Channel Mode Register */ AT91_REG Reserved0[2]; /* */ @@ -44,25 +45,26 @@ typedef struct _AT91S_TC { AT91_REG TC_IMR; /* Interrupt Mask Register */ } AT91S_TC, *AT91PS_TC; -#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ -#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ -#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ -#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ -#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */ -#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ -#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ -#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ - -/* ***************************************************************************** */ -/* SOFTWARE API DEFINITION FOR Usart */ -/* ***************************************************************************** */ -typedef struct _AT91S_USART { +#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ +#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ +#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ +#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ +#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */ +#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ +#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ +#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Usart */ +/******************************************************************************/ +typedef struct _AT91S_USART +{ AT91_REG US_CR; /* Control Register */ AT91_REG US_MR; /* Mode Register */ AT91_REG US_IER; /* Interrupt Enable Register */ @@ -79,7 +81,7 @@ typedef struct _AT91S_USART { AT91_REG US_NER; /* Nb Errors Register */ AT91_REG US_XXR; /* XON_XOFF Register */ AT91_REG US_IF; /* IRDA_FILTER Register */ - AT91_REG Reserved1[44]; /* */ + AT91_REG Reserved1[44]; /* */ AT91_REG US_RPR; /* Receive Pointer Register */ AT91_REG US_RCR; /* Receive Counter Register */ AT91_REG US_TPR; /* Transmit Pointer Register */ @@ -92,10 +94,11 @@ typedef struct _AT91S_USART { AT91_REG US_PTSR; /* PDC Transfer Status Register */ } AT91S_USART, *AT91PS_USART; -/************************************************************************/ -/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ -/************************************************************************/ -typedef struct _AT91S_CKGR { +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ +/******************************************************************************/ +typedef struct _AT91S_CKGR +{ AT91_REG CKGR_MOR; /* Main Oscillator Register */ AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ AT91_REG CKGR_PLLAR; /* PLL A Register */ @@ -103,42 +106,46 @@ typedef struct _AT91S_CKGR { } AT91S_CKGR, *AT91PS_CKGR; /* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */ -#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */ -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */ +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */ +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */ + /* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */ -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */ +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */ + /* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */ -#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ -#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ -#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ -#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */ -#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ -#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */ -#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */ +#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */ +#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ +#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */ +#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */ + /* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */ -#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ -#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ -#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ -#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */ -#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ -#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */ -#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ -#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ - -/* ************************************************************************* */ -/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ -/* ************************************************************************* */ -typedef struct _AT91S_PIO { +#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */ +#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ +#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */ +#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ +#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ +/******************************************************************************/ +typedef struct _AT91S_PIO +{ AT91_REG PIO_PER; /* PIO Enable Register */ AT91_REG PIO_PDR; /* PIO Disable Register */ AT91_REG PIO_PSR; /* PIO Status Register */ @@ -177,10 +184,11 @@ typedef struct _AT91S_PIO { } AT91S_PIO, *AT91PS_PIO; -/* ***************************************************************************** */ -/* SOFTWARE API DEFINITION FOR Debug Unit */ -/* ***************************************************************************** */ -typedef struct _AT91S_DBGU { +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/******************************************************************************/ +typedef struct _AT91S_DBGU +{ AT91_REG DBGU_CR; /* Control Register */ AT91_REG DBGU_MR; /* Mode Register */ AT91_REG DBGU_IER; /* Interrupt Enable Register */ @@ -208,60 +216,62 @@ typedef struct _AT91S_DBGU { } AT91S_DBGU, *AT91PS_DBGU; /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */ -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */ -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */ -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */ -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */ -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */ -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */ -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */ -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */ -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */ -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */ -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */ +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */ /* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */ -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */ -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */ -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */ -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */ -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */ - -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */ -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */ -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ - -/* ***************************************************************************** */ -/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ -/* ***************************************************************************** */ -typedef struct _AT91S_SMC2 { +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */ + +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */ +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */ +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ +/******************************************************************************/ +typedef struct _AT91S_SMC2 +{ AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ } AT91S_SMC2, *AT91PS_SMC2; /* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ -#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ -#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ -#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ -#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ -#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ -#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ -#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */ -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ -#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */ -#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ -#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ -#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ -#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ - -/* ***************************************************************************** */ -/* SOFTWARE API DEFINITION FOR Power Management Controler */ -/* ******************************************************************************/ -typedef struct _AT91S_PMC { +#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ +#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ +#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ +#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ +#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ +#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ +#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ +#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */ +#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ +#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */ +#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ +#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ +#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ +#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Power Management Controler */ +/******************************************************************************/ +typedef struct _AT91S_PMC +{ AT91_REG PMC_SCER; /* System Clock Enable Register */ AT91_REG PMC_SCDR; /* System Clock Disable Register */ AT91_REG PMC_SCSR; /* System Clock Status Register */ @@ -279,63 +289,63 @@ typedef struct _AT91S_PMC { AT91_REG PMC_IMR; /* Interrupt Mask Register */ } AT91S_PMC, *AT91PS_PMC; - /*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */ -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */ -#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */ -#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */ -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */ +#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */ +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */ /*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/ /*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/ /*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/ -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */ -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */ -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */ -#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */ -#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */ -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */ -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */ -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */ -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */ -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */ -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */ -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */ -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */ -#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */ -#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */ -#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */ -#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */ -#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */ +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */ +#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */ +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */ +#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */ +#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */ +#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */ +#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */ +#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */ /*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/ /*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/ -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */ -#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */ -#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */ -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */ /*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/ /*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ /*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ -/* ***************************************************************************** */ -/* SOFTWARE API DEFINITION FOR Ethernet MAC */ -/* ***************************************************************************** */ -typedef struct _AT91S_EMAC { +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Ethernet MAC */ +/******************************************************************************/ +typedef struct _AT91S_EMAC +{ AT91_REG EMAC_CTL; /* Network Control Register */ AT91_REG EMAC_CFG; /* Network Configuration Register */ AT91_REG EMAC_SR; /* Network Status Register */ @@ -382,82 +392,90 @@ typedef struct _AT91S_EMAC { } AT91S_EMAC, *AT91PS_EMAC; /* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ -#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */ -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */ -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */ -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */ -#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */ -#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */ -#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */ -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */ + /* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */ -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ -#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */ -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */ -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */ -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */ -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */ -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */ -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */ -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */ -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */ -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */ -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */ -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */ +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */ +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */ +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */ +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */ + /* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */ -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ + /* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */ -#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ -#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ +#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ +#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ + /* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */ -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ -#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */ -#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */ -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */ -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */ +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ +#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */ +#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */ +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */ +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */ + /* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */ +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ + /* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ -#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ -#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */ -#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */ -#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */ -#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */ -#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */ -#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */ -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */ -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ +#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ +#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ +#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */ +#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */ +#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */ +#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */ +#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */ +#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */ +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */ +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ + /* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ /* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ /* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */ -#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */ -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */ -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */ -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */ -#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */ -#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */ -#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ -#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ - -/* ***************************************************************************** */ -/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ -/* ***************************************************************************** */ -typedef struct _AT91S_SPI { +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */ +#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */ +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */ +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */ +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */ +#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */ +#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */ +#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ +#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/******************************************************************************/ +typedef struct _AT91S_SPI +{ AT91_REG SPI_CR; /* Control Register */ AT91_REG SPI_MR; /* Mode Register */ AT91_REG SPI_RDR; /* Receive Data Register */ @@ -482,60 +500,66 @@ typedef struct _AT91S_SPI { } AT91S_SPI, *AT91PS_SPI; /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */ -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */ -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */ +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */ + /* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */ -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */ -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */ -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */ -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */ -#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */ -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */ -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */ -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */ -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */ +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */ + /* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */ -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ + /* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */ -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ + /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */ -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */ -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */ -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */ -#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */ -#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */ -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */ -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */ -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ + /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ /* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ /* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */ -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */ -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */ -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */ -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */ -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */ -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */ -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */ -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */ -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */ -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */ -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */ -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ - -/* ***************************************************************************** */ -/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ -/* ***************************************************************************** */ -typedef struct _AT91S_PDC { +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */ +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/******************************************************************************/ +typedef struct _AT91S_PDC +{ AT91_REG PDC_RPR; /* Receive Pointer Register */ AT91_REG PDC_RCR; /* Receive Counter Register */ AT91_REG PDC_TPR; /* Transmit Pointer Register */ @@ -549,187 +573,190 @@ typedef struct _AT91S_PDC { } AT91S_PDC, *AT91PS_PDC; /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */ -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */ -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */ -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */ +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */ /* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ /* ========== Register definition ==================================== */ -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */ -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */ -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */ -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */ -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */ -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */ -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */ -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */ -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */ -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */ -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */ -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */ -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */ -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */ -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */ -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */ -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */ -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */ -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */ -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */ -#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */ -#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */ -#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */ -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */ -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */ -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */ -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */ -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */ -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ - -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ -#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ -#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */ -#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */ -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */ +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */ +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */ +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */ +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */ +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */ +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */ +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */ +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */ +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */ +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */ +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */ +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */ +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */ +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */ +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */ +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */ +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */ +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */ +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */ +#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */ +#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */ +#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */ +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */ +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */ +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */ +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */ +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */ +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */ +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ + +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ +#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ +#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */ +#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */ +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */ #define AT91C_PA25_TWD ((unsigned int) 1 << 25) #define AT91C_PA26_TWCK ((unsigned int) 1 << 26) -#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */ -#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */ -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */ -#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */ -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */ -#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */ -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ -#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ - -#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ -#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ -#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ -#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ -#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ -#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ -#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ -#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */ -#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */ -#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */ - -#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */ -#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */ -#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */ -#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ -#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */ -#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */ -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */ - -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ -#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */ - -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */ -#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */ -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */ -#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */ -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */ -#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */ -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */ -#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */ -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */ -#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */ -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */ -#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */ -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ -#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */ - - -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ -#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ -#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */ -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */ -#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */ -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */ -#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */ -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */ -#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */ -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */ -#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ -#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ -#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */ -#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */ -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ -#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ - -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ -#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ -#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */ -#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */ -#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */ -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */ -#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */ -#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */ -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */ -#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */ -#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */ -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */ -#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */ -#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */ -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */ -#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */ -#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */ -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */ -#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */ -#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */ -#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */ -#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */ -#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ -#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ - -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ - -#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ -#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ -#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ -#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ -#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ - -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ -#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ -#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ -#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ -#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ -#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ -#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ -#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ +#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */ +#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */ +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */ +#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */ +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */ +#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */ +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ +#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ + +#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ +#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ +#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ +#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ +#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ +#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ +#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ +#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */ +#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */ +#define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */ +#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */ + +#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */ +#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */ +#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */ +#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ +#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */ +#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */ +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */ + +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */ + +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */ +#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */ +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */ +#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */ +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */ +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */ +#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */ +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */ +#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */ +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */ +#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ +#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */ + +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ +#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ +#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */ +#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */ +#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */ +#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */ +#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ +#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ +#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */ +#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ +#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ + +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ +#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ +#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */ +#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */ +#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */ +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */ +#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */ +#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */ +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */ +#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */ +#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */ +#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */ +#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */ +#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */ +#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */ +#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */ +#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */ +#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */ +#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */ +#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ +#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ + +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ + +#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ +#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ +#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ +#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ +#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ +#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ +#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ + +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ +#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ +#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ +#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ +#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ +#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ +#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ +#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ +#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ #endif diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h index 19d799d539..8bb0c47523 100644 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ b/include/asm-arm/arch-at91rm9200/hardware.h @@ -47,6 +47,8 @@ #define AT91_TCB1_BASE 0xFFFA4000 /*16K */ #define AT91_TCB0_BASE 0xFFFA0000 /*16K */ +#define AT91_USB_HOST_BASE 0x00300000 + /* * Where in virtual memory the IO devices (timers, system controllers * and so on) diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index e482115920..fd03748523 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1,5 +1,5 @@ /* - * This was automagically generated from mach-types! + * This was automagically generated from arch/arm/tools/mach-types! * Do NOT edit */ @@ -230,7 +230,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_PNP1110 215 #define MACH_TYPE_CSB226 216 #define MACH_TYPE_ARNOLD 217 -#define MACH_TYPE_PSIBOARD 218 +#define MACH_TYPE_VOICEBLUE 218 #define MACH_TYPE_JZ8028 219 #define MACH_TYPE_H5400 220 #define MACH_TYPE_FORTE 221 @@ -254,8 +254,8 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_PDB 239 #define MACH_TYPE_BLUE_2G 240 #define MACH_TYPE_BLUEARCH 241 -#define MACH_TYPE_IXDB2400 242 -#define MACH_TYPE_IXDB2800 243 +#define MACH_TYPE_IXDP2400 242 +#define MACH_TYPE_IXDP2800 243 #define MACH_TYPE_EXPLORER 244 #define MACH_TYPE_IXDP425 245 #define MACH_TYPE_CHIMP 246 @@ -598,8 +598,8 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_XAENIAX 585 #define MACH_TYPE_SOMN4250 586 #define MACH_TYPE_PLEB2 587 -#define MACH_TYPE_CWL 588 -#define MACH_TYPE_GD 589 +#define MACH_TYPE_CORNWALLIS 588 +#define MACH_TYPE_GURNEY_DRV 589 #define MACH_TYPE_CHAFFEE 590 #define MACH_TYPE_RMS101 591 #define MACH_TYPE_RX3715 592 @@ -624,6 +624,118 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_RMS100 611 #define MACH_TYPE_KB9200 612 #define MACH_TYPE_SX1 613 +#define MACH_TYPE_HMS39C7092 614 +#define MACH_TYPE_ARMADILLO 615 +#define MACH_TYPE_IPCU 616 +#define MACH_TYPE_LOOX720 617 +#define MACH_TYPE_IXDP465 618 +#define MACH_TYPE_IXDP2351 619 +#define MACH_TYPE_ADSVIX 620 +#define MACH_TYPE_DM270 621 +#define MACH_TYPE_SOCLTPLUS 622 +#define MACH_TYPE_ECIA 623 +#define MACH_TYPE_CM4008 624 +#define MACH_TYPE_P2001 625 +#define MACH_TYPE_TWISTER 626 +#define MACH_TYPE_MUDSHARK 627 +#define MACH_TYPE_HB2 628 +#define MACH_TYPE_IQ80332 629 +#define MACH_TYPE_SENDT 630 +#define MACH_TYPE_MX2JAZZ 631 +#define MACH_TYPE_MULTIIO 632 +#define MACH_TYPE_HRDISPLAY 633 +#define MACH_TYPE_SCMA11BB 634 +#define MACH_TYPE_TRIZEPS3 635 +#define MACH_TYPE_ZEFEERDZA 636 +#define MACH_TYPE_ZEFEERDZB 637 +#define MACH_TYPE_ZEFEERDZG 638 +#define MACH_TYPE_ZEFEERDZN 639 +#define MACH_TYPE_ZEFEERDZQ 640 +#define MACH_TYPE_GTWX5715 641 +#define MACH_TYPE_ASTRO_JACK 643 +#define MACH_TYPE_TIP03 644 +#define MACH_TYPE_A9200EC 645 +#define MACH_TYPE_PNX0105 646 +#define MACH_TYPE_ADCPOECPU 647 +#define MACH_TYPE_CSB637 648 +#define MACH_TYPE_ML69Q6203 649 +#define MACH_TYPE_MB9200 650 +#define MACH_TYPE_KULUN 651 +#define MACH_TYPE_SNAPPER 652 +#define MACH_TYPE_OPTIMA 653 +#define MACH_TYPE_DLHSBC 654 +#define MACH_TYPE_X30 655 +#define MACH_TYPE_N30 656 +#define MACH_TYPE_MANGA_KS8695 657 +#define MACH_TYPE_AJAX 658 +#define MACH_TYPE_NEC_MP900 659 +#define MACH_TYPE_VVTK1000 661 +#define MACH_TYPE_KAFA 662 +#define MACH_TYPE_VVTK3000 663 +#define MACH_TYPE_PIMX1 664 +#define MACH_TYPE_OLLIE 665 +#define MACH_TYPE_SKYMAX 666 +#define MACH_TYPE_JAZZ 667 +#define MACH_TYPE_TEL_T3 668 +#define MACH_TYPE_AISINO_FCR255 669 +#define MACH_TYPE_BTWEB 670 +#define MACH_TYPE_DBG_LH79520 671 +#define MACH_TYPE_CM41XX 672 +#define MACH_TYPE_TS72XX 673 +#define MACH_TYPE_NGGPXA 674 +#define MACH_TYPE_CSB535 675 +#define MACH_TYPE_CSB536 676 +#define MACH_TYPE_PXA_TRAKPOD 677 +#define MACH_TYPE_PRAXIS 678 +#define MACH_TYPE_LH75411 679 +#define MACH_TYPE_OTOM 680 +#define MACH_TYPE_NEXCODER_2440 681 +#define MACH_TYPE_LOOX410 682 +#define MACH_TYPE_WESTLAKE 683 +#define MACH_TYPE_NSB 684 +#define MACH_TYPE_ESL_SARVA_STN 685 +#define MACH_TYPE_ESL_SARVA_TFT 686 +#define MACH_TYPE_ESL_SARVA_IAD 687 +#define MACH_TYPE_ESL_SARVA_ACC 688 +#define MACH_TYPE_TYPHOON 689 +#define MACH_TYPE_CNAV 690 +#define MACH_TYPE_A730 691 +#define MACH_TYPE_NETSTAR 692 +#define MACH_TYPE_PHASEFALE_SUPERCON 693 +#define MACH_TYPE_SHIVA1100 694 +#define MACH_TYPE_ETEXSC 695 +#define MACH_TYPE_IXDPG465 696 +#define MACH_TYPE_A9M2410 697 +#define MACH_TYPE_A9M2440 698 +#define MACH_TYPE_A9M9750 699 +#define MACH_TYPE_A9M9360 700 +#define MACH_TYPE_UNC90 701 +#define MACH_TYPE_ECO920 702 +#define MACH_TYPE_SATVIEW 703 +#define MACH_TYPE_ROADRUNNER 704 +#define MACH_TYPE_AT91RM9200EK 705 +#define MACH_TYPE_GP32 706 +#define MACH_TYPE_GEM 707 +#define MACH_TYPE_I858 708 +#define MACH_TYPE_HX2750 709 +#define MACH_TYPE_ZEUSEVB 710 +#define MACH_TYPE_P700 711 +#define MACH_TYPE_CPE 712 +#define MACH_TYPE_SPITZ 713 +#define MACH_TYPE_NIMBRA340 714 +#define MACH_TYPE_LPC22XX 715 +#define MACH_TYPE_COMET3 716 +#define MACH_TYPE_COMET4 717 +#define MACH_TYPE_CSB625 718 +#define MACH_TYPE_FORTUNET2 719 +#define MACH_TYPE_S5H2200 720 +#define MACH_TYPE_OPTORM920 721 +#define MACH_TYPE_ADSBITSYXB 722 +#define MACH_TYPE_ADSSPHERE 723 +#define MACH_TYPE_ADSPORTAL 724 +#define MACH_TYPE_LN2410SBC 725 +#define MACH_TYPE_CB3RUFC 726 +#define MACH_TYPE_MP2USB 727 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -3217,16 +3329,16 @@ extern unsigned int __machine_arch_type; # define machine_is_arnold() (0) #endif -#ifdef CONFIG_SA1100_PSIBOARD +#ifdef CONFIG_MACH_VOICEBLUE # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_PSIBOARD +# define machine_arch_type MACH_TYPE_VOICEBLUE # endif -# define machine_is_psiboard() (machine_arch_type == MACH_TYPE_PSIBOARD) +# define machine_is_voiceblue() (machine_arch_type == MACH_TYPE_VOICEBLUE) #else -# define machine_is_psiboard() (0) +# define machine_is_voiceblue() (0) #endif #ifdef CONFIG_ARCH_JZ8028 @@ -3505,26 +3617,26 @@ extern unsigned int __machine_arch_type; # define machine_is_bluearch() (0) #endif -#ifdef CONFIG_ARCH_IXDB2400 +#ifdef CONFIG_ARCH_IXDP2400 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_IXDB2400 +# define machine_arch_type MACH_TYPE_IXDP2400 # endif -# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDB2400) +# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDP2400) #else # define machine_is_ixdp2400() (0) #endif -#ifdef CONFIG_ARCH_IXDB2800 +#ifdef CONFIG_ARCH_IXDP2800 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_IXDB2800 +# define machine_arch_type MACH_TYPE_IXDP2800 # endif -# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDB2800) +# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDP2800) #else # define machine_is_ixdp2800() (0) #endif @@ -5072,9 +5184,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_GUMSTIK # endif -# define machine_is_gumstik() (machine_arch_type == MACH_TYPE_GUMSTIK) +# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIK) #else -# define machine_is_gumstik() (0) +# define machine_is_gumstix() (0) #endif #ifdef CONFIG_ARCH_RCUBE @@ -7633,28 +7745,28 @@ extern unsigned int __machine_arch_type; # define machine_is_pleb2() (0) #endif -#ifdef CONFIG_MACH_CWL +#ifdef CONFIG_MACH_CORNWALLIS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_CWL +# define machine_arch_type MACH_TYPE_CORNWALLIS # endif -# define machine_is_cwl() (machine_arch_type == MACH_TYPE_CWL) +# define machine_is_cornwallis() (machine_arch_type == MACH_TYPE_CORNWALLIS) #else -# define machine_is_cwl() (0) +# define machine_is_cornwallis() (0) #endif -#ifdef CONFIG_MACH_GD +#ifdef CONFIG_MACH_GURNEY_DRV # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_GD +# define machine_arch_type MACH_TYPE_GURNEY_DRV # endif -# define machine_is_gd() (machine_arch_type == MACH_TYPE_GD) +# define machine_is_gurney_drv() (machine_arch_type == MACH_TYPE_GURNEY_DRV) #else -# define machine_is_gd() (0) +# define machine_is_gurney_drv() (0) #endif #ifdef CONFIG_MACH_CHAFFEE @@ -7945,6 +8057,1350 @@ extern unsigned int __machine_arch_type; # define machine_is_sx1() (0) #endif +#ifdef CONFIG_MACH_HMS39C7092 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMS39C7092 +# endif +# define machine_is_hms39c7092() (machine_arch_type == MACH_TYPE_HMS39C7092) +#else +# define machine_is_hms39c7092() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO +# endif +# define machine_is_armadillo() (machine_arch_type == MACH_TYPE_ARMADILLO) +#else +# define machine_is_armadillo() (0) +#endif + +#ifdef CONFIG_MACH_IPCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPCU +# endif +# define machine_is_ipcu() (machine_arch_type == MACH_TYPE_IPCU) +#else +# define machine_is_ipcu() (0) +#endif + +#ifdef CONFIG_MACH_LOOX720 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOX720 +# endif +# define machine_is_loox720() (machine_arch_type == MACH_TYPE_LOOX720) +#else +# define machine_is_loox720() (0) +#endif + +#ifdef CONFIG_MACH_IXDP465 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP465 +# endif +# define machine_is_ixdp465() (machine_arch_type == MACH_TYPE_IXDP465) +#else +# define machine_is_ixdp465() (0) +#endif + +#ifdef CONFIG_MACH_IXDP2351 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2351 +# endif +# define machine_is_ixdp2351() (machine_arch_type == MACH_TYPE_IXDP2351) +#else +# define machine_is_ixdp2351() (0) +#endif + +#ifdef CONFIG_MACH_ADSVIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSVIX +# endif +# define machine_is_adsvix() (machine_arch_type == MACH_TYPE_ADSVIX) +#else +# define machine_is_adsvix() (0) +#endif + +#ifdef CONFIG_MACH_DM270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM270 +# endif +# define machine_is_dm270() (machine_arch_type == MACH_TYPE_DM270) +#else +# define machine_is_dm270() (0) +#endif + +#ifdef CONFIG_MACH_SOCLTPLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOCLTPLUS +# endif +# define machine_is_socltplus() (machine_arch_type == MACH_TYPE_SOCLTPLUS) +#else +# define machine_is_socltplus() (0) +#endif + +#ifdef CONFIG_MACH_ECIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECIA +# endif +# define machine_is_ecia() (machine_arch_type == MACH_TYPE_ECIA) +#else +# define machine_is_ecia() (0) +#endif + +#ifdef CONFIG_MACH_CM4008 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM4008 +# endif +# define machine_is_cm4008() (machine_arch_type == MACH_TYPE_CM4008) +#else +# define machine_is_cm4008() (0) +#endif + +#ifdef CONFIG_MACH_P2001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P2001 +# endif +# define machine_is_p2001() (machine_arch_type == MACH_TYPE_P2001) +#else +# define machine_is_p2001() (0) +#endif + +#ifdef CONFIG_MACH_TWISTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TWISTER +# endif +# define machine_is_twister() (machine_arch_type == MACH_TYPE_TWISTER) +#else +# define machine_is_twister() (0) +#endif + +#ifdef CONFIG_MACH_MUDSHARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MUDSHARK +# endif +# define machine_is_mudshark() (machine_arch_type == MACH_TYPE_MUDSHARK) +#else +# define machine_is_mudshark() (0) +#endif + +#ifdef CONFIG_MACH_HB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HB2 +# endif +# define machine_is_hb2() (machine_arch_type == MACH_TYPE_HB2) +#else +# define machine_is_hb2() (0) +#endif + +#ifdef CONFIG_MACH_IQ80332 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80332 +# endif +# define machine_is_iq80332() (machine_arch_type == MACH_TYPE_IQ80332) +#else +# define machine_is_iq80332() (0) +#endif + +#ifdef CONFIG_MACH_SENDT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SENDT +# endif +# define machine_is_sendt() (machine_arch_type == MACH_TYPE_SENDT) +#else +# define machine_is_sendt() (0) +#endif + +#ifdef CONFIG_MACH_MX2JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX2JAZZ +# endif +# define machine_is_mx2jazz() (machine_arch_type == MACH_TYPE_MX2JAZZ) +#else +# define machine_is_mx2jazz() (0) +#endif + +#ifdef CONFIG_MACH_MULTIIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIIO +# endif +# define machine_is_multiio() (machine_arch_type == MACH_TYPE_MULTIIO) +#else +# define machine_is_multiio() (0) +#endif + +#ifdef CONFIG_MACH_HRDISPLAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HRDISPLAY +# endif +# define machine_is_hrdisplay() (machine_arch_type == MACH_TYPE_HRDISPLAY) +#else +# define machine_is_hrdisplay() (0) +#endif + +#ifdef CONFIG_MACH_SCMA11BB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCMA11BB +# endif +# define machine_is_scma11bb() (machine_arch_type == MACH_TYPE_SCMA11BB) +#else +# define machine_is_scma11bb() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS3 +# endif +# define machine_is_trizeps3() (machine_arch_type == MACH_TYPE_TRIZEPS3) +#else +# define machine_is_trizeps3() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZA +# endif +# define machine_is_zefeerdza() (machine_arch_type == MACH_TYPE_ZEFEERDZA) +#else +# define machine_is_zefeerdza() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZB +# endif +# define machine_is_zefeerdzb() (machine_arch_type == MACH_TYPE_ZEFEERDZB) +#else +# define machine_is_zefeerdzb() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZG +# endif +# define machine_is_zefeerdzg() (machine_arch_type == MACH_TYPE_ZEFEERDZG) +#else +# define machine_is_zefeerdzg() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZN +# endif +# define machine_is_zefeerdzn() (machine_arch_type == MACH_TYPE_ZEFEERDZN) +#else +# define machine_is_zefeerdzn() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZQ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZQ +# endif +# define machine_is_zefeerdzq() (machine_arch_type == MACH_TYPE_ZEFEERDZQ) +#else +# define machine_is_zefeerdzq() (0) +#endif + +#ifdef CONFIG_MACH_GTWX5715 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTWX5715 +# endif +# define machine_is_gtwx5715() (machine_arch_type == MACH_TYPE_GTWX5715) +#else +# define machine_is_gtwx5715() (0) +#endif + +#ifdef CONFIG_MACH_ASTRO_JACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASTRO_JACK +# endif +# define machine_is_astro_jack() (machine_arch_type == MACH_TYPE_ASTRO_JACK) +#else +# define machine_is_astro_jack() (0) +#endif + +#ifdef CONFIG_MACH_TIP03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIP03 +# endif +# define machine_is_tip03() (machine_arch_type == MACH_TYPE_TIP03) +#else +# define machine_is_tip03() (0) +#endif + +#ifdef CONFIG_MACH_A9200EC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9200EC +# endif +# define machine_is_a9200ec() (machine_arch_type == MACH_TYPE_A9200EC) +#else +# define machine_is_a9200ec() (0) +#endif + +#ifdef CONFIG_MACH_PNX0105 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX0105 +# endif +# define machine_is_pnx0105() (machine_arch_type == MACH_TYPE_PNX0105) +#else +# define machine_is_pnx0105() (0) +#endif + +#ifdef CONFIG_MACH_ADCPOECPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADCPOECPU +# endif +# define machine_is_adcpoecpu() (machine_arch_type == MACH_TYPE_ADCPOECPU) +#else +# define machine_is_adcpoecpu() (0) +#endif + +#ifdef CONFIG_MACH_CSB637 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB637 +# endif +# define machine_is_csb637() (machine_arch_type == MACH_TYPE_CSB637) +#else +# define machine_is_csb637() (0) +#endif + +#ifdef CONFIG_MACH_ML69Q6203 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ML69Q6203 +# endif +# define machine_is_ml69q6203() (machine_arch_type == MACH_TYPE_ML69Q6203) +#else +# define machine_is_ml69q6203() (0) +#endif + +#ifdef CONFIG_MACH_MB9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB9200 +# endif +# define machine_is_mb9200() (machine_arch_type == MACH_TYPE_MB9200) +#else +# define machine_is_mb9200() (0) +#endif + +#ifdef CONFIG_MACH_KULUN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KULUN +# endif +# define machine_is_kulun() (machine_arch_type == MACH_TYPE_KULUN) +#else +# define machine_is_kulun() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER +# endif +# define machine_is_snapper() (machine_arch_type == MACH_TYPE_SNAPPER) +#else +# define machine_is_snapper() (0) +#endif + +#ifdef CONFIG_MACH_OPTIMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPTIMA +# endif +# define machine_is_optima() (machine_arch_type == MACH_TYPE_OPTIMA) +#else +# define machine_is_optima() (0) +#endif + +#ifdef CONFIG_MACH_DLHSBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DLHSBC +# endif +# define machine_is_dlhsbc() (machine_arch_type == MACH_TYPE_DLHSBC) +#else +# define machine_is_dlhsbc() (0) +#endif + +#ifdef CONFIG_MACH_X30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_X30 +# endif +# define machine_is_x30() (machine_arch_type == MACH_TYPE_X30) +#else +# define machine_is_x30() (0) +#endif + +#ifdef CONFIG_MACH_N30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N30 +# endif +# define machine_is_n30() (machine_arch_type == MACH_TYPE_N30) +#else +# define machine_is_n30() (0) +#endif + +#ifdef CONFIG_MACH_MANGA_KS8695 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MANGA_KS8695 +# endif +# define machine_is_manga_ks8695() (machine_arch_type == MACH_TYPE_MANGA_KS8695) +#else +# define machine_is_manga_ks8695() (0) +#endif + +#ifdef CONFIG_MACH_AJAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AJAX +# endif +# define machine_is_ajax() (machine_arch_type == MACH_TYPE_AJAX) +#else +# define machine_is_ajax() (0) +#endif + +#ifdef CONFIG_MACH_NEC_MP900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEC_MP900 +# endif +# define machine_is_nec_mp900() (machine_arch_type == MACH_TYPE_NEC_MP900) +#else +# define machine_is_nec_mp900() (0) +#endif + +#ifdef CONFIG_MACH_VVTK1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVTK1000 +# endif +# define machine_is_vvtk1000() (machine_arch_type == MACH_TYPE_VVTK1000) +#else +# define machine_is_vvtk1000() (0) +#endif + +#ifdef CONFIG_MACH_KAFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KAFA +# endif +# define machine_is_kafa() (machine_arch_type == MACH_TYPE_KAFA) +#else +# define machine_is_kafa() (0) +#endif + +#ifdef CONFIG_MACH_VVTK3000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVTK3000 +# endif +# define machine_is_vvtk3000() (machine_arch_type == MACH_TYPE_VVTK3000) +#else +# define machine_is_vvtk3000() (0) +#endif + +#ifdef CONFIG_MACH_PIMX1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PIMX1 +# endif +# define machine_is_pimx1() (machine_arch_type == MACH_TYPE_PIMX1) +#else +# define machine_is_pimx1() (0) +#endif + +#ifdef CONFIG_MACH_OLLIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLLIE +# endif +# define machine_is_ollie() (machine_arch_type == MACH_TYPE_OLLIE) +#else +# define machine_is_ollie() (0) +#endif + +#ifdef CONFIG_MACH_SKYMAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKYMAX +# endif +# define machine_is_skymax() (machine_arch_type == MACH_TYPE_SKYMAX) +#else +# define machine_is_skymax() (0) +#endif + +#ifdef CONFIG_MACH_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JAZZ +# endif +# define machine_is_jazz() (machine_arch_type == MACH_TYPE_JAZZ) +#else +# define machine_is_jazz() (0) +#endif + +#ifdef CONFIG_MACH_TEL_T3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEL_T3 +# endif +# define machine_is_tel_t3() (machine_arch_type == MACH_TYPE_TEL_T3) +#else +# define machine_is_tel_t3() (0) +#endif + +#ifdef CONFIG_MACH_AISINO_FCR255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AISINO_FCR255 +# endif +# define machine_is_aisino_fcr255() (machine_arch_type == MACH_TYPE_AISINO_FCR255) +#else +# define machine_is_aisino_fcr255() (0) +#endif + +#ifdef CONFIG_MACH_BTWEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTWEB +# endif +# define machine_is_btweb() (machine_arch_type == MACH_TYPE_BTWEB) +#else +# define machine_is_btweb() (0) +#endif + +#ifdef CONFIG_MACH_DBG_LH79520 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DBG_LH79520 +# endif +# define machine_is_dbg_lh79520() (machine_arch_type == MACH_TYPE_DBG_LH79520) +#else +# define machine_is_dbg_lh79520() (0) +#endif + +#ifdef CONFIG_MACH_CM41XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM41XX +# endif +# define machine_is_cm41xx() (machine_arch_type == MACH_TYPE_CM41XX) +#else +# define machine_is_cm41xx() (0) +#endif + +#ifdef CONFIG_MACH_TS72XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS72XX +# endif +# define machine_is_ts72xx() (machine_arch_type == MACH_TYPE_TS72XX) +#else +# define machine_is_ts72xx() (0) +#endif + +#ifdef CONFIG_MACH_NGGPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NGGPXA +# endif +# define machine_is_nggpxa() (machine_arch_type == MACH_TYPE_NGGPXA) +#else +# define machine_is_nggpxa() (0) +#endif + +#ifdef CONFIG_MACH_CSB535 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB535 +# endif +# define machine_is_csb535() (machine_arch_type == MACH_TYPE_CSB535) +#else +# define machine_is_csb535() (0) +#endif + +#ifdef CONFIG_MACH_CSB536 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB536 +# endif +# define machine_is_csb536() (machine_arch_type == MACH_TYPE_CSB536) +#else +# define machine_is_csb536() (0) +#endif + +#ifdef CONFIG_MACH_PXA_TRAKPOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_TRAKPOD +# endif +# define machine_is_pxa_trakpod() (machine_arch_type == MACH_TYPE_PXA_TRAKPOD) +#else +# define machine_is_pxa_trakpod() (0) +#endif + +#ifdef CONFIG_MACH_PRAXIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRAXIS +# endif +# define machine_is_praxis() (machine_arch_type == MACH_TYPE_PRAXIS) +#else +# define machine_is_praxis() (0) +#endif + +#ifdef CONFIG_MACH_LH75411 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LH75411 +# endif +# define machine_is_lh75411() (machine_arch_type == MACH_TYPE_LH75411) +#else +# define machine_is_lh75411() (0) +#endif + +#ifdef CONFIG_MACH_OTOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTOM +# endif +# define machine_is_otom() (machine_arch_type == MACH_TYPE_OTOM) +#else +# define machine_is_otom() (0) +#endif + +#ifdef CONFIG_MACH_NEXCODER_2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXCODER_2440 +# endif +# define machine_is_nexcoder_2440() (machine_arch_type == MACH_TYPE_NEXCODER_2440) +#else +# define machine_is_nexcoder_2440() (0) +#endif + +#ifdef CONFIG_MACH_LOOX410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOX410 +# endif +# define machine_is_loox410() (machine_arch_type == MACH_TYPE_LOOX410) +#else +# define machine_is_loox410() (0) +#endif + +#ifdef CONFIG_MACH_WESTLAKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WESTLAKE +# endif +# define machine_is_westlake() (machine_arch_type == MACH_TYPE_WESTLAKE) +#else +# define machine_is_westlake() (0) +#endif + +#ifdef CONFIG_MACH_NSB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB +# endif +# define machine_is_nsb() (machine_arch_type == MACH_TYPE_NSB) +#else +# define machine_is_nsb() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_STN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_STN +# endif +# define machine_is_esl_sarva_stn() (machine_arch_type == MACH_TYPE_ESL_SARVA_STN) +#else +# define machine_is_esl_sarva_stn() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_TFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_TFT +# endif +# define machine_is_esl_sarva_tft() (machine_arch_type == MACH_TYPE_ESL_SARVA_TFT) +#else +# define machine_is_esl_sarva_tft() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_IAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_IAD +# endif +# define machine_is_esl_sarva_iad() (machine_arch_type == MACH_TYPE_ESL_SARVA_IAD) +#else +# define machine_is_esl_sarva_iad() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_ACC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_ACC +# endif +# define machine_is_esl_sarva_acc() (machine_arch_type == MACH_TYPE_ESL_SARVA_ACC) +#else +# define machine_is_esl_sarva_acc() (0) +#endif + +#ifdef CONFIG_MACH_TYPHOON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TYPHOON +# endif +# define machine_is_typhoon() (machine_arch_type == MACH_TYPE_TYPHOON) +#else +# define machine_is_typhoon() (0) +#endif + +#ifdef CONFIG_MACH_CNAV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNAV +# endif +# define machine_is_cnav() (machine_arch_type == MACH_TYPE_CNAV) +#else +# define machine_is_cnav() (0) +#endif + +#ifdef CONFIG_MACH_A730 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A730 +# endif +# define machine_is_a730() (machine_arch_type == MACH_TYPE_A730) +#else +# define machine_is_a730() (0) +#endif + +#ifdef CONFIG_MACH_NETSTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSTAR +# endif +# define machine_is_netstar() (machine_arch_type == MACH_TYPE_NETSTAR) +#else +# define machine_is_netstar() (0) +#endif + +#ifdef CONFIG_MACH_PHASEFALE_SUPERCON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHASEFALE_SUPERCON +# endif +# define machine_is_supercon() (machine_arch_type == MACH_TYPE_PHASEFALE_SUPERCON) +#else +# define machine_is_supercon() (0) +#endif + +#ifdef CONFIG_MACH_SHIVA1100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHIVA1100 +# endif +# define machine_is_shiva1100() (machine_arch_type == MACH_TYPE_SHIVA1100) +#else +# define machine_is_shiva1100() (0) +#endif + +#ifdef CONFIG_MACH_ETEXSC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETEXSC +# endif +# define machine_is_etexsc() (machine_arch_type == MACH_TYPE_ETEXSC) +#else +# define machine_is_etexsc() (0) +#endif + +#ifdef CONFIG_MACH_IXDPG465 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDPG465 +# endif +# define machine_is_ixdpg465() (machine_arch_type == MACH_TYPE_IXDPG465) +#else +# define machine_is_ixdpg465() (0) +#endif + +#ifdef CONFIG_MACH_A9M2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M2410 +# endif +# define machine_is_a9m2410() (machine_arch_type == MACH_TYPE_A9M2410) +#else +# define machine_is_a9m2410() (0) +#endif + +#ifdef CONFIG_MACH_A9M2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M2440 +# endif +# define machine_is_a9m2440() (machine_arch_type == MACH_TYPE_A9M2440) +#else +# define machine_is_a9m2440() (0) +#endif + +#ifdef CONFIG_MACH_A9M9750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M9750 +# endif +# define machine_is_a9m9750() (machine_arch_type == MACH_TYPE_A9M9750) +#else +# define machine_is_a9m9750() (0) +#endif + +#ifdef CONFIG_MACH_A9M9360 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M9360 +# endif +# define machine_is_a9m9360() (machine_arch_type == MACH_TYPE_A9M9360) +#else +# define machine_is_a9m9360() (0) +#endif + +#ifdef CONFIG_MACH_UNC90 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNC90 +# endif +# define machine_is_unc90() (machine_arch_type == MACH_TYPE_UNC90) +#else +# define machine_is_unc90() (0) +#endif + +#ifdef CONFIG_MACH_ECO920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECO920 +# endif +# define machine_is_eco920() (machine_arch_type == MACH_TYPE_ECO920) +#else +# define machine_is_eco920() (0) +#endif + +#ifdef CONFIG_MACH_SATVIEW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SATVIEW +# endif +# define machine_is_satview() (machine_arch_type == MACH_TYPE_SATVIEW) +#else +# define machine_is_satview() (0) +#endif + +#ifdef CONFIG_MACH_ROADRUNNER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROADRUNNER +# endif +# define machine_is_roadrunner() (machine_arch_type == MACH_TYPE_ROADRUNNER) +#else +# define machine_is_roadrunner() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200EK +# endif +# define machine_is_at91rm9200ek() (machine_arch_type == MACH_TYPE_AT91RM9200EK) +#else +# define machine_is_at91rm9200ek() (0) +#endif + +#ifdef CONFIG_MACH_GP32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GP32 +# endif +# define machine_is_gp32() (machine_arch_type == MACH_TYPE_GP32) +#else +# define machine_is_gp32() (0) +#endif + +#ifdef CONFIG_MACH_GEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEM +# endif +# define machine_is_gem() (machine_arch_type == MACH_TYPE_GEM) +#else +# define machine_is_gem() (0) +#endif + +#ifdef CONFIG_MACH_I858 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I858 +# endif +# define machine_is_i858() (machine_arch_type == MACH_TYPE_I858) +#else +# define machine_is_i858() (0) +#endif + +#ifdef CONFIG_MACH_HX2750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HX2750 +# endif +# define machine_is_hx2750() (machine_arch_type == MACH_TYPE_HX2750) +#else +# define machine_is_hx2750() (0) +#endif + +#ifdef CONFIG_MACH_ZEUSEVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEUSEVB +# endif +# define machine_is_zeusevb() (machine_arch_type == MACH_TYPE_ZEUSEVB) +#else +# define machine_is_zeusevb() (0) +#endif + +#ifdef CONFIG_MACH_P700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P700 +# endif +# define machine_is_p700() (machine_arch_type == MACH_TYPE_P700) +#else +# define machine_is_p700() (0) +#endif + +#ifdef CONFIG_MACH_CPE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPE +# endif +# define machine_is_cpe() (machine_arch_type == MACH_TYPE_CPE) +#else +# define machine_is_cpe() (0) +#endif + +#ifdef CONFIG_MACH_SPITZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPITZ +# endif +# define machine_is_spitz() (machine_arch_type == MACH_TYPE_SPITZ) +#else +# define machine_is_spitz() (0) +#endif + +#ifdef CONFIG_MACH_NIMBRA340 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMBRA340 +# endif +# define machine_is_nimbra340() (machine_arch_type == MACH_TYPE_NIMBRA340) +#else +# define machine_is_nimbra340() (0) +#endif + +#ifdef CONFIG_MACH_LPC22XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC22XX +# endif +# define machine_is_lpc22xx() (machine_arch_type == MACH_TYPE_LPC22XX) +#else +# define machine_is_lpc22xx() (0) +#endif + +#ifdef CONFIG_MACH_COMET3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMET3 +# endif +# define machine_is_omap_comet3() (machine_arch_type == MACH_TYPE_COMET3) +#else +# define machine_is_omap_comet3() (0) +#endif + +#ifdef CONFIG_MACH_COMET4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMET4 +# endif +# define machine_is_omap_comet4() (machine_arch_type == MACH_TYPE_COMET4) +#else +# define machine_is_omap_comet4() (0) +#endif + +#ifdef CONFIG_MACH_CSB625 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB625 +# endif +# define machine_is_csb625() (machine_arch_type == MACH_TYPE_CSB625) +#else +# define machine_is_csb625() (0) +#endif + +#ifdef CONFIG_MACH_FORTUNET2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FORTUNET2 +# endif +# define machine_is_fortunet2() (machine_arch_type == MACH_TYPE_FORTUNET2) +#else +# define machine_is_fortunet2() (0) +#endif + +#ifdef CONFIG_MACH_S5H2200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5H2200 +# endif +# define machine_is_s5h2200() (machine_arch_type == MACH_TYPE_S5H2200) +#else +# define machine_is_s5h2200() (0) +#endif + +#ifdef CONFIG_MACH_OPTORM920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPTORM920 +# endif +# define machine_is_optorm920() (machine_arch_type == MACH_TYPE_OPTORM920) +#else +# define machine_is_optorm920() (0) +#endif + +#ifdef CONFIG_MACH_ADSBITSYXB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSYXB +# endif +# define machine_is_adsbitsyxb() (machine_arch_type == MACH_TYPE_ADSBITSYXB) +#else +# define machine_is_adsbitsyxb() (0) +#endif + +#ifdef CONFIG_MACH_ADSSPHERE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSSPHERE +# endif +# define machine_is_adssphere() (machine_arch_type == MACH_TYPE_ADSSPHERE) +#else +# define machine_is_adssphere() (0) +#endif + +#ifdef CONFIG_MACH_ADSPORTAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSPORTAL +# endif +# define machine_is_adsportal() (machine_arch_type == MACH_TYPE_ADSPORTAL) +#else +# define machine_is_adsportal() (0) +#endif + +#ifdef CONFIG_MACH_LN2410SBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LN2410SBC +# endif +# define machine_is_ln2410sbc() (machine_arch_type == MACH_TYPE_LN2410SBC) +#else +# define machine_is_ln2410sbc() (0) +#endif + +#ifdef CONFIG_MACH_CB3RUFC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CB3RUFC +# endif +# define machine_is_cb3rufc() (machine_arch_type == MACH_TYPE_CB3RUFC) +#else +# define machine_is_cb3rufc() (0) +#endif + +#ifdef CONFIG_MACH_MP2USB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP2USB +# endif +# define machine_is_mp2usb() (machine_arch_type == MACH_TYPE_MP2USB) +#else +# define machine_is_mp2usb() (0) +#endif + /* * These have not yet been registered */ diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h index c3b0e4a6ba..146934cf0c 100644 --- a/include/asm-arm/u-boot.h +++ b/include/asm-arm/u-boot.h @@ -24,6 +24,13 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** */ #ifndef _U_BOOT_H_ |
