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-rw-r--r--drivers/net/fec_mxc.c165
-rw-r--r--drivers/net/fec_mxc.h7
-rw-r--r--drivers/net/phy/micrel.c87
-rw-r--r--drivers/net/phy/phy.c5
-rw-r--r--drivers/spi/mxc_spi.c93
5 files changed, 217 insertions, 140 deletions
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ed733535d5..1fdd071e38 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -70,34 +70,15 @@ static void swap_packet(uint32_t *packet, int length)
#endif
/*
- * The i.MX28 has two ethernet interfaces, but they are not equal.
- * Only the first one can access the MDIO bus.
- */
-#ifdef CONFIG_MX28
-static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
-{
- return (struct ethernet_regs *)MXS_ENET0_BASE;
-}
-#else
-static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
-{
- return fec->eth;
-}
-#endif
-
-/*
* MII-interface related functions
*/
-static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
- uint16_t *retVal)
+static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
+ uint8_t regAddr)
{
- struct eth_device *edev = eth_get_dev_by_name(dev);
- struct fec_priv *fec = (struct fec_priv *)edev->priv;
- struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
-
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
uint32_t start;
+ int val;
/*
* reading from any PHY's register is done by properly
@@ -129,10 +110,10 @@ static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
/*
* it's now safe to read the PHY's register
*/
- *retVal = readl(&eth->mii_data);
- debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
- regAddr, *retVal);
- return 0;
+ val = (unsigned short)readl(&eth->mii_data);
+ debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
+ regAddr, val);
+ return val;
}
static void fec_mii_setspeed(struct fec_priv *fec)
@@ -143,16 +124,12 @@ static void fec_mii_setspeed(struct fec_priv *fec)
*/
writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
&fec->eth->mii_speed);
- debug("fec_init: mii_speed %08x\n",
- readl(&fec->eth->mii_speed));
+ debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed));
}
-static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
- uint16_t data)
-{
- struct eth_device *edev = eth_get_dev_by_name(dev);
- struct fec_priv *fec = (struct fec_priv *)edev->priv;
- struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
+static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
+ uint8_t regAddr, uint16_t data)
+{
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
uint32_t start;
@@ -178,15 +155,28 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
* clear MII interrupt bit
*/
writel(FEC_IEVENT_MII, &eth->ievent);
- debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
+ debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
regAddr, data);
return 0;
}
+int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
+{
+ return fec_mdio_read(bus->priv, phyAddr, regAddr);
+}
+
+int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
+ u16 data)
+{
+ return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
+}
+
+#ifndef CONFIG_PHYLIB
static int miiphy_restart_aneg(struct eth_device *dev)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct ethernet_regs *eth = fec->bus->priv;
int ret = 0;
/*
@@ -194,19 +184,18 @@ static int miiphy_restart_aneg(struct eth_device *dev)
* Reset PHY, then delay 300ns
*/
#ifdef CONFIG_MX27
- miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF);
+ fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
#endif
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
- BMCR_RESET);
+ fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
udelay(1000);
/*
* Set the auto-negotiation advertisement register bits
*/
- miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
+ fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
LPA_100FULL | LPA_100HALF | LPA_10FULL |
LPA_10HALF | PHY_ANLPAR_PSB_802_3);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
+ fec_mdio_write(eth, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);
if (fec->mii_postcall)
@@ -218,8 +207,9 @@ static int miiphy_restart_aneg(struct eth_device *dev)
static int miiphy_wait_aneg(struct eth_device *dev)
{
uint32_t start;
- uint16_t status;
+ int status;
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct ethernet_regs *eth = fec->bus->priv;
/*
* Wait for AN completion
@@ -231,9 +221,9 @@ static int miiphy_wait_aneg(struct eth_device *dev)
return -1;
}
- if (miiphy_read(dev->name, fec->phy_id,
- MII_BMSR, &status)) {
- printf("%s: Autonegotiation failed. status: 0x%04x\n",
+ status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
+ if (status < 0) {
+ printf("%s: Autonegotiation failed. status: %d\n",
dev->name, status);
return -1;
}
@@ -241,6 +231,8 @@ static int miiphy_wait_aneg(struct eth_device *dev)
return 0;
}
+#endif
+
static int fec_rx_task_enable(struct fec_priv *fec)
{
writel(1 << 24, &fec->eth->r_des_active);
@@ -372,6 +364,21 @@ static int fec_set_hwaddr(struct eth_device *dev)
return 0;
}
+static void fec_eth_phy_config(struct eth_device *dev)
+{
+#ifdef CONFIG_PHYLIB
+ struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct phy_device *phydev;
+
+ phydev = phy_connect(fec->bus, fec->phy_id, dev,
+ PHY_INTERFACE_MODE_RGMII);
+ if (phydev) {
+ fec->phydev = phydev;
+ phy_config(phydev);
+ }
+#endif
+}
+
/**
* Start the FEC engine
* @param[in] dev Our device to handle
@@ -379,13 +386,14 @@ static int fec_set_hwaddr(struct eth_device *dev)
static int fec_open(struct eth_device *edev)
{
struct fec_priv *fec = (struct fec_priv *)edev->priv;
+ int speed;
debug("fec_open: fec_open(dev)\n");
/* full-duplex, heartbeat disabled */
writel(1 << 2, &fec->eth->x_cntrl);
fec->rbd_index = 0;
-#if defined(CONFIG_MX6Q)
+#ifdef FEC_QUIRK_ENET_MAC
/* Enable ENET HW endian SWAP */
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
&fec->eth->ecntrl);
@@ -427,9 +435,37 @@ static int fec_open(struct eth_device *edev)
}
#endif
+#ifdef CONFIG_PHYLIB
+ if (!fec->phydev)
+ fec_eth_phy_config(edev);
+ if (fec->phydev) {
+ /* Start up the PHY */
+ phy_startup(fec->phydev);
+ speed = fec->phydev->speed;
+ } else {
+ speed = _100BASET;
+ }
+#else
miiphy_wait_aneg(edev);
- miiphy_speed(edev->name, fec->phy_id);
+ speed = miiphy_speed(edev->name, fec->phy_id);
miiphy_duplex(edev->name, fec->phy_id);
+#endif
+
+#ifdef FEC_QUIRK_ENET_MAC
+ {
+ u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
+ u32 rcr = (readl(&fec->eth->r_cntrl) &
+ ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
+ FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+ if (speed == _1000BASET)
+ ecr |= FEC_ECNTRL_SPEED;
+ else if (speed != _100BASET)
+ rcr |= FEC_RCNTRL_RMII_10T;
+ writel(ecr, &fec->eth->ecntrl);
+ writel(rcr, &fec->eth->r_cntrl);
+ }
+#endif
+ debug("%s:Speed=%i\n", __func__, speed);
/*
* Enable SmartDMA receive task
@@ -541,9 +577,10 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
fec_tbd_init(fec);
+#ifndef CONFIG_PHYLIB
if (fec->xcv_type != SEVENWIRE)
miiphy_restart_aneg(dev);
-
+#endif
fec_open(dev);
return 0;
}
@@ -745,6 +782,7 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
{
struct eth_device *edev;
struct fec_priv *fec;
+ struct mii_dev *bus;
unsigned char ethaddr[6];
uint32_t start;
int ret = 0;
@@ -819,15 +857,40 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
}
fec->phy_id = phy_id;
- miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
-
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("mdio_alloc failed\n");
+ ret = -ENOMEM;
+ goto err3;
+ }
+ bus->read = fec_phy_read;
+ bus->write = fec_phy_write;
+ sprintf(bus->name, edev->name);
+#ifdef CONFIG_MX28
+ /*
+ * The i.MX28 has two ethernet interfaces, but they are not equal.
+ * Only the first one can access the MDIO bus.
+ */
+ bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE;
+#else
+ bus->priv = fec->eth;
+#endif
+ ret = mdio_register(bus);
+ if (ret) {
+ printf("mdio_register failed\n");
+ free(bus);
+ ret = -ENOMEM;
+ goto err3;
+ }
+ fec->bus = bus;
eth_register(edev);
if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
}
-
+ /* Configure phy */
+ fec_eth_phy_config(edev);
return ret;
err3:
@@ -860,9 +923,11 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
return lout;
}
+#ifndef CONFIG_PHYLIB
int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
fec->mii_postcall = cb;
return 0;
}
+#endif
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 9825eab291..2eb78037fc 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -198,6 +198,7 @@ struct ethernet_regs {
#define FEC_RCNTRL_FCE 0x00000020
#define FEC_RCNTRL_RGMII 0x00000040
#define FEC_RCNTRL_RMII 0x00000100
+#define FEC_RCNTRL_RMII_10T 0x00000200
#define FEC_TCNTRL_GTS 0x00000001
#define FEC_TCNTRL_HBC 0x00000002
@@ -207,6 +208,7 @@ struct ethernet_regs {
#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
+#define FEC_ECNTRL_SPEED 0x00000020
#define FEC_ECNTRL_DBSWAP 0x00000100
#define FEC_X_WMRK_STRFWD 0x00000100
@@ -284,7 +286,12 @@ struct fec_priv {
void *base_ptr;
int dev_id;
int phy_id;
+ struct mii_dev *bus;
+#ifdef CONFIG_PHYLIB
+ struct phy_device *phydev;
+#else
int (*mii_postcall)(int);
+#endif
};
/**
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index d4e64f29d8..e3043dfa20 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -20,6 +20,9 @@
* author Andy Fleming
*
*/
+#include <config.h>
+#include <common.h>
+#include <micrel.h>
#include <phy.h>
static struct phy_driver KSZ804_driver = {
@@ -42,10 +45,94 @@ static struct phy_driver KS8721_driver = {
.shutdown = &genphy_shutdown,
};
+/* ksz9021 PHY Registers */
+#define MII_KSZ9021_EXTENDED_CTRL 0x0b
+#define MII_KSZ9021_EXTENDED_DATAW 0x0c
+#define MII_KSZ9021_EXTENDED_DATAR 0x0d
+#define MII_KSZ9021_PHY_CTL 0x1f
+#define MIIM_KSZ9021_PHYCTL_1000 (1 << 6)
+#define MIIM_KSZ9021_PHYCTL_100 (1 << 5)
+#define MIIM_KSZ9021_PHYCTL_10 (1 << 4)
+#define MIIM_KSZ9021_PHYCTL_DUPLEX (1 << 3)
+
+#define CTRL1000_PREFER_MASTER (1 << 10)
+#define CTRL1000_CONFIG_MASTER (1 << 11)
+#define CTRL1000_MANUAL_CONFIG (1 << 12)
+
+int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
+{
+ /* extended registers */
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
+ return phy_write(phydev, MDIO_DEVAD_NONE,
+ MII_KSZ9021_EXTENDED_DATAW, val);
+}
+
+int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
+{
+ /* extended registers */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
+ return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
+}
+
+/* Micrel ksz9021 */
+static int ksz9021_config(struct phy_device *phydev)
+{
+ unsigned ctrl1000 = 0;
+ const unsigned master = CTRL1000_PREFER_MASTER |
+ CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
+ unsigned features = phydev->drv->features;
+
+ if (getenv("disable_giga"))
+ features &= ~(SUPPORTED_1000baseT_Half |
+ SUPPORTED_1000baseT_Full);
+ /* force master mode for 1000BaseT due to chip errata */
+ if (features & SUPPORTED_1000baseT_Half)
+ ctrl1000 |= ADVERTISE_1000HALF | master;
+ if (features & SUPPORTED_1000baseT_Full)
+ ctrl1000 |= ADVERTISE_1000FULL | master;
+ phydev->advertising = phydev->supported = features;
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
+ genphy_config_aneg(phydev);
+ genphy_restart_aneg(phydev);
+ return 0;
+}
+
+static int ksz9021_startup(struct phy_device *phydev)
+{
+ unsigned phy_ctl;
+ genphy_update_link(phydev);
+ phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_PHY_CTL);
+
+ if (phy_ctl & MIIM_KSZ9021_PHYCTL_DUPLEX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ if (phy_ctl & MIIM_KSZ9021_PHYCTL_1000)
+ phydev->speed = SPEED_1000;
+ else if (phy_ctl & MIIM_KSZ9021_PHYCTL_100)
+ phydev->speed = SPEED_100;
+ else if (phy_ctl & MIIM_KSZ9021_PHYCTL_10)
+ phydev->speed = SPEED_10;
+ return 0;
+}
+
+static struct phy_driver ksz9021_driver = {
+ .name = "Micrel ksz9021",
+ .uid = 0x221610,
+ .mask = 0xfffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &ksz9021_config,
+ .startup = &ksz9021_startup,
+ .shutdown = &genphy_shutdown,
+};
+
int phy_micrel_init(void)
{
phy_register(&KSZ804_driver);
phy_register(&KS8721_driver);
+ phy_register(&ksz9021_driver);
return 0;
}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index eb551803e5..7d327f766a 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -733,6 +733,8 @@ int phy_startup(struct phy_device *phydev)
static int __board_phy_config(struct phy_device *phydev)
{
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
return 0;
}
@@ -741,9 +743,6 @@ int board_phy_config(struct phy_device *phydev)
int phy_config(struct phy_device *phydev)
{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
/* Invoke an optional board-specific helper */
board_phy_config(phydev);
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 2fa748608f..2e1531858d 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -33,93 +33,12 @@
#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
"See linux mxc_spi driver from Freescale for details."
-
-#elif defined(CONFIG_MX31)
-
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_SMC (1 << 3)
-#define MXC_CSPICTRL_POL (1 << 4)
-#define MXC_CSPICTRL_PHA (1 << 5)
-#define MXC_CSPICTRL_SSCTL (1 << 6)
-#define MXC_CSPICTRL_SSPOL (1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
-#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC (1 << 8)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPICTRL_MAXBITS 0x1f
-
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 4
-
-static unsigned long spi_bases[] = {
- 0x43fa4000,
- 0x50010000,
- 0x53f84000,
-};
-
-#elif defined(CONFIG_MX51)
-
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
-#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
-#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 32
-
-/* Bit position inside CTRL register to be associated with SS */
-#define MXC_CSPICTRL_CHAN 18
-
-/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL 4
-#define MXC_CSPICON_PHA 0
-#define MXC_CSPICON_SSPOL 12
-
-static unsigned long spi_bases[] = {
- CSPI1_BASE_ADDR,
- CSPI2_BASE_ADDR,
- CSPI3_BASE_ADDR,
-};
-
-#elif defined(CONFIG_MX35)
-
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_SMC (1 << 3)
-#define MXC_CSPICTRL_POL (1 << 4)
-#define MXC_CSPICTRL_PHA (1 << 5)
-#define MXC_CSPICTRL_SSCTL (1 << 6)
-#define MXC_CSPICTRL_SSPOL (1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 4
+#endif
static unsigned long spi_bases[] = {
- 0x43fa4000,
- 0x50010000,
+ MXC_SPI_BASE_ADDRESSES
};
-#else
-#error "Unsupported architecture"
-#endif
-
#define OUT MXC_GPIO_DIRECTION_OUT
#define reg_read readl
@@ -129,7 +48,7 @@ struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
u32 ctrl_reg;
-#if defined(CONFIG_MX51)
+#if defined(MXC_ECSPI)
u32 cfg_reg;
#endif
int gpio;
@@ -167,7 +86,7 @@ u32 get_cspi_div(u32 div)
return i;
}
-#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#ifdef MXC_CSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
@@ -204,7 +123,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
}
#endif
-#if defined(CONFIG_MX51)
+#ifdef MXC_ECSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
@@ -316,7 +235,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
MXC_CSPICTRL_BITCOUNT(bitlen - 1);
reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
-#ifdef CONFIG_MX51
+#ifdef MXC_ECSPI
reg_write(&regs->cfg, mxcs->cfg_reg);
#endif
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