diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mmc/Makefile | 1 | ||||
-rw-r--r-- | drivers/mmc/atmel_sdhci.c | 40 | ||||
-rw-r--r-- | drivers/mmc/sdhci.c | 20 | ||||
-rw-r--r-- | drivers/rtc/Makefile | 2 | ||||
-rw-r--r-- | drivers/rtc/ds1307.c | 34 | ||||
-rw-r--r-- | drivers/serial/Kconfig | 7 | ||||
-rw-r--r-- | drivers/serial/serial-uclass.c | 30 | ||||
-rw-r--r-- | drivers/serial/serial_zynq.c | 203 | ||||
-rw-r--r-- | drivers/spi/cadence_qspi.c | 33 | ||||
-rw-r--r-- | drivers/spi/cadence_qspi.h | 1 |
10 files changed, 247 insertions, 124 deletions
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 99d02954ed..5d357056dd 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_DM_MMC) += mmc-uclass.o obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o +obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c new file mode 100644 index 0000000000..24b68b640b --- /dev/null +++ b/drivers/mmc/atmel_sdhci.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <sdhci.h> +#include <asm/arch/clk.h> + +#define ATMEL_SDHC_MIN_FREQ 400000 + +int atmel_sdhci_init(void *regbase, u32 id) +{ + struct sdhci_host *host; + u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; + + host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host)); + if (!host) { + printf("%s: sdhci_host calloc failed\n", __func__); + return -ENOMEM; + } + + host->name = "atmel_sdhci"; + host->ioaddr = regbase; + host->quirks = 0; + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + max_clk = at91_get_periph_generated_clk(id); + if (!max_clk) { + printf("%s: Failed to get the proper clock\n", __func__); + free(host); + return -ENODEV; + } + + add_sdhci(host, max_clk, min_clk); + + return 0; +} diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index d89e302841..02d71b9344 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -286,9 +286,25 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) { struct sdhci_host *host = mmc->priv; - unsigned int div, clk, timeout; + unsigned int div, clk, timeout, reg; - sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + /* Wait max 20 ms */ + timeout = 200; + while (sdhci_readl(host, SDHCI_PRESENT_STATE) & + (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { + if (timeout == 0) { + printf("%s: Timeout to wait cmd & data inhibit\n", + __func__); + return -1; + } + + timeout--; + udelay(100); + } + + reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + reg &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); if (clock == 0) return 0; diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 3092de1d9c..fc38a3f309 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -4,7 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # - #ccflags-y += -DDEBUG obj-$(CONFIG_DM_RTC) += rtc-uclass.o @@ -37,6 +36,7 @@ obj-$(CONFIG_RTC_M48T35A) += m48t35ax.o obj-$(CONFIG_RTC_MAX6900) += max6900.o obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o obj-$(CONFIG_RTC_MC146818) += mc146818.o +obj-$(CONFIG_RTC_MCP79411) += ds1307.o obj-$(CONFIG_MCFRTC) += mcfrtc.o obj-$(CONFIG_RTC_MK48T59) += mk48t59.o obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 03ab1a8c5d..3be1da6873 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -58,6 +58,10 @@ #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ #define RTC_CTL_BIT_OUT 0x80 /* Output Control */ +/* MCP7941X-specific bits */ +#define MCP7941X_BIT_ST 0x80 +#define MCP7941X_BIT_VBATEN 0x08 + static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); @@ -69,6 +73,9 @@ int rtc_get (struct rtc_time *tmp) int rel = 0; uchar sec, min, hour, mday, wday, mon, year; +#ifdef CONFIG_RTC_MCP79411 +read_rtc: +#endif sec = rtc_read (RTC_SEC_REG_ADDR); min = rtc_read (RTC_MIN_REG_ADDR); hour = rtc_read (RTC_HR_REG_ADDR); @@ -81,6 +88,7 @@ int rtc_get (struct rtc_time *tmp) "hr: %02x min: %02x sec: %02x\n", year, mon, mday, wday, hour, min, sec); +#ifdef CONFIG_RTC_DS1307 if (sec & RTC_SEC_BIT_CH) { printf ("### Warning: RTC oscillator has stopped\n"); /* clear the CH flag */ @@ -88,6 +96,23 @@ int rtc_get (struct rtc_time *tmp) rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH); rel = -1; } +#endif + +#ifdef CONFIG_RTC_MCP79411 + /* make sure that the backup battery is enabled */ + if (!(wday & MCP7941X_BIT_VBATEN)) { + rtc_write(RTC_DAY_REG_ADDR, + wday | MCP7941X_BIT_VBATEN); + } + + /* clock halted? turn it on, so clock can tick. */ + if (!(sec & MCP7941X_BIT_ST)) { + rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST); + printf("Started RTC\n"); + goto read_rtc; + } +#endif + tmp->tm_sec = bcd2bin (sec & 0x7F); tmp->tm_min = bcd2bin (min & 0x7F); @@ -121,11 +146,20 @@ int rtc_set (struct rtc_time *tmp) rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); +#ifdef CONFIG_RTC_MCP79411 + rtc_write (RTC_DAY_REG_ADDR, + bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN); +#else rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); +#endif rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); +#ifdef CONFIG_RTC_MCP79411 + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST); +#else rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); +#endif return 0; } diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 53b4e1b9d5..d462244a04 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -91,6 +91,13 @@ config DEBUG_UART_S5P will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running. +config DEBUG_UART_ZYNQ + bool "Xilinx Zynq" + help + Select this to enable a debug UART using the serial_s5p driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + endchoice config DEBUG_UART_BASE diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 55011cc4b9..842f78bff3 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -29,14 +29,34 @@ static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; static void serial_find_console_or_panic(void) { + const void *blob = gd->fdt_blob; struct udevice *dev; int node; - if (CONFIG_IS_ENABLED(OF_CONTROL) && gd->fdt_blob) { + if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) { /* Check for a chosen console */ - node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path"); + node = fdtdec_get_chosen_node(blob, "stdout-path"); + if (node < 0) { + const char *str, *p, *name; + + /* + * Deal with things like + * stdout-path = "serial0:115200n8"; + * + * We need to look up the alias and then follow it to + * the correct node. + */ + str = fdtdec_get_chosen_prop(blob, "stdout-path"); + if (str) { + p = strchr(str, ':'); + name = fdt_get_alias_namelen(blob, str, + p ? p - str : strlen(str)); + if (name) + node = fdt_path_offset(blob, name); + } + } if (node < 0) - node = fdt_path_offset(gd->fdt_blob, "console"); + node = fdt_path_offset(blob, "console"); if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) { gd->cur_serial_dev = dev; @@ -48,14 +68,14 @@ static void serial_find_console_or_panic(void) * bind it anyway. */ if (node > 0 && - !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) { + !lists_bind_fdt(gd->dm_root, blob, node, &dev)) { if (!device_probe(dev)) { gd->cur_serial_dev = dev; return; } } } - if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !gd->fdt_blob) { + if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) { /* * Try to use CONFIG_CONS_INDEX if available (it is numbered * from 1!). diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 9d84290196..88bebed236 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -6,6 +6,9 @@ */ #include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <errno.h> #include <fdtdec.h> #include <watchdog.h> #include <asm/io.h> @@ -17,6 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ @@ -37,26 +41,21 @@ struct uart_zynq { u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ }; -static struct uart_zynq *uart_zynq_ports[2] = { - [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, - [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, +struct zynq_uart_priv { + struct uart_zynq *regs; }; /* Set up the baud rate in gd struct */ -static void uart_zynq_serial_setbrg(const int port) +static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, + unsigned long clock, unsigned long baud) { /* Calculation results. */ unsigned int calc_bauderror, bdiv, bgen; unsigned long calc_baud = 0; - unsigned long baud; - unsigned long clock = get_uart_clk(port); - struct uart_zynq *regs = uart_zynq_ports[port]; /* Covering case where input clock is so slow */ - if (clock < 1000000 && gd->baudrate > 4800) - gd->baudrate = 4800; - - baud = gd->baudrate; + if (clock < 1000000 && baud > 4800) + baud = 4800; /* master clock * Baud rate = ------------------ @@ -88,133 +87,131 @@ static void uart_zynq_serial_setbrg(const int port) } /* Initialize the UART, with...some settings. */ -static int uart_zynq_serial_init(const int port) +static void _uart_zynq_serial_init(struct uart_zynq *regs) { - struct uart_zynq *regs = uart_zynq_ports[port]; - - if (!regs) - return -1; - /* RX/TX enabled & reset */ writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ ZYNQ_UART_CR_RXRST, ®s->control); writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ - uart_zynq_serial_setbrg(port); - - return 0; } -static void uart_zynq_serial_putc(const char c, const int port) +static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - struct uart_zynq *regs = uart_zynq_ports[port]; + if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) + return -EAGAIN; - while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) - WATCHDOG_RESET(); - - if (c == '\n') { - writel('\r', ®s->tx_rx_fifo); - while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) - WATCHDOG_RESET(); - } writel(c, ®s->tx_rx_fifo); + + return 0; } -static void uart_zynq_serial_puts(const char *s, const int port) +int zynq_serial_setbrg(struct udevice *dev, int baudrate) { - while (*s) - uart_zynq_serial_putc(*s++, port); + struct zynq_uart_priv *priv = dev_get_priv(dev); + unsigned long clock = get_uart_clk(0); + + _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); + + return 0; } -static int uart_zynq_serial_tstc(const int port) +static int zynq_serial_probe(struct udevice *dev) { - struct uart_zynq *regs = uart_zynq_ports[port]; + struct zynq_uart_priv *priv = dev_get_priv(dev); + + _uart_zynq_serial_init(priv->regs); - return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; + return 0; } -static int uart_zynq_serial_getc(const int port) +static int zynq_serial_getc(struct udevice *dev) { - struct uart_zynq *regs = uart_zynq_ports[port]; + struct zynq_uart_priv *priv = dev_get_priv(dev); + struct uart_zynq *regs = priv->regs; + + if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) + return -EAGAIN; - while (!uart_zynq_serial_tstc(port)) - WATCHDOG_RESET(); return readl(®s->tx_rx_fifo); } -/* Multi serial device functions */ -#define DECLARE_PSSERIAL_FUNCTIONS(port) \ - static int uart_zynq##port##_init(void) \ - { return uart_zynq_serial_init(port); } \ - static void uart_zynq##port##_setbrg(void) \ - { return uart_zynq_serial_setbrg(port); } \ - static int uart_zynq##port##_getc(void) \ - { return uart_zynq_serial_getc(port); } \ - static int uart_zynq##port##_tstc(void) \ - { return uart_zynq_serial_tstc(port); } \ - static void uart_zynq##port##_putc(const char c) \ - { uart_zynq_serial_putc(c, port); } \ - static void uart_zynq##port##_puts(const char *s) \ - { uart_zynq_serial_puts(s, port); } - -/* Serial device descriptor */ -#define INIT_PSSERIAL_STRUCTURE(port, __name) { \ - .name = __name, \ - .start = uart_zynq##port##_init, \ - .stop = NULL, \ - .setbrg = uart_zynq##port##_setbrg, \ - .getc = uart_zynq##port##_getc, \ - .tstc = uart_zynq##port##_tstc, \ - .putc = uart_zynq##port##_putc, \ - .puts = uart_zynq##port##_puts, \ -} +static int zynq_serial_putc(struct udevice *dev, const char ch) +{ + struct zynq_uart_priv *priv = dev_get_priv(dev); -DECLARE_PSSERIAL_FUNCTIONS(0); -static struct serial_device uart_zynq_serial0_device = - INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); -DECLARE_PSSERIAL_FUNCTIONS(1); -static struct serial_device uart_zynq_serial1_device = - INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); + return _uart_zynq_serial_putc(priv->regs, ch); +} -#if CONFIG_IS_ENABLED(OF_CONTROL) -__weak struct serial_device *default_serial_console(void) +static int zynq_serial_pending(struct udevice *dev, bool input) { - const void *blob = gd->fdt_blob; - int node; - unsigned int base_addr; + struct zynq_uart_priv *priv = dev_get_priv(dev); + struct uart_zynq *regs = priv->regs; - node = fdt_path_offset(blob, "serial0"); - if (node < 0) - return NULL; + if (input) + return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); + else + return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); +} - base_addr = fdtdec_get_addr(blob, node, "reg"); - if (base_addr == FDT_ADDR_T_NONE) - return NULL; +static int zynq_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct zynq_uart_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; - if (base_addr == ZYNQ_SERIAL_BASEADDR0) - return &uart_zynq_serial0_device; + addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; - if (base_addr == ZYNQ_SERIAL_BASEADDR1) - return &uart_zynq_serial1_device; + priv->regs = (struct uart_zynq *)addr; - return NULL; + return 0; } -#else -__weak struct serial_device *default_serial_console(void) + +static const struct dm_serial_ops zynq_serial_ops = { + .putc = zynq_serial_putc, + .pending = zynq_serial_pending, + .getc = zynq_serial_getc, + .setbrg = zynq_serial_setbrg, +}; + +static const struct udevice_id zynq_serial_ids[] = { + { .compatible = "xlnx,xuartps" }, + { .compatible = "cdns,uart-r1p8" }, + { } +}; + +U_BOOT_DRIVER(serial_s5p) = { + .name = "serial_zynq", + .id = UCLASS_SERIAL, + .of_match = zynq_serial_ids, + .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct zynq_uart_priv), + .probe = zynq_serial_probe, + .ops = &zynq_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DEBUG_UART_ZYNQ + +#include <debug_uart.h> + +void _debug_uart_init(void) { -#if defined(CONFIG_ZYNQ_SERIAL_UART0) - if (uart_zynq_ports[0]) - return &uart_zynq_serial0_device; -#endif -#if defined(CONFIG_ZYNQ_SERIAL_UART1) - if (uart_zynq_ports[1]) - return &uart_zynq_serial1_device; -#endif - return NULL; + struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; + + _uart_zynq_serial_init(regs); + _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); } -#endif -void zynq_serial_initialize(void) +static inline void _debug_uart_putc(int ch) { - serial_register(&uart_zynq_serial0_device); - serial_register(&uart_zynq_serial1_device); + struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; + + while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); } + +DEBUG_UART_FUNCS + +#endif diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46a1a..4f7fd52532 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -37,9 +37,8 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) } /* Calibration sequence to determine the read data capture delay register */ -static int spi_calibration(struct udevice *bus) +static int spi_calibration(struct udevice *bus, uint hz) { - struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); void *base = priv->regbase; u8 opcode_rdid = 0x9F; @@ -64,7 +63,7 @@ static int spi_calibration(struct udevice *bus) } /* use back the intended clock and find low range */ - cadence_spi_write_speed(bus, plat->max_hz); + cadence_spi_write_speed(bus, hz); for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); @@ -111,7 +110,7 @@ static int spi_calibration(struct udevice *bus) (range_hi + range_lo) / 2, range_lo, range_hi); /* just to ensure we do once only when speed or chip select change */ - priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_hz = hz; priv->qspi_calibrated_cs = spi_chip_select(bus); return 0; @@ -123,17 +122,25 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) struct cadence_spi_priv *priv = dev_get_priv(bus); int err; + if (hz > plat->max_hz) + hz = plat->max_hz; + /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); - cadence_spi_write_speed(bus, hz); - - /* Calibration required for different SCLK speed or chip select */ - if (priv->qspi_calibrated_hz != plat->max_hz || + /* + * Calibration required for different current SCLK speed, requested + * SCLK speed or chip select + */ + if (priv->previous_hz != hz || + priv->qspi_calibrated_hz != hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { - err = spi_calibration(bus); + err = spi_calibration(bus, hz); if (err) return err; + + /* prevent calibration run when same as previous request */ + priv->previous_hz = hz; } /* Enable QSPI */ @@ -291,10 +298,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0]; plat->ahbbase = (void *)data[2]; - /* Use 500KHz as a suitable default */ - plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); - /* All other paramters are embedded in the child node */ subnode = fdt_first_subnode(blob, node); if (subnode < 0) { @@ -302,6 +305,10 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) return -ENODEV; } + /* Use 500 KHz as a suitable default */ + plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency", + 500000); + /* Read other parameters from DT */ plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa5bc..2912e36a53 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -38,6 +38,7 @@ struct cadence_spi_priv { int qspi_is_init; unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; + unsigned int previous_hz; }; /* Functions call declaration */ |