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Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.x86 | 47 |
1 files changed, 42 insertions, 5 deletions
diff --git a/doc/README.x86 b/doc/README.x86 index a9105f87c0..c699b795e2 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -18,11 +18,11 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link on other x86 boards since coreboot deals with most of the low-level details. U-Boot also supports booting directly from x86 reset vector without coreboot, -aka raw support or bare support. Currently Link and Intel Crown Bay board -support running U-Boot 'bare metal'. +aka raw support or bare support. Currently Link, Intel Crown Bay and Intel +Minnowboard Max support running U-Boot 'bare metal'. -As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux -kernel as part of a FIT image. It also supports a compressed zImage. +As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit +Linux kernel as part of a FIT image. It also supports a compressed zImage. Build Instructions ------------------ @@ -47,7 +47,7 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' to point to a new board. You can also change the Cache-As-RAM (CAR) related settings here if the default values do not fit your new board. -Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a +Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is not turned on by default in the U-Boot source tree. Firstly, you need turn it @@ -110,6 +110,33 @@ Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig $ make all + +Intel Minnowboard Max instructions: + +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at +the time of writing). Put it in the board directory: +board/intel/minnowmax/fsp.bin + +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same +directory: board/intel/minnowmax/vga.bin + +You still need two more binary blobs. These come from the sample SPI image +provided in the FSP (SPI.bin at the time of writing). + +Use ifdtool in the U-Boot tools directory to extract the images from that +file, for example: + + $ ./tools/ifdtool -x BayleyBay/SPI.bin + $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin + $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin + +Now you can build U-Boot and obtain u-boot.rom + +$ make minnowmax_defconfig +$ make all + + Test with coreboot ------------------ For testing U-Boot as the coreboot payload, there are things that need be paid @@ -130,6 +157,16 @@ symbol address of _start (in arch/x86/cpu/start.S). If you want to use ELF as the coreboot payload, change U-Boot configuration to use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. +To enable video you must enable these options in coreboot: + + - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) + - Keep VESA framebuffer + +At present it seems that for Minnowboard Max, coreboot does not pass through +the video information correctly (it always says the resolution is 0x0). This +works correctly for link though. + + CPU Microcode ------------- Modern CPUs usually require a special bit stream called microcode [5] to be |
