summaryrefslogtreecommitdiffstats
path: root/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mcf52x2/start.S2
-rw-r--r--cpu/mpc8260/cpu.c9
-rw-r--r--cpu/mpc8260/cpu_init.c28
-rw-r--r--cpu/mpc8260/pci.c19
-rw-r--r--cpu/mpc8260/speed.c8
-rw-r--r--cpu/mpc8xx/serial.c13
-rw-r--r--cpu/ppc4xx/cpu.c30
-rw-r--r--cpu/ppc4xx/cpu_init.c3
-rw-r--r--cpu/ppc4xx/ndfc.c3
-rw-r--r--cpu/ppc4xx/sdram.c2
10 files changed, 102 insertions, 15 deletions
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index f1f4077ebc..7c9a7d2d2b 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -140,11 +140,11 @@ _start:
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
-#if defined(CONFIG_M5282)
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
+#if defined(CONFIG_M5282)
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
index 4f23012b72..94651dc4a6 100644
--- a/cpu/mpc8260/cpu.c
+++ b/cpu/mpc8260/cpu.c
@@ -49,6 +49,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_GET_CPU_STR_F)
+extern int get_cpu_str_f (char *buf);
+#endif
+
int checkcpu (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
@@ -81,7 +85,12 @@ int checkcpu (void)
if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
return -1; /* whoops! someone moved the IMMR */
+#if defined(CONFIG_GET_CPU_STR_F)
+ get_cpu_str_f (buf);
+ printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
+#else
printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
+#endif
/*
* the bottom 16 bits of the immr are the Part Number and Mask Number
diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index 640026be5a..7dcc94999d 100644
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -28,6 +28,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+extern unsigned long board_get_cpu_clk_f (void);
+#endif
+
static void config_8260_ioports (volatile immap_t * immr)
{
int portnum;
@@ -90,6 +94,7 @@ static void config_8260_ioports (volatile immap_t * immr)
}
}
+#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
/*
* Breath some life into the CPU...
*
@@ -102,6 +107,9 @@ void cpu_init_f (volatile immap_t * immr)
#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
uint sccr;
#endif
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+ unsigned long cpu_clk;
+#endif
volatile memctl8260_t *memctl = &immr->im_memctl;
extern void m8260_cpm_reset (void);
@@ -119,10 +127,27 @@ void cpu_init_f (volatile immap_t * immr)
immr->im_clkrst.car_rmr = CFG_RMR;
/* BCR - Bus Configuration Register (4-25) */
+#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE)
+ if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
+ immr->im_siu_conf.sc_bcr = CFG_BCR_60x;
+ } else {
+ immr->im_siu_conf.sc_bcr = CFG_BCR_SINGLE;
+ }
+#else
immr->im_siu_conf.sc_bcr = CFG_BCR;
+#endif
/* SIUMCR - contains debug pin configuration (4-31) */
+#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH)
+ cpu_clk = board_get_cpu_clk_f ();
+ if (cpu_clk >= 100000000) {
+ immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_HIGH;
+ } else {
+ immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_LOW;
+ }
+#else
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
+#endif
config_8260_ioports (immr);
@@ -157,7 +182,8 @@ void cpu_init_f (volatile immap_t * immr)
#endif
/* now restrict to preliminary range */
- memctl->memc_br0 = CFG_BR0_PRELIM;
+ /* the PS came from the HRCW, don´t change it */
+ memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK);
memctl->memc_or0 = CFG_OR0_PRELIM;
#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index b14fc159be..1edd6fb8dd 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -274,7 +274,23 @@ void pci_mpc8250_init (struct pci_controller *hose)
| SIUMCR_CS10PC00
| SIUMCR_BCTLC00
| SIUMCR_MMR11;
-
+#elif defined(CONFIG_TQM8272)
+#if 0
+ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_LBPC11) |
+ SIUMCR_LBPC01 |
+ SIUMCR_CS10PC01 |
+ SIUMCR_APPC10;
+#else
+#if 0
+ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr |
+ SIUMCR_APPC10);
+#else
+ immap->im_siu_conf.sc_siumcr = 0x88000000;
+#endif
+#endif
#else
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@@ -288,6 +304,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
SIUMCR_CS10PC01 |
SIUMCR_APPC10;
#endif
+printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr);
/* Make PCI lowest priority */
/* Each 4 bits is a device bus request and the MS 4bits
diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c
index 360404f0cf..38cd0d9a70 100644
--- a/cpu/mpc8260/speed.c
+++ b/cpu/mpc8260/speed.c
@@ -25,6 +25,10 @@
#include <mpc8260.h>
#include <asm/processor.h>
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+extern unsigned long board_get_cpu_clk_f (void);
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
@@ -112,8 +116,12 @@ int get_clocks (void)
#if !defined(CONFIG_8260_CLKIN)
#error clock measuring not implemented yet - define CONFIG_8260_CLKIN
#else
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+ clkin = board_get_cpu_clk_f ();
+#else
clkin = CONFIG_8260_CLKIN;
#endif
+#endif
sccr = immap->im_clkrst.car_sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index 8ae584f2e1..c8caa793d2 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -227,8 +227,17 @@ static int smc_init (void)
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
-#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */
- *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff;
+#ifdef CFG_SPC1920_SMC1_CLK4
+ /* clock source is PLD */
+
+ /* set freq to 19200 Baud */
+ *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3;
+ /* configure clk4 as input */
+ im->im_ioport.iop_pdpar |= 0x800;
+ im->im_ioport.iop_pddir &= ~0x800;
+
+ cp->cp_simode = 0x0000;
+ cp->cp_simode |= 0x7000;
#else
/* Set up the baud rate generator */
smc_setbrg ();
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 9c5c9109b1..57a7e8d6e2 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -332,24 +332,44 @@ int checkcpu (void)
strcpy(addstr, "No Security/Kasumi support");
break;
- case PVR_440SP_RA:
- puts("SP Rev. A");
+ case PVR_440SP_6_RAB:
+ puts("SP Rev. A/B");
+ strcpy(addstr, "RAID 6 support");
break;
- case PVR_440SP_RB:
- puts("SP Rev. B");
+ case PVR_440SP_RAB:
+ puts("SP Rev. A/B");
+ strcpy(addstr, "No RAID 6 support");
+ break;
+
+ case PVR_440SP_6_RC:
+ puts("SP Rev. C");
+ strcpy(addstr, "RAID 6 support");
break;
case PVR_440SP_RC:
puts("SP Rev. C");
+ strcpy(addstr, "No RAID 6 support");
+ break;
+
+ case PVR_440SPe_6_RA:
+ puts("SPe Rev. A");
+ strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RA:
puts("SPe Rev. A");
+ strcpy(addstr, "No RAID 6 support");
+ break;
+
+ case PVR_440SPe_6_RB:
+ puts("SPe Rev. B");
+ strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RB:
puts("SPe Rev. B");
+ strcpy(addstr, "No RAID 6 support");
break;
default:
@@ -419,7 +439,7 @@ int ppc440spe_revB() {
unsigned int pvr;
pvr = get_pvr();
- if (pvr == PVR_440SPe_RB)
+ if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
return 1;
else
return 0;
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 4b746b072e..db0559b04d 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -31,9 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
-
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-
#ifdef CFG_INIT_DCACHE_CS
# if (CFG_INIT_DCACHE_CS == 0)
# define PBxAP pb0ap
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index 352173128d..b198ff46ce 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -156,7 +156,7 @@ void board_nand_select_device(struct nand_chip *nand, int chip)
out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
}
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
{
int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
@@ -188,6 +188,7 @@ void board_nand_init(struct nand_chip *nand)
*/
board_nand_select_device(nand, cs);
out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
+ return 0;
}
#endif
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index f06038e998..294b89cb2a 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -380,7 +380,7 @@ long int initdram(int board_type)
mtsdram(mem_b0cr, mb0cf[i].reg);
mtsdram(mem_tr0, 0x41094012);
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
- mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/
+ mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
udelay(400); /* Delay 200 usecs (min) */
OpenPOWER on IntegriCloud