diff options
Diffstat (limited to 'cpu/ppc4xx/cpu.c')
| -rw-r--r-- | cpu/ppc4xx/cpu.c | 291 |
1 files changed, 180 insertions, 111 deletions
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index a9bb89ad0a..a26533c59c 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -39,121 +39,146 @@ #if defined(CONFIG_440) -static int do_chip_reset( unsigned long sys0, unsigned long sys1 ); +#define FREQ_EBC (sys_info.freqEPB) +#else +#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) #endif -/* ------------------------------------------------------------------------- */ +#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) -int checkcpu (void) +#define PCI_ASYNC + +int pci_async_enabled(void) { -#if defined(CONFIG_405GP) || \ - defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || \ - defined(CONFIG_440) || \ - defined(CONFIG_IOP480) - uint pvr = get_pvr(); +#if defined(CONFIG_405GP) + return (mfdcr(strap) & PSR_PCI_ASYNC_EN); #endif -#if defined(CONFIG_405GP) || \ - defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || \ - defined(CONFIG_IOP480) - DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + unsigned long val; + + mfsdr(sdr_sdstp1, val); + return (val & SDR0_SDSTP1_PAME_MASK); +#endif +} +#endif + +#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405) +int pci_arbiter_enabled(void) +{ +#if defined(CONFIG_405GP) + return (mfdcr(strap) & PSR_PCI_ARBIT_EN); +#endif + +#if defined(CONFIG_405EP) + return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN); +#endif + +#if defined(CONFIG_440GP) + return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) + unsigned long val; + + mfsdr(sdr_sdstp1, val); + return (val & SDR0_SDSTP1_PAE_MASK); +#endif +} +#endif + +#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440GX) || defined(CONFIG_440SP) + +#define I2C_BOOTROM + +int i2c_bootrom_enabled(void) +{ +#if defined(CONFIG_405EP) + return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) + unsigned long val; + + mfsdr(sdr_sdcs, val); + return (val & SDR0_SDCS_SDD); +#endif +} +#endif + + +#if defined(CONFIG_440) +static int do_chip_reset(unsigned long sys0, unsigned long sys1); +#endif + + +int checkcpu (void) +{ +#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */ + DECLARE_GLOBAL_DATA_PTR; + uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; -#endif -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) - PPC405_SYS_INFO sys_info; +#if !defined(CONFIG_IOP480) + sys_info_t sys_info; puts ("CPU: "); get_sys_info(&sys_info); -#ifdef CONFIG_405GP - puts ("AMCC PowerPC 405GP"); - if (pvr == PVR_405GPR_RB) { - putc('r'); - } - puts (" Rev. "); -#endif -#ifdef CONFIG_405CR - puts ("AMCC PowerPC 405CR Rev. "); + puts("AMCC PowerPC 4"); + +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) + puts("05"); #endif -#ifdef CONFIG_405EP - puts ("AMCC PowerPC 405EP Rev. "); +#if defined(CONFIG_440) + puts("40"); #endif + switch (pvr) { case PVR_405GP_RB: - case PVR_405GPR_RB: - putc('B'); + puts("GP Rev. B"); break; + case PVR_405GP_RC: -#ifdef CONFIG_405CR - case PVR_405CR_RC: -#endif - putc('C'); + puts("GP Rev. C"); break; + case PVR_405GP_RD: - putc('D'); + puts("GP Rev. D"); break; + #ifdef CONFIG_405GP - case PVR_405GP_RE: - putc('E'); + case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ + puts("GP Rev. E"); break; #endif + case PVR_405CR_RA: - putc('A'); + puts("CR Rev. A"); break; + case PVR_405CR_RB: - case PVR_405EP_RB: - putc('B'); + puts("CR Rev. B"); break; - default: - printf ("? (PVR=%08x)", pvr); - break; - } - printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), - sys_info.freqPLB / 1000000, - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, - sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000); - -#if defined(CONFIG_405GP) - if (mfdcr(strap) & PSR_PCI_ASYNC_EN) { - printf (" PCI async ext clock used, "); - } else { - printf (" PCI sync clock at %lu MHz, ", - sys_info.freqPLB / sys_info.pllPciDiv / 1000000); - } - printf ("%sternal PCI arbiter enabled\n", - (mfdcr(strap) & PSR_PCI_ARBIT_EN) ? "in" : "ex"); -#elif defined(CONFIG_405EP) - printf (" IIC Boot EEPROM %sabled\n", - (mfdcr(cpc0_boot) & CPC0_BOOT_SEP) ? "en" : "dis"); - printf (" PCI async ext clock used, "); - printf ("%sternal PCI arbiter enabled\n", - (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) ? "in" : "ex"); +#ifdef CONFIG_405CR + case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ + puts("CR Rev. C"); + break; #endif -#if defined(CONFIG_405EP) - printf (" 16 kB I-Cache 16 kB D-Cache"); -#else - printf (" 16 kB I-Cache %d kB D-Cache", - ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); -#endif -#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ + case PVR_405GPR_RB: + puts("GPr Rev. B"); + break; -#ifdef CONFIG_IOP480 - printf ("PLX IOP480 (PVR=%08x)", pvr); - printf (" at %s MHz:", strmhz(buf, clock)); - printf (" %u kB I-Cache", 4); - printf (" %u kB D-Cache", 2); -#endif + case PVR_405EP_RB: + puts("EP Rev. B"); + break; #if defined(CONFIG_440) - puts ("AMCC PowerPC 440"); - switch(pvr) { case PVR_440GP_RB: puts("GP Rev. B"); /* See errata 1.12: CHIP_4 */ @@ -166,40 +191,103 @@ int checkcpu (void) mfdcr(cpc0_strp1) ); } break; + case PVR_440GP_RC: puts("GP Rev. C"); break; + case PVR_440GX_RA: puts("GX Rev. A"); break; + case PVR_440GX_RB: puts("GX Rev. B"); break; + case PVR_440GX_RC: puts("GX Rev. C"); break; -#if defined(CONFIG_440GR) - case PVR_440EP_RA: - puts("GR Rev. A"); - break; - case PVR_440EP_RB: - puts("GR Rev. B"); + + case PVR_440GX_RF: + puts("GX Rev. F"); break; -#else + case PVR_440EP_RA: puts("EP Rev. A"); break; - case PVR_440EP_RB: + +#ifdef CONFIG_440EP + case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ puts("EP Rev. B"); break; -#endif +#endif /* CONFIG_440EP */ + +#ifdef CONFIG_440GR + case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ + puts("GR Rev. A"); + break; +#endif /* CONFIG_440GR */ +#endif /* CONFIG_440 */ + + case PVR_440SP_RA: + puts("SP Rev. A"); + break; + + case PVR_440SP_RB: + puts("SP Rev. B"); + break; default: printf (" UNKNOWN (PVR=%08x)", pvr); break; } + + printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), + sys_info.freqPLB / 1000000, + sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, + FREQ_EBC / 1000000); + +#if defined(I2C_BOOTROM) + printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); +#endif + +#if defined(CONFIG_PCI) + printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); +#endif + +#if defined(PCI_ASYNC) + if (pci_async_enabled()) { + printf (", PCI async ext clock used"); + } else { + printf (", PCI sync clock at %lu MHz", + sys_info.freqPLB / sys_info.pllPciDiv / 1000000); + } +#endif + +#if defined(CONFIG_PCI) + putc('\n'); #endif - puts ("\n"); + +#if defined(CONFIG_405EP) + printf (" 16 kB I-Cache 16 kB D-Cache"); +#elif defined(CONFIG_440) + printf (" 32 kB I-Cache 32 kB D-Cache"); +#else + printf (" 16 kB I-Cache %d kB D-Cache", + ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); +#endif +#endif /* !defined(CONFIG_IOP480) */ + +#if defined(CONFIG_IOP480) + printf ("PLX IOP480 (PVR=%08x)", pvr); + printf (" at %s MHz:", strmhz(buf, clock)); + printf (" %u kB I-Cache", 4); + printf (" %u kB D-Cache", 2); +#endif + +#endif /* !defined(CONFIG_405) */ + + putc ('\n'); return 0; } @@ -230,8 +318,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #if defined(CONFIG_440) -static -int do_chip_reset (unsigned long sys0, unsigned long sys1) +static int do_chip_reset (unsigned long sys0, unsigned long sys1) { /* Changes to cpc0_sys0 and cpc0_sys1 require chip * reset. @@ -252,31 +339,13 @@ int do_chip_reset (unsigned long sys0, unsigned long sys1) */ unsigned long get_tbclk (void) { -#if defined(CONFIG_440) - +#if !defined(CONFIG_IOP480) sys_info_t sys_info; get_sys_info(&sys_info); return (sys_info.freqProcessor); - -#elif defined(CONFIG_405GP) || \ - defined(CONFIG_405CR) || \ - defined(CONFIG_405) || \ - defined(CONFIG_405EP) - - PPC405_SYS_INFO sys_info; - - get_sys_info(&sys_info); - return (sys_info.freqProcessor); - -#elif defined(CONFIG_IOP480) - - return (66000000); - #else - -# error get_tbclk() not implemented - + return (66000000); #endif } |
