diff options
Diffstat (limited to 'cpu/ppc4xx/405gp_pci.c')
| -rw-r--r-- | cpu/ppc4xx/405gp_pci.c | 73 |
1 files changed, 40 insertions, 33 deletions
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 89be137a86..f6b29e9d6e 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -81,6 +81,10 @@ #ifdef CONFIG_PCI +#if defined(CONFIG_PMC405) +ushort pmc405_pci_subsys_deviceid(void); +#endif + /*#define DEBUG*/ /*-----------------------------------------------------------------------------+ @@ -96,13 +100,10 @@ void pci_405gp_init(struct pci_controller *hose) unsigned short temp_short; unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) - unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart}; - unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1}; char *ptmla_str, *ptmms_str; -#else +#endif unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; -#endif #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; @@ -431,27 +432,33 @@ static struct pci_controller ppc440_hose = {0}; void pci_440_init (struct pci_controller *hose) { int reg_num = 0; - unsigned long strap; +#ifndef CONFIG_DISABLE_PISE_TEST /*--------------------------------------------------------------------------+ * The PCI initialization sequence enable bit must be set ... if not abort * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ -#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) + unsigned long strap; + mfsdr(sdr_sdstp1,strap); - if ( (strap & 0x00010000) == 0 ){ + if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { printf("PCI: SDR0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); return; } -#else +#elif defined(CONFIG_440GP) + unsigned long strap; + strap = mfdcr(cpc0_strp1); - if( (strap & 0x00040000) == 0 ){ + if ((strap & CPC0_STRP1_PISE_MASK) == 0) { printf("PCI: CPC0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); return; } #endif +#endif /* CONFIG_DISABLE_PISE_TEST */ + /*--------------------------------------------------------------------------+ * PCI controller init *--------------------------------------------------------------------------*/ @@ -460,26 +467,26 @@ void pci_440_init (struct pci_controller *hose) pci_set_region(hose->regions + reg_num++, 0x00000000, - PCIX0_IOBASE, - 0x10000, - PCI_REGION_IO); + PCIX0_IOBASE, + 0x10000, + PCI_REGION_IO); pci_set_region(hose->regions + reg_num++, CFG_PCI_TARGBASE, - CFG_PCI_MEMBASE, - 0x10000000, - PCI_REGION_MEM ); + CFG_PCI_MEMBASE, + 0x10000000, + PCI_REGION_MEM ); hose->region_count = reg_num; pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); #if defined(CFG_PCI_PRE_INIT) - /* Let board change/modify hose & do initial checks */ - if( pci_pre_init (hose) == 0 ){ - printf("PCI: Board-specific initialization failed.\n"); - printf("PCI: Configuration aborted.\n"); - return; - } + /* Let board change/modify hose & do initial checks */ + if (pci_pre_init (hose) == 0) { + printf("PCI: Board-specific initialization failed.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } #endif pci_register_hose( hose ); @@ -490,9 +497,9 @@ void pci_440_init (struct pci_controller *hose) #if defined(CFG_PCI_TARGET_INIT) pci_target_init(hose); /* Let board setup pci target */ #else - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID ); - out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID ); + out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif #if defined(CONFIG_440GX) @@ -518,24 +525,24 @@ void pci_440_init (struct pci_controller *hose) out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); out32r( PCIX0_POM0PCIAH, 0x00000000 ); out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ - out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); + out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); #endif /*--------------------------------------------------------------------------+ * PCI host configuration -- we don't make any assumptions here ... the - * _board_must_indicate_ what to do -- there's just too many runtime - * scenarios in environments like cPCI, PPMC, etc. to make a determination - * based on hard-coded values or state of arbiter enable. + * _board_must_indicate_ what to do -- there's just too many runtime + * scenarios in environments like cPCI, PPMC, etc. to make a determination + * based on hard-coded values or state of arbiter enable. *--------------------------------------------------------------------------*/ - if( is_pci_host(hose) ){ + if (is_pci_host(hose)) { #ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); + printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) - out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); + out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); #endif - hose->last_busno = pci_hose_scan(hose); - } + hose->last_busno = pci_hose_scan(hose); + } } |
