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-rw-r--r--board/google/chromebook_link/Kconfig31
-rw-r--r--board/google/chromebook_link/MAINTAINERS6
-rw-r--r--board/google/chromebook_link/Makefile15
-rw-r--r--board/google/chromebook_link/link.c124
-rw-r--r--board/google/common/Makefile7
-rw-r--r--board/google/common/early_init.S29
6 files changed, 212 insertions, 0 deletions
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
new file mode 100644
index 0000000000..3a4f557d30
--- /dev/null
+++ b/board/google/chromebook_link/Kconfig
@@ -0,0 +1,31 @@
+if TARGET_CHROMEBOOK_LINK
+
+config SYS_BOARD
+ default "chromebook_link"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "ivybridge"
+
+config SYS_CONFIG_NAME
+ default "chromebook_link"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select HAVE_ACPI_RESUME
+ select MARK_GRAPHICS_MEM_WRCOMB
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config EARLY_POST_CROS_EC
+ bool "Enable early post to Chrome OS EC"
+ default y
+
+endif
diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS
new file mode 100644
index 0000000000..bc253a2ba7
--- /dev/null
+++ b/board/google/chromebook_link/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK LINK BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_link/
+F: include/configs/chromebook_link.h
+F: configs/chromebook_link_defconfig
diff --git a/board/google/chromebook_link/Makefile b/board/google/chromebook_link/Makefile
new file mode 100644
index 0000000000..a133c2e894
--- /dev/null
+++ b/board/google/chromebook_link/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += link.o
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
new file mode 100644
index 0000000000..88cee05241
--- /dev/null
+++ b/board/google/chromebook_link/link.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+
+int arch_early_init_r(void)
+{
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ return 0;
+}
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
+ .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
+ .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
+ .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
+ .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
+ .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
+ .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
+ .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
+ .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
+ .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
+ .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
+ .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
+ .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
+ .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio12 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
+ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
+ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
+ .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
+ .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
+ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio36 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_map link_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+
+int board_early_init_f(void)
+{
+ ich_gpio_set_gpio_map(&link_gpio_map);
+
+ return 0;
+}
diff --git a/board/google/common/Makefile b/board/google/common/Makefile
new file mode 100644
index 0000000000..b38bc14ff6
--- /dev/null
+++ b/board/google/common/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += early_init.o
diff --git a/board/google/common/early_init.S b/board/google/common/early_init.S
new file mode 100644
index 0000000000..7017185d06
--- /dev/null
+++ b/board/google/common/early_init.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ /* Enable post codes to EC */
+#ifdef CONFIG_EARLY_POST_CROS_EC
+ mov $0x1b, %ecx
+ rdmsr
+ and $0x100, %eax
+ test %eax, %eax
+ je 1f
+
+ mov $0x8000f8f0, %eax
+ mov $0xcf8, %dx
+ out %eax, (%dx)
+ mov $0xfed1c001, %eax
+ mov $0xcfc, %dx
+ out %eax, (%dx)
+ mov $0xfed1f410, %esp
+ mov (%esp), %eax
+ and $0xfffffffb, %eax
+ mov %eax, (%esp)
+1:
+#endif
+ jmp early_board_init_ret
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