diff options
Diffstat (limited to 'board/freescale/mpc837xemds/mpc837xemds.c')
| -rw-r--r-- | board/freescale/mpc837xemds/mpc837xemds.c | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c new file mode 100644 index 0000000000..0e4ec0213b --- /dev/null +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * CREDITS: Kim Phillips contribute to LIBFDT code + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <i2c.h> +#include <spd.h> +#if defined(CONFIG_SPD_EEPROM) +#include <spd_sdram.h> +#endif +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" +#endif + +int board_early_init_f(void) +{ + u8 *bcsr = (u8 *)CFG_BCSR; + + /* Enable flash write */ + bcsr[0x9] &= ~0x04; + /* Clear all of the interrupt of BCSR */ + bcsr[0xe] = 0xff; + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif +int fixed_sdram(void); + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + /* Initialize DDR ECC byte */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + + /* return total bus DDR size(bytes) */ + return (msize * 1024 * 1024); +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + +#if (CFG_DDR_SIZE != 512) +#warning Currenly any ddr size other than 512 is not supported +#endif + im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + udelay(50000); + + im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; + udelay(1000); + + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + udelay(1000); + + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + __asm__ __volatile__("sync"); + udelay(1000); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + udelay(2000); + return CFG_DDR_SIZE; +} +#endif /*!CFG_SPD_EEPROM */ + +int checkboard(void) +{ + puts("Board: Freescale MPC837xEMDS\n"); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ |
