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-rw-r--r--board/esg/ima3-mx53/imximage.cfg104
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diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
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index 324a90e902..0000000000
--- a/board/esg/ima3-mx53/imximage.cfg
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@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2012
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM nor
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-/* IOMUX for RAM only */
-DATA 4 0x53fa8554 0x300020
-DATA 4 0x53fa8560 0x300020
-DATA 4 0x53fa8594 0x300020
-DATA 4 0x53fa8584 0x300020
-DATA 4 0x53fa8558 0x300040
-DATA 4 0x53fa8568 0x300040
-DATA 4 0x53fa8590 0x300040
-DATA 4 0x53fa857c 0x300040
-DATA 4 0x53fa8564 0x300040
-DATA 4 0x53fa8580 0x300040
-DATA 4 0x53fa8570 0x300220
-DATA 4 0x53fa8578 0x300220
-DATA 4 0x53fa872c 0x300000
-DATA 4 0x53fa8728 0x300000
-DATA 4 0x53fa871c 0x300000
-DATA 4 0x53fa8718 0x300000
-DATA 4 0x53fa8574 0x300020
-DATA 4 0x53fa8588 0x300020
-DATA 4 0x53fa855c 0x0
-DATA 4 0x53fa858c 0x0
-DATA 4 0x53fa856c 0x300040
-DATA 4 0x53fa86f0 0x300000
-DATA 4 0x53fa8720 0x300000
-DATA 4 0x53fa86fc 0x0
-DATA 4 0x53fa86f4 0x0
-DATA 4 0x53fa8714 0x0
-DATA 4 0x53fa8724 0x4000000
-
-/* DDR RAM */
-DATA 4 0x63fd9088 0x40404040
-DATA 4 0x63fd9090 0x40404040
-DATA 4 0x63fd907C 0x01420143
-DATA 4 0x63fd9080 0x01450146
-DATA 4 0x63fd9018 0x00111740
-DATA 4 0x63fd9000 0x84190000
-
-/* esdcfgX */
-DATA 4 0x63fd900C 0x9f5152e3
-DATA 4 0x63fd9010 0xb68e8a63
-DATA 4 0x63fd9014 0x01ff00db
-
-/* Read/Write command delay */
-DATA 4 0x63fd902c 0x000026d2
-
-/* Out of reset delays */
-DATA 4 0x63fd9030 0x00ff0e21
-
-/* ESDCTL ODT timing control */
-DATA 4 0x63fd9008 0x12273030
-
-/* ESDCTL power down control */
-DATA 4 0x63fd9004 0x0002002d
-
-/* Set registers in DDR memory chips */
-DATA 4 0x63fd901c 0x00008032
-DATA 4 0x63fd901c 0x00008033
-DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x052080b0
-DATA 4 0x63fd901c 0x04008040
-
-/* ESDCTL refresh control */
-DATA 4 0x63fd9020 0x00005800
-
-/* PHY ZQ HW control */
-DATA 4 0x63fd9040 0x05380003
-
-/* PHY ODT control */
-DATA 4 0x63fd9058 0x00022222
-
-/* start DDR3 */
-DATA 4 0x63fd901c 0x00000000
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