diff options
Diffstat (limited to 'board/esd')
37 files changed, 216 insertions, 216 deletions
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 5a021552dd..46622a29fd 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -92,7 +92,7 @@ int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); int board_revision(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* @@ -100,8 +100,8 @@ int board_revision(void) */ /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03800000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000); @@ -113,7 +113,7 @@ int board_revision(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x001c0000: @@ -166,7 +166,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * New boards have a single 32MB flash connected to CS0 @@ -174,12 +174,12 @@ int board_early_init_f (void) */ if (board_revision() >= 8) { /* disable CS1 */ - mtebc(pb1ap, 0); - mtebc(pb1cr, 0); + mtebc(PB1AP, 0); + mtebc(PB1CR, 0); /* resize CS0 to 32MB */ - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8); - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8); + mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8); + mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8); } return 0; @@ -209,7 +209,7 @@ int misc_init_r(void) int status; int index; int i; - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; char *str; uchar *logo_addr; ulong logo_size; @@ -219,8 +219,8 @@ int misc_init_r(void) /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { @@ -265,7 +265,7 @@ int misc_init_r(void) } /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); puts("FPGA: "); diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/ar405/flash.c +++ b/board/esd/ar405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 074fe08b1c..8da08facff 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -77,7 +77,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/ash405/flash.c +++ b/board/esd/ash405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 2fe6b7bf04..418d3e237e 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -52,16 +52,16 @@ const unsigned char fpgadata[] = { int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; int index, len, i; int status; /* * Setup GPIO pins */ - cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff; - cntrl0Reg |= 0x0070f000; - mtdcr (cntrl0, cntrl0Reg); + CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff; + CPC0_CR0Reg |= 0x0070f000; + mtdcr (CPC0_CR0, CPC0_CR0Reg); #ifdef FPGA_DEBUG /* set up serial port with default baudrate */ diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c index 56c822ec97..224dde4ee0 100644 --- a/board/esd/canbt/flash.c +++ b/board/esd/canbt/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 01b12232b1..7a92401893 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -56,7 +56,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO12 (CS3) pin diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/cms700/flash.c +++ b/board/esd/cms700/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index cd57ed4598..00c7024a85 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -31,13 +31,13 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * Setup GPIO pins */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); @@ -72,7 +72,7 @@ int board_early_init_f (void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -81,8 +81,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c index 56c822ec97..224dde4ee0 100644 --- a/board/esd/cpci2dp/flash.c +++ b/board/esd/cpci2dp/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index a677c623f7..4c9ed2fa58 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -214,7 +214,7 @@ int ctermm2(void) int cpci405_host(void) { - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) return -1; /* yes, board is cpci405 host */ else return 0; /* no, board is cpci405 adapter */ @@ -222,14 +222,14 @@ int cpci405_host(void) int cpci405_version(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); udelay(1000); /* wait some time before reading input */ @@ -238,7 +238,7 @@ int cpci405_version(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x00180000: @@ -261,7 +261,7 @@ int cpci405_version(void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -283,8 +283,8 @@ int misc_init_r (void) /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, @@ -330,7 +330,7 @@ int misc_init_r (void) } /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); puts("FPGA: "); @@ -400,8 +400,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return 0; } diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c index d535924f86..4fcf174d15 100644 --- a/board/esd/cpci405/flash.c +++ b/board/esd/cpci405/flash.c @@ -91,13 +91,13 @@ unsigned long flash_init (void) size_b1 = 1 << 20; } base_b1 = -size_b1; - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17); - mtdcr (ebccfgd, pbcr); + mtdcr (EBC0_CFGDATA, pbcr); #if 0 /* test-only */ - printf("size_b1=%x base_b1=%x pb1cr = %x\n", + printf("size_b1=%x base_b1=%x PB1CR = %x\n", size_b1, base_b1, pbcr); /* test-only */ #endif } @@ -108,13 +108,13 @@ unsigned long flash_init (void) size_b0 = 1 << 20; } base_b0 = base_b1 - size_b0; - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17); - mtdcr (ebccfgd, pbcr); + mtdcr (EBC0_CFGDATA, pbcr); #if 0 /* test-only */ - printf("size_b0=%x base_b0=%x pb0cr = %x\n", + printf("size_b0=%x base_b0=%x PB0CR = %x\n", size_b0, base_b0, pbcr); /* test-only */ #endif } diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c index 56c822ec97..224dde4ee0 100644 --- a/board/esd/cpciiser4/flash.c +++ b/board/esd/cpciiser4/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index e52d37bc21..fc0d091bca 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -54,7 +54,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO13 (CS4) pin diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/dp405/flash.c +++ b/board/esd/dp405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 8e9ac28b18..28a50c7b0e 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -135,7 +135,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 100 us */ - mtebc (epcr, 0xb8400000); + mtebc (EBC0_CFG, 0xb8400000); return 0; } @@ -143,13 +143,13 @@ int board_early_init_f (void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * Setup UART1 handshaking: use CTS instead of DSR */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c index 240aa09f5b..c62c6a9b03 100644 --- a/board/esd/du405/flash.c +++ b/board/esd/du405/flash.c @@ -67,25 +67,25 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 0ec519b8db..376de98354 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -45,8 +45,8 @@ int board_early_init_f(void) u32 sdr0_pfc1, sdr0_pfc2; u32 reg; - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the GPIO pins @@ -145,8 +145,8 @@ int board_early_init_f(void) mtsdr(SDR0_PFC1, sdr0_pfc1); /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* setup NAND FLASH */ mfsdr(SDR0_CUST0, sdr0_cust0); @@ -176,12 +176,12 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -265,8 +265,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); /* * release IO-RST# @@ -380,35 +380,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/hh405/flash.c +++ b/board/esd/hh405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 5ae4c75861..b72b716ddf 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -374,7 +374,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/hub405/flash.c +++ b/board/esd/hub405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index 03e5ad7dd1..acb23dad1f 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -97,7 +97,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c index e763a895ea..eda7c5713c 100644 --- a/board/esd/ocrtc/flash.c +++ b/board/esd/ocrtc/flash.c @@ -68,9 +68,9 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; switch (size_b1) { case 1 << 20: @@ -90,14 +90,14 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; switch (size_b1) { case 1 << 20: @@ -117,8 +117,8 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index 35bfa95f26..709bcdd980 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -57,7 +57,7 @@ int board_early_init_f (void) * EBC Configuration Register: clear EBTC -> high-Z ebc signals between * transfers, set device-paced timeout to 256 cycles */ - mtebc (epcr, 0x20400000); + mtebc (EBC0_CFG, 0x20400000); return 0; } diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c index 9058483800..67a7bb5d86 100644 --- a/board/esd/pci405/flash.c +++ b/board/esd/pci405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 56184caa8f..04bc569ead 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -67,7 +67,7 @@ const unsigned char fpgadata[] = int board_revision(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* @@ -77,8 +77,8 @@ int board_revision(void) /* * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200); udelay(1000); /* wait some time before reading input */ @@ -87,7 +87,7 @@ int board_revision(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x00100200: @@ -133,7 +133,7 @@ unsigned long fpga_init_state(void) int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) @@ -166,18 +166,18 @@ int board_early_init_f (void) /* * Setup GPIO pins (IRQ4/GPIO21 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00008000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000); /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } @@ -282,11 +282,11 @@ int misc_init_r (void) #define PCI0_BRDGOPT1 0x4a pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); -#define plb0_acr 0x87 +#define PLB0_ACR 0x87 /* * Enable fairness and high bus utilization */ - mtdcr(plb0_acr, 0x98000000); + mtdcr(PLB0_ACR, 0x98000000); free(dst); return (0); @@ -313,14 +313,14 @@ int checkboard (void) printf(" (Rev 1.%ld", gd->board_type); if (gd->board_type >= 2) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* * Setup GPIO pins (Trace/GPIO1 to GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg & ~0x08000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000); udelay(1000); /* wait some time before reading input */ diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/plu405/flash.c +++ b/board/esd/plu405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index e41545a936..a3c1cec6ef 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -90,7 +90,7 @@ int board_early_init_f(void) * EBC Configuration Register: set ready timeout to * 512 ebc-clks -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 192a642aea..5ff87e7a25 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -60,12 +60,12 @@ int board_early_init_f (void) * EBC Configuration Register: * set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); + mtebc (EBC0_CFG, 0xa8400000); /* * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | + mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT | CONFIG_SYS_FPGA_DONE | CONFIG_SYS_XEREADY | CONFIG_SYS_NONMONARCH | @@ -73,7 +73,7 @@ int board_early_init_f (void) if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) { /* rev 1.2 boards */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | + mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE | CONFIG_SYS_SELF_RST) << 5)); } diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index f68e1b5e86..419311aec8 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -127,7 +127,7 @@ int board_early_init_f(void) * - set ready timeout to 512 ebc-clks -> ca. 15 us * - EBC lines are always driven */ - mtebc(epcr, 0xa8400000); + mtebc(EBC0_CFG, 0xa8400000); return 0; } diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index f22a1c2888..119cbf2627 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -64,7 +64,7 @@ struct serial_device *default_serial_console(void) * Use default console on P4 when strapping jumper * is installed (bootstrap option != 'H'). */ - mfsdr(SDR_PINSTP, val); + mfsdr(SDR0_PINSTP, val); if (((val & 0xf0000000) >> 29) != 7) return &serial1_device; @@ -100,8 +100,8 @@ int board_early_init_f(void) u32 reg; /* general EBC configuration (disable EBC timeouts) */ - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xf8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xf8400000); /* * Setup the GPIO pins @@ -134,13 +134,13 @@ int board_early_init_f(void) out_be32((void *)GPIO1_ISR3H, 0x00000000); /* patch PLB:PCI divider for 66MHz PCI */ - mfcpr(clk_spcid, reg); + mfcpr(CPR0_SPCID, reg); if (pci_is_66mhz() && (reg != 0x02000000)) { - mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ + mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ - mfcpr(clk_icfg, reg); + mfcpr(CPR0_ICFG, reg); reg |= CPR0_ICFG_RLI_MASK; - mtcpr(clk_icfg, reg); + mtcpr(CPR0_ICFG, reg); mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */ } @@ -240,19 +240,19 @@ int misc_init_r(void) gd->bd->bi_flashoffset = 0; #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb2cr); + mtdcr(EBC0_CFGADDR, PB2CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - pbcr = mfdcr(ebccfgd); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb2cr); + mtdcr(EBC0_CFGADDR, PB2CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -424,8 +424,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); #ifdef CONFIG_FPGA pmc440_init_fpga(); @@ -507,35 +507,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); #ifdef CONFIG_PCI_PNP hose->fixup_irq = pmc440_pci_fixup_irq; diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/voh405/flash.c +++ b/board/esd/voh405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 91275507e0..7477f56b2b 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -99,7 +99,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/vom405/flash.c +++ b/board/esd/vom405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index a481acaea1..de9c7b974c 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -56,7 +56,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO12 (CS3) pin diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c index 274ada9fe5..a53122b217 100644 --- a/board/esd/wuh405/flash.c +++ b/board/esd/wuh405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index e330fff16c..e86f1d0abc 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -75,7 +75,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } |
