diff options
Diffstat (limited to 'arch')
31 files changed, 745 insertions, 140 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7b20fab407..171ad03429 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -7,139 +7,225 @@ config SYS_ARCH config ARM64 bool +config HAS_VBAR + bool + +config CPU_ARM720T + bool + +config CPU_ARM920T + bool + +config CPU_ARM926EJS + bool + +config CPU_ARM946ES + bool + +config CPU_ARM1136 + bool + +config CPU_ARM1176 + bool + select HAS_VBAR + +config CPU_V7 + bool + select HAS_VBAR + +config CPU_PXA + bool + +config CPU_SA1100 + bool + +config SYS_CPU + default "arm720t" if CPU_ARM720T + default "arm920t" if CPU_ARM920T + default "arm926ejs" if CPU_ARM926EJS + default "arm946es" if CPU_ARM946ES + default "arm1136" if CPU_ARM1136 + default "arm1176" if CPU_ARM1176 + default "armv7" if CPU_V7 + default "pxa" if CPU_PXA + default "sa1100" if CPU_SA1100 + choice prompt "Target select" config TARGET_INTEGRATORAP_CM720T bool "Support integratorap_cm720t" + select CPU_ARM720T config TARGET_INTEGRATORAP_CM920T bool "Support integratorap_cm920t" + select CPU_ARM920T config TARGET_INTEGRATORCP_CM920T bool "Support integratorcp_cm920t" + select CPU_ARM920T config TARGET_A320EVB bool "Support a320evb" + select CPU_ARM920T config TARGET_AT91RM9200EK bool "Support at91rm9200ek" + select CPU_ARM920T config TARGET_EB_CPUX9K2 bool "Support eb_cpux9k2" + select CPU_ARM920T config TARGET_CPUAT91 bool "Support cpuat91" + select CPU_ARM920T config TARGET_EDB93XX bool "Support edb93xx" + select CPU_ARM920T config TARGET_SCB9328 bool "Support scb9328" + select CPU_ARM920T config TARGET_CM4008 bool "Support cm4008" + select CPU_ARM920T config TARGET_CM41XX bool "Support cm41xx" + select CPU_ARM920T config TARGET_VCMA9 bool "Support VCMA9" + select CPU_ARM920T config TARGET_SMDK2410 bool "Support smdk2410" + select CPU_ARM920T config TARGET_INTEGRATORAP_CM926EJS bool "Support integratorap_cm926ejs" + select CPU_ARM926EJS config TARGET_INTEGRATORCP_CM926EJS bool "Support integratorcp_cm926ejs" + select CPU_ARM926EJS config TARGET_ASPENITE bool "Support aspenite" + select CPU_ARM926EJS config TARGET_GPLUGD bool "Support gplugd" + select CPU_ARM926EJS config TARGET_AFEB9260 bool "Support afeb9260" + select CPU_ARM926EJS config TARGET_AT91SAM9260EK bool "Support at91sam9260ek" + select CPU_ARM926EJS config TARGET_AT91SAM9261EK bool "Support at91sam9261ek" + select CPU_ARM926EJS config TARGET_AT91SAM9263EK bool "Support at91sam9263ek" + select CPU_ARM926EJS config TARGET_AT91SAM9M10G45EK bool "Support at91sam9m10g45ek" + select CPU_ARM926EJS config TARGET_AT91SAM9N12EK bool "Support at91sam9n12ek" + select CPU_ARM926EJS config TARGET_AT91SAM9RLEK bool "Support at91sam9rlek" + select CPU_ARM926EJS config TARGET_AT91SAM9X5EK bool "Support at91sam9x5ek" + select CPU_ARM926EJS config TARGET_SNAPPER9260 bool "Support snapper9260" + select CPU_ARM926EJS config TARGET_VL_MA2SC bool "Support vl_ma2sc" + select CPU_ARM926EJS config TARGET_SBC35_A9G20 bool "Support sbc35_a9g20" + select CPU_ARM926EJS config TARGET_TNY_A9260 bool "Support tny_a9260" + select CPU_ARM926EJS config TARGET_USB_A9263 bool "Support usb_a9263" + select CPU_ARM926EJS config TARGET_ETHERNUT5 bool "Support ethernut5" + select CPU_ARM926EJS config TARGET_TOP9000 bool "Support top9000" + select CPU_ARM926EJS config TARGET_MEESC bool "Support meesc" + select CPU_ARM926EJS config TARGET_OTC570 bool "Support otc570" + select CPU_ARM926EJS config TARGET_CPU9260 bool "Support cpu9260" + select CPU_ARM926EJS config TARGET_PM9261 bool "Support pm9261" + select CPU_ARM926EJS config TARGET_PM9263 bool "Support pm9263" + select CPU_ARM926EJS config TARGET_PM9G45 bool "Support pm9g45" + select CPU_ARM926EJS config TARGET_CORVUS bool "Support corvus" + select CPU_ARM926EJS config TARGET_TAURUS bool "Support taurus" + select CPU_ARM926EJS config TARGET_STAMP9G20 bool "Support stamp9g20" + select CPU_ARM926EJS config ARCH_DAVINCI bool "TI DaVinci" + select CPU_ARM926EJS help Support for TI's DaVinci platform. config KIRKWOOD bool "Marvell Kirkwood" + select CPU_ARM926EJS config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" @@ -149,370 +235,478 @@ config TARGET_MAXBCM config TARGET_DEVKIT3250 bool "Support devkit3250" + select CPU_ARM926EJS config TARGET_JADECPU bool "Support jadecpu" + select CPU_ARM926EJS config TARGET_MX25PDK bool "Support mx25pdk" + select CPU_ARM926EJS config TARGET_TX25 bool "Support tx25" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_ZMX25 bool "Support zmx25" + select CPU_ARM926EJS config TARGET_APF27 bool "Support apf27" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_IMX27LITE bool "Support imx27lite" + select CPU_ARM926EJS config TARGET_MAGNESIUM bool "Support magnesium" + select CPU_ARM926EJS config TARGET_APX4DEVKIT bool "Support apx4devkit" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_XFI3 bool "Support xfi3" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_M28EVK bool "Support m28evk" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_MX23EVK bool "Support mx23evk" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_MX28EVK bool "Support mx28evk" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_MX23_OLINUXINO bool "Support mx23_olinuxino" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_BG0900 bool "Support bg0900" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_SANSA_FUZE_PLUS bool "Support sansa_fuze_plus" + select CPU_ARM926EJS select SUPPORT_SPL config TARGET_SC_SPS_1 bool "Support sc_sps_1" + select CPU_ARM926EJS select SUPPORT_SPL config ARCH_NOMADIK bool "ST-Ericsson Nomadik" + select CPU_ARM926EJS config ORION5X bool "Marvell Orion" + select CPU_ARM926EJS config TARGET_DKB bool "Support dkb" + select CPU_ARM926EJS config TARGET_SPEAR300 bool "Support spear300" + select CPU_ARM926EJS config TARGET_SPEAR310 bool "Support spear310" + select CPU_ARM926EJS config TARGET_SPEAR320 bool "Support spear320" + select CPU_ARM926EJS config TARGET_SPEAR600 bool "Support spear600" + select CPU_ARM926EJS config TARGET_X600 bool "Support x600" + select CPU_ARM926EJS select SUPPORT_SPL config ARCH_VERSATILE bool "ARM Ltd. Versatile family" + select CPU_ARM926EJS config TARGET_INTEGRATORCP_CM1136 bool "Support integratorcp_cm1136" + select CPU_ARM1136 config TARGET_IMX31_PHYCORE bool "Support imx31_phycore" + select CPU_ARM1136 config TARGET_QONG bool "Support qong" + select CPU_ARM1136 config TARGET_MX31ADS bool "Support mx31ads" + select CPU_ARM1136 config TARGET_MX31PDK bool "Support mx31pdk" + select CPU_ARM1136 select SUPPORT_SPL config TARGET_TT01 bool "Support tt01" + select CPU_ARM1136 config TARGET_IMX31_LITEKIT bool "Support imx31_litekit" + select CPU_ARM1136 config TARGET_WOODBURN bool "Support woodburn" + select CPU_ARM1136 config TARGET_WOODBURN_SD bool "Support woodburn_sd" + select CPU_ARM1136 select SUPPORT_SPL config TARGET_FLEA3 bool "Support flea3" + select CPU_ARM1136 config TARGET_MX35PDK bool "Support mx35pdk" + select CPU_ARM1136 config TARGET_RPI_B bool "Support rpi_b" + select CPU_ARM1176 config TARGET_TNETV107X_EVM bool "Support tnetv107x_evm" + select CPU_ARM1176 config TARGET_INTEGRATORAP_CM946ES bool "Support integratorap_cm946es" + select CPU_ARM946ES config TARGET_INTEGRATORCP_CM946ES bool "Support integratorcp_cm946es" + select CPU_ARM946ES config TARGET_VEXPRESS_CA15_TC2 bool "Support vexpress_ca15_tc2" + select CPU_V7 config TARGET_VEXPRESS_CA5X2 bool "Support vexpress_ca5x2" + select CPU_V7 config TARGET_VEXPRESS_CA9X4 bool "Support vexpress_ca9x4" + select CPU_V7 config TARGET_KWB bool "Support kwb" + select CPU_V7 select SUPPORT_SPL config TARGET_TSERIES bool "Support tseries" + select CPU_V7 select SUPPORT_SPL config TARGET_CM_T335 bool "Support cm_t335" + select CPU_V7 select SUPPORT_SPL config TARGET_PEPPER bool "Support pepper" + select CPU_V7 select SUPPORT_SPL config TARGET_AM335X_IGEP0033 bool "Support am335x_igep0033" + select CPU_V7 select SUPPORT_SPL config TARGET_PCM051 bool "Support pcm051" + select CPU_V7 select SUPPORT_SPL config TARGET_DRACO bool "Support draco" + select CPU_V7 select SUPPORT_SPL config TARGET_DXR2 bool "Support dxr2" + select CPU_V7 select SUPPORT_SPL config TARGET_PXM2 bool "Support pxm2" + select CPU_V7 select SUPPORT_SPL config TARGET_RUT bool "Support rut" + select CPU_V7 select SUPPORT_SPL config TARGET_PENGWYN bool "Support pengwyn" + select CPU_V7 select SUPPORT_SPL config TARGET_AM335X_EVM bool "Support am335x_evm" + select CPU_V7 select SUPPORT_SPL config TARGET_AM43XX_EVM bool "Support am43xx_evm" + select CPU_V7 select SUPPORT_SPL config TARGET_TI814X_EVM bool "Support ti814x_evm" + select CPU_V7 select SUPPORT_SPL config TARGET_TI816X_EVM bool "Support ti816x_evm" + select CPU_V7 select SUPPORT_SPL config TARGET_SAMA5D3_XPLAINED bool "Support sama5d3_xplained" + select CPU_V7 select SUPPORT_SPL config TARGET_SAMA5D3XEK bool "Support sama5d3xek" + select CPU_V7 select SUPPORT_SPL config TARGET_BCM28155_AP bool "Support bcm28155_ap" + select CPU_V7 config TARGET_BCM958300K bool "Support bcm958300k" + select CPU_V7 config TARGET_BCM958622HR bool "Support bcm958622hr" + select CPU_V7 config ARCH_EXYNOS bool "Samsung EXYNOS" + select CPU_V7 config ARCH_S5PC1XX bool "Samsung S5PC1XX" + select CPU_V7 config ARCH_HIGHBANK bool "Calxeda Highbank" + select CPU_V7 config ARCH_KEYSTONE bool "TI Keystone" + select CPU_V7 select SUPPORT_SPL config TARGET_M53EVK bool "Support m53evk" + select CPU_V7 select SUPPORT_SPL config TARGET_IMA3_MX53 bool "Support ima3-mx53" + select CPU_V7 config TARGET_MX51EVK bool "Support mx51evk" + select CPU_V7 config TARGET_MX53ARD bool "Support mx53ard" + select CPU_V7 config TARGET_MX53EVK bool "Support mx53evk" + select CPU_V7 config TARGET_MX53LOCO bool "Support mx53loco" + select CPU_V7 config TARGET_MX53SMD bool "Support mx53smd" + select CPU_V7 config TARGET_MX51_EFIKAMX bool "Support mx51_efikamx" + select CPU_V7 config TARGET_VISION2 bool "Support vision2" + select CPU_V7 config TARGET_UDOO bool "Support udoo" + select CPU_V7 config TARGET_WANDBOARD bool "Support wandboard" + select CPU_V7 config TARGET_TITANIUM bool "Support titanium" + select CPU_V7 config TARGET_NITROGEN6X bool "Support nitrogen6x" + select CPU_V7 config TARGET_CGTQMX6EVAL bool "Support cgtqmx6eval" + select CPU_V7 config TARGET_EMBESTMX6BOARDS bool "Support embestmx6boards" + select CPU_V7 config TARGET_ARISTAINETOS bool "Support aristainetos" + select CPU_V7 config TARGET_MX6QARM2 bool "Support mx6qarm2" + select CPU_V7 config TARGET_MX6QSABREAUTO bool "Support mx6qsabreauto" + select CPU_V7 config TARGET_MX6SABRESD bool "Support mx6sabresd" + select CPU_V7 config TARGET_MX6SLEVK bool "Support mx6slevk" + select CPU_V7 config TARGET_MX6SXSABRESD bool "Support mx6sxsabresd" + select CPU_V7 config TARGET_GW_VENTANA bool "Support gw_ventana" + select CPU_V7 select SUPPORT_SPL config TARGET_HUMMINGBOARD bool "Support hummingboard" + select CPU_V7 config TARGET_TQMA6 bool "TQ Systems TQMa6 board" + select CPU_V7 config TARGET_OT1200 bool "Bachmann OT1200" + select CPU_V7 config OMAP34XX bool "OMAP34XX SoC" + select CPU_V7 config OMAP44XX bool "OMAP44XX SoC" + select CPU_V7 select SUPPORT_SPL config OMAP54XX bool "OMAP54XX SoC" + select CPU_V7 select SUPPORT_SPL config RMOBILE bool "Renesas ARM SoCs" + select CPU_V7 config TARGET_CM_FX6 bool "Support cm_fx6" + select CPU_V7 select SUPPORT_SPL config TARGET_SOCFPGA_CYCLONE5 bool "Support socfpga_cyclone5" + select CPU_V7 select SUPPORT_SPL config TARGET_SUN4I bool "Support sun4i" + select CPU_V7 select SUPPORT_SPL config TARGET_SUN5I bool "Support sun5i" + select CPU_V7 select SUPPORT_SPL config TARGET_SUN6I bool "Support sun6i" + select CPU_V7 select SUPPORT_SPL config TARGET_SUN7I bool "Support sun7i" + select CPU_V7 select SUPPORT_SPL config TARGET_SUN8I bool "Support sun8i" + select CPU_V7 select SUPPORT_SPL config TARGET_SNOWBALL bool "Support snowball" + select CPU_V7 config TARGET_U8500_HREF bool "Support u8500_href" + select CPU_V7 config TARGET_VF610TWR bool "Support vf610twr" + select CPU_V7 config ZYNQ bool "Xilinx Zynq Platform" + select CPU_V7 select SUPPORT_SPL config TEGRA @@ -520,6 +714,8 @@ config TEGRA select SUPPORT_SPL select SPL select OF_CONTROL if !SPL_BUILD + select CPU_ARM720T if SPL_BUILD + select CPU_V7 if !SPL_BUILD config TARGET_VEXPRESS_AEMV8A bool "Support vexpress_aemv8a" @@ -535,53 +731,69 @@ config TARGET_LS2085A_SIMU config TARGET_LS1021AQDS bool "Support ls1021aqds_nor" + select CPU_V7 config TARGET_LS1021ATWR bool "Support ls1021atwr_nor" + select CPU_V7 config TARGET_BALLOON3 bool "Support balloon3" + select CPU_PXA config TARGET_H2200 bool "Support h2200" + select CPU_PXA config TARGET_PALMLD bool "Support palmld" + select CPU_PXA config TARGET_PALMTC bool "Support palmtc" + select CPU_PXA config TARGET_PALMTREO680 bool "Support palmtreo680" + select CPU_PXA select SUPPORT_SPL config TARGET_PXA255_IDP bool "Support pxa255_idp" + select CPU_PXA config TARGET_TRIZEPSIV bool "Support trizepsiv" + select CPU_PXA config TARGET_VPAC270 bool "Support vpac270" + select CPU_PXA select SUPPORT_SPL config TARGET_XAENIAX bool "Support xaeniax" + select CPU_PXA config TARGET_ZIPITZ2 bool "Support zipitz2" + select CPU_PXA config TARGET_LP8X4X bool "Support lp8x4x" + select CPU_PXA config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" + select CPU_PXA config TARGET_JORNADA bool "Support jornada" + select CPU_SA1100 config ARCH_UNIPHIER bool "Panasonic UniPhier platform" + select CPU_V7 select SUPPORT_SPL endchoice diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/cpu/arm926ejs/davinci/Kconfig index 1791cefa2f..613f04d8b0 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Kconfig +++ b/arch/arm/cpu/arm926ejs/davinci/Kconfig @@ -57,9 +57,6 @@ config TARGET_CALIMAIN endchoice -config SYS_CPU - default "arm926ejs" - config SYS_SOC default "davinci" diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig index 91ffedf732..6c037a16c9 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig +++ b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig @@ -59,9 +59,6 @@ config TARGET_GOFLEXHOME endchoice -config SYS_CPU - default "arm926ejs" - config SYS_SOC default "kirkwood" diff --git a/arch/arm/cpu/arm926ejs/nomadik/Kconfig b/arch/arm/cpu/arm926ejs/nomadik/Kconfig index eda51fdc37..265f336469 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/Kconfig +++ b/arch/arm/cpu/arm926ejs/nomadik/Kconfig @@ -8,9 +8,6 @@ config NOMADIK_NHK8815 endchoice -config SYS_CPU - default "arm926ejs" - config SYS_SOC default "nomadik" diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/cpu/arm926ejs/orion5x/Kconfig index 2d0ab2be17..5a542629c7 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/Kconfig +++ b/arch/arm/cpu/arm926ejs/orion5x/Kconfig @@ -8,9 +8,6 @@ config TARGET_EDMINIV2 endchoice -config SYS_CPU - default "arm926ejs" - config SYS_SOC default "orion5x" diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 3757ffb2c2..697e0945d7 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -38,7 +38,7 @@ int arch_cpu_init(void) #if defined(CONFIG_DW_UDC) periph1_clken |= MISC_USBDENB; #endif -#if defined(CONFIG_DW_I2C) +#if defined(CONFIG_SYS_I2C_DW) periph1_clken |= MISC_I2CENB; #endif #if defined(CONFIG_ST_SMI) diff --git a/arch/arm/cpu/arm926ejs/versatile/Kconfig b/arch/arm/cpu/arm926ejs/versatile/Kconfig index 35c16d876c..d2e76f4afc 100644 --- a/arch/arm/cpu/arm926ejs/versatile/Kconfig +++ b/arch/arm/cpu/arm926ejs/versatile/Kconfig @@ -1,8 +1,5 @@ if ARCH_VERSATILE -config SYS_CPU - default "arm926ejs" - config SYS_BOARD default "versatile" diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index b895223523..090be9383f 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -51,9 +51,6 @@ config TARGET_PEACH_PIT endchoice -config SYS_CPU - default "armv7" - config SYS_SOC default "exynos" diff --git a/arch/arm/cpu/armv7/highbank/Kconfig b/arch/arm/cpu/armv7/highbank/Kconfig index 29ff99511c..0e73c04142 100644 --- a/arch/arm/cpu/armv7/highbank/Kconfig +++ b/arch/arm/cpu/armv7/highbank/Kconfig @@ -1,8 +1,5 @@ if ARCH_HIGHBANK -config SYS_CPU - default "armv7" - config SYS_BOARD default "highbank" diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig index 393885f710..134ae87fe1 100644 --- a/arch/arm/cpu/armv7/keystone/Kconfig +++ b/arch/arm/cpu/armv7/keystone/Kconfig @@ -14,9 +14,6 @@ config TARGET_K2L_EVM endchoice -config SYS_CPU - default "armv7" - config SYS_SOC default "keystone" diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 53c0d24005..c215404469 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -90,9 +90,6 @@ config TARGET_TWISTER endchoice -config SYS_CPU - default "armv7" - config SYS_SOC default "omap3" diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig index e270895135..eccf897258 100644 --- a/arch/arm/cpu/armv7/omap4/Kconfig +++ b/arch/arm/cpu/armv7/omap4/Kconfig @@ -14,9 +14,6 @@ config TARGET_OMAP4_SDP4430 endchoice -config SYS_CPU - default "armv7" - config SYS_SOC default "omap4" diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 2ccf5b919d..129982caca 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -14,9 +14,6 @@ config TARGET_DRA7XX_EVM endchoice -config SYS_CPU - default "armv7" - config SYS_SOC default "omap5" diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index 6c2bb22a85..c46a0cc9b8 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -20,9 +20,6 @@ config TARGET_ALT endchoice -config SYS_CPU - default "armv7" - config SYS_SOC default "rmobile" diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig index 2fbbc18203..628813423f 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -13,9 +13,6 @@ config TARGET_SMDKC100 endchoice -config SYS_CPU - default "armv7" - config SYS_SOC default "s5pc1xx" diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index fedd7c8f7e..fdc05b942f 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -81,12 +81,6 @@ ENTRY(c_runtime_cpu_setup) mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB #endif -/* - * Move vector table - */ - /* Set vector address in CP15 VBAR register */ - ldr r0, =_start - mcr p15, 0, r0, c12, c0, 0 @Set VBAR bx lr diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 8906f64c45..f013dc3cad 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -1,16 +1,10 @@ menu "Panasonic UniPhier platform" depends on ARCH_UNIPHIER -config SYS_CPU - string - default "armv7" - config SYS_SOC - string default "uniphier" config SYS_CONFIG_NAME - string default "ph1_pro4" if MACH_PH1_PRO4 default "ph1_ld4" if MACH_PH1_LD4 default "ph1_sld8" if MACH_PH1_SLD8 diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig index d6655a972b..f418cd6d99 100644 --- a/arch/arm/cpu/armv7/zynq/Kconfig +++ b/arch/arm/cpu/armv7/zynq/Kconfig @@ -17,9 +17,6 @@ config TARGET_ZYNQ_ZC770 endchoice -config SYS_CPU - default "armv7" - config SYS_BOARD default "zynq" diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 9019736d2c..4dacfd941f 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -28,6 +28,8 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USE_IRQ int interrupt_init (void) { + unsigned long cpsr; + /* * setup up stacks if necessary */ @@ -35,6 +37,31 @@ int interrupt_init (void) IRQ_STACK_START_IN = gd->irq_sp + 8; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; + + __asm__ __volatile__("mrs %0, cpsr\n" + : "=r" (cpsr) + : + : "memory"); + + __asm__ __volatile__("msr cpsr_c, %0\n" + "mov sp, %1\n" + : + : "r" (IRQ_MODE | I_BIT | F_BIT | (cpsr & ~FIQ_MODE)), + "r" (IRQ_STACK_START) + : "memory"); + + __asm__ __volatile__("msr cpsr_c, %0\n" + "mov sp, %1\n" + : + : "r" (FIQ_MODE | I_BIT | F_BIT | (cpsr & ~IRQ_MODE)), + "r" (FIQ_STACK_START) + : "memory"); + + __asm__ __volatile__("msr cpsr_c, %0" + : + : "r" (cpsr) + : "memory"); + return arch_interrupt_init(); } diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 8035251563..b4a258ce5c 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -6,6 +6,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <asm-offsets.h> +#include <config.h> #include <linux/linkage.h> /* @@ -52,6 +54,34 @@ fixnext: cmp r2, r3 blo fixloop + /* + * Relocate the exception vectors + */ +#ifdef CONFIG_HAS_VBAR + /* + * If the ARM processor has the security extensions, + * use VBAR to relocate the exception vectors. + */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ +#else + /* + * Copy the relocated exception vectors to the + * correct address + * CP15 c1 V bit gives us the location of the vectors: + * 0x00000000 or 0xFFFF0000. + */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */ + ands r2, r2, #(1 << 13) + ldreq r1, =0x00000000 /* If V=0 */ + ldrne r1, =0xFFFF0000 /* If V=1 */ + ldmia r0!, {r2-r8,r10} + stmia r1!, {r2-r8,r10} + ldmia r0!, {r2-r8,r10} + stmia r1!, {r2-r8,r10} +#endif + relocate_done: #ifdef __XSCALE__ diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 0cb87cee7f..49238ed21e 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -33,7 +33,7 @@ ************************************************************************* */ - .section ".vectors", "x" + .section ".vectors", "ax" /* ************************************************************************* diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index e7bb3e33d5..9d38ef73a7 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -10,4 +10,4 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o -obj-y += interrupts.o cpu.o +obj-y += interrupts.o cpu.o call64.o diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/call64.S new file mode 100644 index 0000000000..74dd5a89dc --- /dev/null +++ b/arch/x86/cpu/call64.S @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2014 Google, Inc + * Copyright (C) 1991, 1992, 1993 Linus Torvalds + * + * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/global_data.h> +#include <asm/msr-index.h> +#include <asm/processor-flags.h> + +.code32 +.globl cpu_call64 +cpu_call64: + /* + * cpu_call64(ulong pgtable, ulong setup_base, ulong target) + * + * eax - pgtable + * edx - setup_base + * ecx - target + */ + cli + push %ecx /* arg2 = target */ + push %edx /* arg1 = setup_base */ + mov %eax, %ebx + + /* Load new GDT with the 64bit segments using 32bit descriptor */ + leal gdt, %eax + movl %eax, gdt+2 + lgdt gdt + + /* Enable PAE mode */ + movl $(X86_CR4_PAE), %eax + movl %eax, %cr4 + + /* Enable the boot page tables */ + leal (%ebx), %eax + movl %eax, %cr3 + + /* Enable Long mode in EFER (Extended Feature Enable Register) */ + movl $MSR_EFER, %ecx + rdmsr + btsl $_EFER_LME, %eax + wrmsr + + /* After gdt is loaded */ + xorl %eax, %eax + lldt %ax + movl $0x20, %eax + ltr %ax + + /* + * Setup for the jump to 64bit mode + * + * When the jump is performed we will be in long mode but + * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1 + * (and in turn EFER.LMA = 1). To jump into 64bit mode we use + * the new gdt/idt that has __KERNEL_CS with CS.L = 1. + * We place all of the values on our mini stack so lret can + * used to perform that far jump. See the gdt below. + */ + pop %esi /* setup_base */ + + pushl $0x10 + leal lret_target, %eax + pushl %eax + + /* Enter paged protected Mode, activating Long Mode */ + movl $(X86_CR0_PG | X86_CR0_PE), %eax + movl %eax, %cr0 + + /* Jump from 32bit compatibility mode into 64bit mode. */ + lret + +code64: +lret_target: + pop %eax /* target */ + mov %eax, %eax /* Clear bits 63:32 */ + jmp *%eax /* Jump to the 64-bit target */ + + .data +gdt: + .word gdt_end - gdt + .long gdt + .word 0 + .quad 0x0000000000000000 /* NULL descriptor */ + .quad 0x00af9a000000ffff /* __KERNEL_CS */ + .quad 0x00cf92000000ffff /* __KERNEL_DS */ + .quad 0x0080890000000000 /* TS descriptor */ + .quad 0x0000000000000000 /* TS continued */ +gdt_end: diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 623e3af61f..2e252532d6 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -18,7 +18,10 @@ #include <common.h> #include <command.h> +#include <errno.h> +#include <malloc.h> #include <asm/control_regs.h> +#include <asm/cpu.h> #include <asm/processor.h> #include <asm/processor-flags.h> #include <asm/interrupt.h> @@ -240,3 +243,144 @@ int icache_status(void) { return 1; } + +void cpu_enable_paging_pae(ulong cr3) +{ + __asm__ __volatile__( + /* Load the page table address */ + "movl %0, %%cr3\n" + /* Enable pae */ + "movl %%cr4, %%eax\n" + "orl $0x00000020, %%eax\n" + "movl %%eax, %%cr4\n" + /* Enable paging */ + "movl %%cr0, %%eax\n" + "orl $0x80000000, %%eax\n" + "movl %%eax, %%cr0\n" + : + : "r" (cr3) + : "eax"); +} + +void cpu_disable_paging_pae(void) +{ + /* Turn off paging */ + __asm__ __volatile__ ( + /* Disable paging */ + "movl %%cr0, %%eax\n" + "andl $0x7fffffff, %%eax\n" + "movl %%eax, %%cr0\n" + /* Disable pae */ + "movl %%cr4, %%eax\n" + "andl $0xffffffdf, %%eax\n" + "movl %%eax, %%cr4\n" + : + : + : "eax"); +} + +static bool has_cpuid(void) +{ + unsigned long flag; + + asm volatile("pushf\n" \ + "pop %%eax\n" + "mov %%eax, %%ecx\n" /* ecx = flags */ + "xor %1, %%eax\n" + "push %%eax\n" + "popf\n" /* flags ^= $2 */ + "pushf\n" + "pop %%eax\n" /* eax = flags */ + "push %%ecx\n" + "popf\n" /* flags = ecx */ + "xor %%ecx, %%eax\n" + "mov %%eax, %0" + : "=r" (flag) + : "i" (1 << 21) + : "eax", "ecx", "memory"); + + return flag != 0; +} + +static bool can_detect_long_mode(void) +{ + unsigned long flag; + + asm volatile("mov $0x80000000, %%eax\n" + "cpuid\n" + "mov %%eax, %0" + : "=r" (flag) + : + : "eax", "ebx", "ecx", "edx", "memory"); + + return flag > 0x80000000UL; +} + +static bool has_long_mode(void) +{ + unsigned long flag; + + asm volatile("mov $0x80000001, %%eax\n" + "cpuid\n" + "mov %%edx, %0" + : "=r" (flag) + : + : "eax", "ebx", "ecx", "edx", "memory"); + + return flag & (1 << 29) ? true : false; +} + +int cpu_has_64bit(void) +{ + return has_cpuid() && can_detect_long_mode() && + has_long_mode(); +} + +int print_cpuinfo(void) +{ + printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86"); + + return 0; +} + +#define PAGETABLE_SIZE (6 * 4096) + +/** + * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode + * + * @pgtable: Pointer to a 24iKB block of memory + */ +static void build_pagetable(uint32_t *pgtable) +{ + uint i; + + memset(pgtable, '\0', PAGETABLE_SIZE); + + /* Level 4 needs a single entry */ + pgtable[0] = (uint32_t)&pgtable[1024] + 7; + + /* Level 3 has one 64-bit entry for each GiB of memory */ + for (i = 0; i < 4; i++) { + pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + + 0x1000 * i + 7; + } + + /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ + for (i = 0; i < 2048; i++) + pgtable[2048 + i * 2] = 0x183 + (i << 21UL); +} + +int cpu_jump_to_64bit(ulong setup_base, ulong target) +{ + uint32_t *pgtable; + + pgtable = memalign(4096, PAGETABLE_SIZE); + if (!pgtable) + return -ENOMEM; + + build_pagetable(pgtable); + cpu_call64((ulong)pgtable, setup_base, target); + free(pgtable); + + return -EFAULT; +} diff --git a/arch/x86/include/asm/bootm.h b/arch/x86/include/asm/bootm.h index 033ab79516..f6a64ce2c9 100644 --- a/arch/x86/include/asm/bootm.h +++ b/arch/x86/include/asm/bootm.h @@ -9,4 +9,20 @@ void bootm_announce_and_cleanup(void); +/** + * boot_linux_kernel() - boot a linux kernel + * + * This boots a kernel image, either 32-bit or 64-bit. It will also work with + * a self-extracting kernel, if you set @image_64bit to false. + * + * @setup_base: Pointer to the setup.bin information for the kernel + * @load_address: Pointer to the start of the kernel image + * @image_64bit: true if the image is a raw 64-bit kernel, false if it + * is raw 32-bit or any type of self-extracting kernel + * such as a bzImage. + * @return -ve error code. This function does not return if the kernel was + * booted successfully. + */ +int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit); + #endif diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h new file mode 100644 index 0000000000..6c6774af76 --- /dev/null +++ b/arch/x86/include/asm/cpu.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __X86_CPU_H +#define __X86_CPU_H + + /** + * cpu_enable_paging_pae() - Enable PAE-paging + * + * @pdpt: Value to set in cr3 (PDPT or PML4T) + */ +void cpu_enable_paging_pae(ulong cr3); + +/** + * cpu_disable_paging_pae() - Disable paging and PAE + */ +void cpu_disable_paging_pae(void); + +/** + * cpu_has_64bit() - Check if the CPU has 64-bit support + * + * @return 1 if this CPU supports long mode (64-bit), 0 if not + */ +int cpu_has_64bit(void); + +/** + * cpu_call64() - Jump to a 64-bit Linux kernel (internal function) + * + * The kernel is uncompressed and the 64-bit entry point is expected to be + * at @target. + * + * This function is used internally - see cpu_jump_to_64bit() for a more + * useful function. + * + * @pgtable: Address of 24KB area containing the page table + * @setup_base: Pointer to the setup.bin information for the kernel + * @target: Pointer to the start of the kernel image + */ +void cpu_call64(ulong pgtable, ulong setup_base, ulong target); + +/** + * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel + * + * The kernel is uncompressed and the 64-bit entry point is expected to be + * at @target. + * + * @setup_base: Pointer to the setup.bin information for the kernel + * @target: Pointer to the start of the kernel image + */ +int cpu_jump_to_64bit(ulong setup_base, ulong target); + +#endif diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 0a36e178f5..6027d593ff 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -44,12 +44,16 @@ #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd +#define MSR_NHM_PLATFORM_INFO 0x000000ce #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) +#define SNB_C1_AUTO_UNDEMOTE (1UL << 27) +#define SNB_C3_AUTO_UNDEMOTE (1UL << 28) +#define MSR_PLATFORM_INFO 0x000000ce #define MSR_MTRRcap 0x000000fe #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e @@ -64,10 +68,20 @@ #define MSR_OFFCORE_RSP_0 0x000001a6 #define MSR_OFFCORE_RSP_1 0x000001a7 +#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad +#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae + +#define MSR_LBR_SELECT 0x000001c8 +#define MSR_LBR_TOS 0x000001c9 +#define MSR_LBR_NHM_FROM 0x00000680 +#define MSR_LBR_NHM_TO 0x000006c0 +#define MSR_LBR_CORE_FROM 0x00000040 +#define MSR_LBR_CORE_TO 0x00000060 #define MSR_IA32_PEBS_ENABLE 0x000003f1 #define MSR_IA32_DS_AREA 0x00000600 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 +#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 #define MSR_MTRRfix64K_00000 0x00000250 #define MSR_MTRRfix16K_80000 0x00000258 @@ -91,7 +105,8 @@ #define MSR_IA32_LASTINTTOIP 0x000001de /* DEBUGCTLMSR bits (others vary by model): */ -#define DEBUGCTLMSR_LBR (1UL << 0) +#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ +/* single-step on branches */ #define DEBUGCTLMSR_BTF (1UL << 1) #define DEBUGCTLMSR_TR (1UL << 6) #define DEBUGCTLMSR_BTS (1UL << 7) @@ -100,11 +115,50 @@ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) +#define MSR_IA32_POWER_CTL 0x000001fc + #define MSR_IA32_MC0_CTL 0x00000400 #define MSR_IA32_MC0_STATUS 0x00000401 #define MSR_IA32_MC0_ADDR 0x00000402 #define MSR_IA32_MC0_MISC 0x00000403 +/* C-state Residency Counters */ +#define MSR_PKG_C3_RESIDENCY 0x000003f8 +#define MSR_PKG_C6_RESIDENCY 0x000003f9 +#define MSR_PKG_C7_RESIDENCY 0x000003fa +#define MSR_CORE_C3_RESIDENCY 0x000003fc +#define MSR_CORE_C6_RESIDENCY 0x000003fd +#define MSR_CORE_C7_RESIDENCY 0x000003fe +#define MSR_PKG_C2_RESIDENCY 0x0000060d +#define MSR_PKG_C8_RESIDENCY 0x00000630 +#define MSR_PKG_C9_RESIDENCY 0x00000631 +#define MSR_PKG_C10_RESIDENCY 0x00000632 + +/* Run Time Average Power Limiting (RAPL) Interface */ + +#define MSR_RAPL_POWER_UNIT 0x00000606 + +#define MSR_PKG_POWER_LIMIT 0x00000610 +#define MSR_PKG_ENERGY_STATUS 0x00000611 +#define MSR_PKG_PERF_STATUS 0x00000613 +#define MSR_PKG_POWER_INFO 0x00000614 + +#define MSR_DRAM_POWER_LIMIT 0x00000618 +#define MSR_DRAM_ENERGY_STATUS 0x00000619 +#define MSR_DRAM_PERF_STATUS 0x0000061b +#define MSR_DRAM_POWER_INFO 0x0000061c + +#define MSR_PP0_POWER_LIMIT 0x00000638 +#define MSR_PP0_ENERGY_STATUS 0x00000639 +#define MSR_PP0_POLICY 0x0000063a +#define MSR_PP0_PERF_STATUS 0x0000063b + +#define MSR_PP1_POWER_LIMIT 0x00000640 +#define MSR_PP1_ENERGY_STATUS 0x00000641 +#define MSR_PP1_POLICY 0x00000642 + +#define MSR_CORE_C1_RES 0x00000660 + #define MSR_AMD64_MC0_MASK 0xc0010044 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) @@ -123,18 +177,31 @@ #define MSR_P6_EVNTSEL0 0x00000186 #define MSR_P6_EVNTSEL1 0x00000187 +#define MSR_KNC_PERFCTR0 0x00000020 +#define MSR_KNC_PERFCTR1 0x00000021 +#define MSR_KNC_EVNTSEL0 0x00000028 +#define MSR_KNC_EVNTSEL1 0x00000029 + +/* Alternative perfctr range with full access. */ +#define MSR_IA32_PMC0 0x000004c1 + /* AMD64 MSRs. Not complete. See the architecture manual for a more complete list. */ #define MSR_AMD64_PATCH_LEVEL 0x0000008b +#define MSR_AMD64_TSC_RATIO 0xc0000104 #define MSR_AMD64_NB_CFG 0xc001001f #define MSR_AMD64_PATCH_LOADER 0xc0010020 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 +#define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_DC_CFG 0xc0011022 +#define MSR_AMD64_BU_CFG2 0xc001102a #define MSR_AMD64_IBSFETCHCTL 0xc0011030 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 +#define MSR_AMD64_IBSFETCH_REG_COUNT 3 +#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) #define MSR_AMD64_IBSOPCTL 0xc0011033 #define MSR_AMD64_IBSOPRIP 0xc0011034 #define MSR_AMD64_IBSOPDATA 0xc0011035 @@ -142,12 +209,21 @@ #define MSR_AMD64_IBSOPDATA3 0xc0011037 #define MSR_AMD64_IBSDCLINAD 0xc0011038 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 +#define MSR_AMD64_IBSOP_REG_COUNT 7 +#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) #define MSR_AMD64_IBSCTL 0xc001103a #define MSR_AMD64_IBSBRTARGET 0xc001103b +#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ + +/* Fam 16h MSRs */ +#define MSR_F16H_L2I_PERF_CTL 0xc0010230 +#define MSR_F16H_L2I_PERF_CTR 0xc0010231 /* Fam 15h MSRs */ #define MSR_F15H_PERF_CTL 0xc0010200 #define MSR_F15H_PERF_CTR 0xc0010201 +#define MSR_F15H_NB_PERF_CTL 0xc0010240 +#define MSR_F15H_NB_PERF_CTR 0xc0010241 /* Fam 10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 @@ -226,7 +302,9 @@ #define MSR_IA32_PLATFORM_ID 0x00000017 #define MSR_IA32_EBL_CR_POWERON 0x0000002a #define MSR_EBC_FREQUENCY_ID 0x0000002c +#define MSR_SMI_COUNT 0x00000034 #define MSR_IA32_FEATURE_CONTROL 0x0000003a +#define MSR_IA32_TSC_ADJUST 0x0000003b #define FEATURE_CONTROL_LOCKED (1<<0) #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) @@ -237,11 +315,16 @@ #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_TSCDEADLINE 0x000006e0 + #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b #define MSR_IA32_PERF_STATUS 0x00000198 #define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 +#define MSR_AMD_PERF_STATUS 0xc0010063 +#define MSR_AMD_PERF_CTL 0xc0010062 #define MSR_IA32_MPERF 0x000000e7 #define MSR_IA32_APERF 0x000000e8 @@ -267,6 +350,9 @@ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 +#define ENERGY_PERF_BIAS_PERFORMANCE 0 +#define ENERGY_PERF_BIAS_NORMAL 6 +#define ENERGY_PERF_BIAS_POWERSAVE 15 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 @@ -320,6 +406,8 @@ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) +#define MSR_IA32_TSC_DEADLINE 0x000006E0 + /* P4/Xeon+ specific */ #define MSR_IA32_MCG_EAX 0x00000180 #define MSR_IA32_MCG_EBX 0x00000181 @@ -446,7 +534,23 @@ #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c - +#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d +#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e +#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f +#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 +#define MSR_IA32_VMX_VMFUNC 0x00000491 + +/* VMX_BASIC bits and bitmasks */ +#define VMX_BASIC_VMCS_SIZE_SHIFT 32 +#define VMX_BASIC_64 0x0001000000000000LLU +#define VMX_BASIC_MEM_TYPE_SHIFT 50 +#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU +#define VMX_BASIC_MEM_TYPE_WB 6LLU +#define VMX_BASIC_INOUT 0x0040000000000000LLU + +/* MSR_IA32_VMX_MISC bits */ +#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) +#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F /* AMD-V MSRs */ #define MSR_VM_CR 0xc0010114 diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 0f36662688..8e7dd424ca 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -35,10 +35,8 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *); struct boot_params *load_zimage(char *image, unsigned long kernel_size, - void **load_address); + ulong *load_addressp); int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, unsigned long initrd_addr, unsigned long initrd_size); -void boot_zimage(void *setup_base, void *load_address); - #endif diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 4c5c7f5aa7..86030cf52a 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -10,10 +10,12 @@ #include <common.h> #include <command.h> +#include <errno.h> #include <fdt_support.h> #include <image.h> #include <u-boot/zlib.h> #include <asm/bootparam.h> +#include <asm/cpu.h> #include <asm/byteorder.h> #include <asm/zimage.h> #ifdef CONFIG_SYS_COREBOOT @@ -109,17 +111,17 @@ static int boot_prep_linux(bootm_headers_t *images) } if (is_zimage) { - void *load_address; + ulong load_address; char *base_ptr; base_ptr = (char *)load_zimage(data, len, &load_address); - images->os.load = (ulong)load_address; + images->os.load = load_address; cmd_line_dest = base_ptr + COMMAND_LINE_OFFSET; images->ep = (ulong)base_ptr; } else if (images->ep) { cmd_line_dest = (void *)images->ep + COMMAND_LINE_OFFSET; } else { - printf("## Kernel loading failed (no setup) ...\n"); + printf("## Kernel loading failed (missing x86 kernel setup) ...\n"); goto error; } @@ -139,16 +141,50 @@ error: return 1; } +int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit) +{ + bootm_announce_and_cleanup(); + +#ifdef CONFIG_SYS_COREBOOT + timestamp_add_now(TS_U_BOOT_START_KERNEL); +#endif + if (image_64bit) { + if (!cpu_has_64bit()) { + puts("Cannot boot 64-bit kernel on 32-bit machine\n"); + return -EFAULT; + } + return cpu_jump_to_64bit(setup_base, load_address); + } else { + /* + * Set %ebx, %ebp, and %edi to 0, %esi to point to the + * boot_params structure, and then jump to the kernel. We + * assume that %cs is 0x10, 4GB flat, and read/execute, and + * the data segments are 0x18, 4GB flat, and read/write. + * U-boot is setting them up that way for itself in + * arch/i386/cpu/cpu.c. + */ + __asm__ __volatile__ ( + "movl $0, %%ebp\n" + "cli\n" + "jmp *%[kernel_entry]\n" + :: [kernel_entry]"a"(load_address), + [boot_params] "S"(setup_base), + "b"(0), "D"(0) + ); + } + + /* We can't get to here */ + return -EFAULT; +} + /* Subcommand: GO */ static int boot_jump_linux(bootm_headers_t *images) { debug("## Transferring control to Linux (at address %08lx, kernel %08lx) ...\n", images->ep, images->os.load); - boot_zimage((struct boot_params *)images->ep, (void *)images->os.load); - /* does not return */ - - return 1; + return boot_linux_kernel(images->ep, images->os.load, + images->os.arch == IH_ARCH_X86_64); } int do_bootm_linux(int flag, int argc, char * const argv[], @@ -161,10 +197,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], if (flag & BOOTM_STATE_OS_PREP) return boot_prep_linux(images); - if (flag & BOOTM_STATE_OS_GO) { - boot_jump_linux(images); - return 0; - } + if (flag & BOOTM_STATE_OS_GO) + return boot_jump_linux(images); return boot_jump_linux(images); } diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index b57b2c30fe..c3c709ec07 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -10,6 +10,7 @@ #include <common.h> #include <physmem.h> +#include <asm/cpu.h> #include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -112,41 +113,13 @@ static void x86_phys_enter_paging(void) x86_phys_map_page(page_addr, page_addr, 0); } - /* Turn on paging */ - __asm__ __volatile__( - /* Load the page table address */ - "movl %0, %%cr3\n\t" - /* Enable pae */ - "movl %%cr4, %%eax\n\t" - "orl $0x00000020, %%eax\n\t" - "movl %%eax, %%cr4\n\t" - /* Enable paging */ - "movl %%cr0, %%eax\n\t" - "orl $0x80000000, %%eax\n\t" - "movl %%eax, %%cr0\n\t" - : - : "r" (pdpt) - : "eax" - ); + cpu_enable_paging_pae((ulong)pdpt); } /* Disable paging and PAE mode. */ static void x86_phys_exit_paging(void) { - /* Turn off paging */ - __asm__ __volatile__ ( - /* Disable paging */ - "movl %%cr0, %%eax\n\t" - "andl $0x7fffffff, %%eax\n\t" - "movl %%eax, %%cr0\n\t" - /* Disable pae */ - "movl %%cr4, %%eax\n\t" - "andl $0xffffffdf, %%eax\n\t" - "movl %%eax, %%cr4\n\t" - : - : - : "eax" - ); + cpu_disable_paging_pae(); } /* diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index b1902834e8..566b048c88 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -103,7 +103,7 @@ static int get_boot_protocol(struct setup_header *hdr) } struct boot_params *load_zimage(char *image, unsigned long kernel_size, - void **load_address) + ulong *load_addressp) { struct boot_params *setup_base; int setup_size; @@ -155,9 +155,9 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, /* Determine load address */ if (big_image) - *load_address = (void *)BZIMAGE_LOAD_ADDR; + *load_addressp = BZIMAGE_LOAD_ADDR; else - *load_address = (void *)ZIMAGE_LOAD_ADDR; + *load_addressp = ZIMAGE_LOAD_ADDR; printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base); memset(setup_base, 0, sizeof(*setup_base)); @@ -204,10 +204,10 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, return 0; } - printf("Loading %s at address %p (%ld bytes)\n", - big_image ? "bzImage" : "zImage", *load_address, kernel_size); + printf("Loading %s at address %lx (%ld bytes)\n", + big_image ? "bzImage" : "zImage", *load_addressp, kernel_size); - memmove(*load_address, image + setup_size, kernel_size); + memmove((void *)*load_addressp, image + setup_size, kernel_size); return setup_base; } @@ -261,30 +261,6 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, return 0; } -void boot_zimage(void *setup_base, void *load_address) -{ - bootm_announce_and_cleanup(); - -#ifdef CONFIG_SYS_COREBOOT - timestamp_add_now(TS_U_BOOT_START_KERNEL); -#endif - /* - * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params - * structure, and then jump to the kernel. We assume that %cs is - * 0x10, 4GB flat, and read/execute, and the data segments are 0x18, - * 4GB flat, and read/write. U-boot is setting them up that way for - * itself in arch/i386/cpu/cpu.c. - */ - __asm__ __volatile__ ( - "movl $0, %%ebp\n" - "cli\n" - "jmp *%[kernel_entry]\n" - :: [kernel_entry]"a"(load_address), - [boot_params] "S"(setup_base), - "b"(0), "D"(0) - ); -} - void setup_pcat_compatibility(void) __attribute__((weak, alias("__setup_pcat_compatibility"))); @@ -296,7 +272,7 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { struct boot_params *base_ptr; void *bzImage_addr = NULL; - void *load_address; + ulong load_address; char *s; ulong bzImage_size = 0; ulong initrd_addr = 0; @@ -331,20 +307,17 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address); if (!base_ptr) { - printf("## Kernel loading failed ...\n"); + puts("## Kernel loading failed ...\n"); return -1; } if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET, 0, initrd_addr, initrd_size)) { - printf("Setting up boot parameters failed ...\n"); + puts("Setting up boot parameters failed ...\n"); return -1; } /* we assume that the kernel is in place */ - boot_zimage(base_ptr, load_address); - /* does not return */ - - return -1; + return boot_linux_kernel((ulong)base_ptr, load_address, false); } U_BOOT_CMD( |
