diff options
Diffstat (limited to 'arch')
25 files changed, 3 insertions, 3388 deletions
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 57324b6174..7b520f8dca 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -29,12 +29,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o START-y = start.o -RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += resetvec.o start16.o +START-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o COBJS = interrupts.o cpu.o timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START-y) $(RESET_OBJS-)) +START := $(addprefix $(obj),$(START-y)) all: $(obj).depend $(START) $(LIB) diff --git a/arch/x86/cpu/sc520/Makefile b/arch/x86/cpu/sc520/Makefile deleted file mode 100644 index f462264b8d..0000000000 --- a/arch/x86/cpu/sc520/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -# -# (C) Copyright 2008 -# Graeme Russ, graeme.russ@gmail.com. -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(SOC).o - -COBJS-$(CONFIG_SYS_SC520) += sc520.o -COBJS-$(CONFIG_PCI) += sc520_pci.o -COBJS-$(CONFIG_SYS_SC520_RESET) += sc520_reset.o -COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o -COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o -COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o - -SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -#########################################################################
\ No newline at end of file diff --git a/arch/x86/cpu/sc520/asm-offsets.c b/arch/x86/cpu/sc520/asm-offsets.c deleted file mode 100644 index 794f00cdb9..0000000000 --- a/arch/x86/cpu/sc520/asm-offsets.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include <common.h> -#include <asm/arch/sc520.h> - -#include <linux/kbuild.h> - -int main(void) -{ - DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off)); - - DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0])); - DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1])); - DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2])); - DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3])); - DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4])); - DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5])); - DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6])); - DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7])); - DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8])); - DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9])); - DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10])); - DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11])); - DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12])); - DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13])); - DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14])); - DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15])); - - return 0; -} diff --git a/arch/x86/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c deleted file mode 100644 index 3fe85e7648..0000000000 --- a/arch/x86/cpu/sc520/sc520.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2008-2011 - * Graeme Russ, <graeme.russ@gmail.com> - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor-flags.h> -#include <asm/arch/sc520.h> - -DECLARE_GLOBAL_DATA_PTR; - -sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE; - -int cpu_init_f(void) -{ - if (CONFIG_SYS_SC520_HIGH_SPEED) { - /* set it to 133 MHz and write back */ - writeb(0x02, &sc520_mmcr->cpuctl); - gd->cpu_clk = 133000000; - } else { - /* set it to 100 MHz and write back */ - writeb(0x01, &sc520_mmcr->cpuctl); - gd->cpu_clk = 100000000; - } - - /* wait at least one millisecond */ - asm("movl $0x2000, %%ecx\n" - "0: pushl %%ecx\n" - "popl %%ecx\n" - "loop 0b\n" : : : "ecx"); - - return x86_cpu_init_f(); -} - -int cpu_init_r(void) -{ - /* Disable the PAR used for CAR */ - writel(0x0000000, &sc520_mmcr->par[2]); - - /* turn on the SDRAM write buffer */ - writeb(0x11, &sc520_mmcr->dbctl); - - return x86_cpu_init_r(); -} diff --git a/arch/x86/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S deleted file mode 100644 index c04cc1f116..0000000000 --- a/arch/x86/cpu/sc520/sc520_car.S +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2010-2011 - * Graeme Russ, <graeme.russ@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/processor-flags.h> -#include <asm/arch/sc520.h> -#include <generated/asm-offsets.h> - -.section .text - -.globl car_init -car_init: - /* - * How to enable Cache-As-RAM for the AMD Elan SC520: - * 1. Turn off the CPU Cache (may not be strictly required) - * 2. Set code execution PAR (usually the BOOTCS region) to be - * non-cachable - * 3. Create a Cachable PAR Region for an area of memory which is - * a) NOT where the code is being executed - * b) NOT SDRAM (Controller not initialised yet) - * c) WILL response to read requests - * The easiest way to do this is to create a second BOOTCS - * PAR mappnig with an address != the PAR in step 2 - * 4. Issue a wbinvd to invalidate the CPU cache - * 5. Turn on the CPU Cache - * 6. Read 16kB from the cached PAR region setup in step 3 - * 7. Turn off the CPU Cache (but DO NOT issue a wbinvd) - * - * The following code uses PAR2 as the cached PAR (PAR0 and PAR1 - * are avoided as these are the only two PARs which can be used - * as PCI BUS Memory regions which the board might require) - * - * The configuration of PAR2 must be set in the board configuration - * file as CONFIG_SYS_SC520_CAR_PAR - */ - - /* Configure Cache-As-RAM PAR */ - movl $CONFIG_SYS_SC520_CAR_PAR, %eax - movl $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi - movl %eax, (%edi) - - /* Trash the cache then turn it on */ - wbinvd - movl %cr0, %eax - andl $~(X86_CR0_NW | X86_CR0_CD), %eax - movl %eax, %cr0 - - /* - * The cache is now enabled and empty. Map a region of memory to - * it by reading that region. - */ - movl $CONFIG_SYS_CAR_ADDR, %esi - movl $CONFIG_SYS_CAR_SIZE, %ecx - shrl $2, %ecx /* we are reading longs */ - cld - rep lodsl - - /* Turn off the cache, but don't trash it */ - movl %cr0, %eax - orl $(X86_CR0_NW | X86_CR0_CD), %eax - movl %eax, %cr0 - - /* Clear the CAR region */ - xorl %eax, %eax - movl $CONFIG_SYS_CAR_ADDR, %edi - movl $CONFIG_SYS_CAR_SIZE, %ecx - shrl $2, %ecx /* we are writing longs */ - rep stosl - - /* - * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of - * Cache-As-RAM - */ - jmp car_init_ret diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c deleted file mode 100644 index 52d07c119a..0000000000 --- a/arch/x86/cpu/sc520/sc520_pci.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2008-2011 - * Graeme Russ, <graeme.russ@gmail.com> - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <pci.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pci.h> -#include <asm/arch/sc520.h> - -static struct { - u8 priority; - u16 level_reg; - u8 level_bit; -} sc520_irq[] = { - { SC520_IRQ0, 0, 0x01 }, - { SC520_IRQ1, 0, 0x02 }, - { SC520_IRQ2, 1, 0x02 }, - { SC520_IRQ3, 0, 0x08 }, - { SC520_IRQ4, 0, 0x10 }, - { SC520_IRQ5, 0, 0x20 }, - { SC520_IRQ6, 0, 0x40 }, - { SC520_IRQ7, 0, 0x80 }, - - { SC520_IRQ8, 1, 0x01 }, - { SC520_IRQ9, 1, 0x02 }, - { SC520_IRQ10, 1, 0x04 }, - { SC520_IRQ11, 1, 0x08 }, - { SC520_IRQ12, 1, 0x10 }, - { SC520_IRQ13, 1, 0x20 }, - { SC520_IRQ14, 1, 0x40 }, - { SC520_IRQ15, 1, 0x80 } -}; - -/* The interrupt used for PCI INTA-INTD */ -int sc520_pci_ints[15] = { - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1 -}; - -/* utility function to configure a pci interrupt */ -int pci_sc520_set_irq(int pci_pin, int irq) -{ - int i; - u8 tmpb; - u16 tmpw; - - debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); - - if (irq < 0 || irq > 15) - return -1; /* illegal irq */ - - if (pci_pin < 0 || pci_pin > 15) - return -1; /* illegal pci int pin */ - - /* first disable any non-pci interrupt source that use - * this level */ - - /* PCI interrupt mapping (A through D)*/ - for (i = 0; i <= 3 ; i++) { - tmpb = readb(&sc520_mmcr->pci_int_map[i]); - - if (tmpb == sc520_irq[irq].priority) - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]); - } - - /* GP IRQ interrupt mapping */ - for (i = 0; i <= 10 ; i++) { - tmpb = readb(&sc520_mmcr->gp_int_map[i]); - - if (tmpb == sc520_irq[irq].priority) - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]); - } - - /* Set the trigger to level */ - tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]); - tmpb |= sc520_irq[irq].level_bit; - writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]); - - - if (pci_pin < 4) { - /* PCI INTA-INTD */ - /* route the interrupt */ - writeb(sc520_irq[irq].priority, - &sc520_mmcr->pci_int_map[pci_pin]); - } else { - /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - writeb(sc520_irq[irq].priority, - &sc520_mmcr->gp_int_map[pci_pin - 4]); - - /* also set the polarity in this case */ - tmpw = readw(&sc520_mmcr->intpinpol); - tmpw |= (1 << (pci_pin-4)); - writew(tmpw, &sc520_mmcr->intpinpol); - } - - /* register the pin */ - sc520_pci_ints[pci_pin] = irq; - - - return 0; /* OK */ -} - -void pci_sc520_init(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - hose->region_count = pci_set_regions(hose); - - pci_setup_type1(hose); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - /* enable target memory acceses on host brige */ - pci_write_config_word(0, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); -} diff --git a/arch/x86/cpu/sc520/sc520_reset.c b/arch/x86/cpu/sc520/sc520_reset.c deleted file mode 100644 index 137af978c1..0000000000 --- a/arch/x86/cpu/sc520/sc520_reset.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2011 - * Graeme Russ, <graeme.russ@gmail.com> - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sc520.h> - -DECLARE_GLOBAL_DATA_PTR; - -void reset_cpu(ulong addr) -{ - printf("Resetting using SC520 MMCR\n"); - /* Write a '1' to the SYS_RST of the RESCFG MMCR */ - writeb(0x01, &sc520_mmcr->rescfg); - - /* NOTREACHED */ -} diff --git a/arch/x86/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c deleted file mode 100644 index 9dc13342e3..0000000000 --- a/arch/x86/cpu/sc520/sc520_sdram.c +++ /dev/null @@ -1,479 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * Graeme Russ, <graeme.russ@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor-flags.h> -#include <asm/arch/sc520.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct sc520_sdram_info { - u8 banks; - u8 columns; - u8 rows; - u8 size; -}; - -static void sc520_sizemem(void); -static void sc520_set_dram_timing(void); -static void sc520_set_dram_refresh_rate(void); -static void sc520_enable_dram_refresh(void); -static void sc520_enable_sdram(void); - -int dram_init_f(void) -{ - sc520_sizemem(); - sc520_set_dram_timing(); - sc520_set_dram_refresh_rate(); - sc520_enable_dram_refresh(); - sc520_enable_sdram(); - - return 0; -} - -static inline void sc520_dummy_write(void) -{ - writew(0x0000, CACHELINESZ); -} -static inline void sc520_issue_sdram_op_mode_select(u8 command) -{ - writeb(command, &sc520_mmcr->drcctl); - sc520_dummy_write(); -} - -static inline int check_long(u32 test_long) -{ - u8 i; - u8 tmp_byte = (u8)(test_long & 0x000000ff); - - for (i = 1; i < 4; i++) { - if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte) - return -1; - } - - return 0; -} - -static inline int write_and_test(u32 data, u32 address) -{ - writel(data, address); - if (readl(address) == data) - return 0; /* Good */ - else - return -1; /* Bad */ -} - -static void sc520_enable_sdram(void) -{ - u32 par_config; - - /* Enable Writes, Caching and Code Execution to SDRAM */ - par_config = readl(&sc520_mmcr->par[3]); - par_config &= ~(SC520_PAR_EXEC_DIS | - SC520_PAR_CACHE_DIS | - SC520_PAR_WRITE_DIS); - writel(par_config, &sc520_mmcr->par[3]); - - par_config = readl(&sc520_mmcr->par[4]); - par_config &= ~(SC520_PAR_EXEC_DIS | - SC520_PAR_CACHE_DIS | - SC520_PAR_WRITE_DIS); - writel(par_config, &sc520_mmcr->par[4]); -} - -static void sc520_set_dram_timing(void) -{ - u8 drctmctl = 0x00; - -#if defined CONFIG_SYS_SDRAM_DRCTMCTL - /* just have your hardware designer _GIVE_ you what you need here! */ - drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL; -#else - switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) { - case 2: - break; - case 3: - drctmctl |= 0x01; - break; - case 4: - default: - drctmctl |= 0x02; - break; - } - - switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) { - case 2: - break; - case 3: - drctmctl |= 0x04; - break; - case 4: - default: - drctmctl |= 0x08; - break; - - case 6: - drctmctl |= 0x0c; - break; - } - - switch (CONFIG_SYS_SDRAM_CAS_LATENCY) { - case 2: - break; - case 3: - default: - drctmctl |= 0x10; - break; - } -#endif - writeb(drctmctl, &sc520_mmcr->drctmctl); - - /* Issue load mode register command */ - sc520_issue_sdram_op_mode_select(0x03); -} - -static void sc520_set_dram_refresh_rate(void) -{ - u8 drctl; - - drctl = readb(&sc520_mmcr->drcctl); - drctl &= 0xcf; - - switch (CONFIG_SYS_SDRAM_REFRESH_RATE) { - case 78: - break; - case 156: - default: - drctl |= 0x10; - break; - case 312: - drctl |= 0x20; - break; - case 624: - drctl |= 0x30; - break; - } - - writeb(drctl, &sc520_mmcr->drcctl); -} - -static void sc520_enable_dram_refresh(void) -{ - u8 drctl; - - drctl = readb(&sc520_mmcr->drcctl); - drctl &= 0x30; /* keep refresh rate */ - drctl |= 0x08; /* enable refresh, normal mode */ - - writeb(drctl, &sc520_mmcr->drcctl); -} - -static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info) -{ - u32 col_data; - u32 row_data; - - u32 drcbendadr; - u16 drccfg; - - u8 banks = 0x00; - u8 columns = 0x00; - u8 rows = 0x00; - - bank_info->banks = 0x00; - bank_info->columns = 0x00; - bank_info->rows = 0x00; - bank_info->size = 0x00; - - if ((bank < 0) || (bank > 3)) { - printf("Bad Bank ID\n"); - return; - } - - /* Save configuration */ - drcbendadr = readl(&sc520_mmcr->drcbendadr); - drccfg = readw(&sc520_mmcr->drccfg); - - /* Setup SDRAM Bank to largest possible size */ - writew(0x000b << (bank * 4), &sc520_mmcr->drccfg); - - /* Set ending address for this bank */ - writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr); - - /* write col 11 wrap adr */ - if (write_and_test(COL11_DATA, COL11_ADR) != 0) - goto restore_and_exit; - - /* write col 10 wrap adr */ - if (write_and_test(COL10_DATA, COL10_ADR) != 0) - goto restore_and_exit; - - /* write col 9 wrap adr */ - if (write_and_test(COL09_DATA, COL09_ADR) != 0) - goto restore_and_exit; - - /* write col 8 wrap adr */ - if (write_and_test(COL08_DATA, COL08_ADR) != 0) - goto restore_and_exit; - - col_data = readl(COL11_ADR); - - /* All four bytes in the read long must be the same */ - if (check_long(col_data) < 0) - goto restore_and_exit; - - if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA)) - columns = (u8)(col_data & 0x000000ff); - else - goto restore_and_exit; - - /* write row 14 wrap adr */ - if (write_and_test(ROW14_DATA, ROW14_ADR) != 0) - goto restore_and_exit; - - /* write row 13 wrap adr */ - if (write_and_test(ROW13_DATA, ROW13_ADR) != 0) - goto restore_and_exit; - - /* write row 12 wrap adr */ - if (write_and_test(ROW12_DATA, ROW12_ADR) != 0) - goto restore_and_exit; - - /* write row 11 wrap adr */ - if (write_and_test(ROW11_DATA, ROW11_ADR) != 0) - goto restore_and_exit; - - if (write_and_test(ROW10_DATA, ROW10_ADR) != 0) - goto restore_and_exit; - - /* - * read data @ row 12 wrap adr to determine number of banks, - * and read data @ row 14 wrap adr to determine number of rows. - * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. - * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 - * if data @ row 12 wrap == 11 or 12, we have 4 banks, - */ - row_data = readl(ROW12_ADR); - - /* All four bytes in the read long must be the same */ - if (check_long(row_data) != 0) - goto restore_and_exit; - - switch (row_data) { - case ROW10_DATA: - banks = 2; - break; - - case ROW11_DATA: - case ROW12_DATA: - banks = 4; - break; - - default: - goto restore_and_exit; - } - - row_data = readl(ROW14_ADR); - - /* All four bytes in the read long must be the same */ - if (check_long(row_data) != 0) - goto restore_and_exit; - - switch (row_data) { - case ROW11_DATA: - case ROW12_DATA: - case ROW13_DATA: - case ROW14_DATA: - rows = (u8)(row_data & 0x000000ff); - break; - - default: - goto restore_and_exit; - } - - bank_info->banks = banks; - bank_info->columns = columns; - bank_info->rows = rows; - - if ((bank_info->banks != 0) && - (bank_info->columns != 0) && - (bank_info->rows != 0)) { - bank_info->size = bank_info->rows; - bank_info->size >>= (11 - bank_info->columns); - bank_info->size++; - } - -restore_and_exit: - /* Restore configuration */ - writel(drcbendadr, &sc520_mmcr->drcbendadr); - writew(drccfg, &sc520_mmcr->drccfg); -} - -static void sc520_setup_sizemem(void) -{ - u8 i; - - /* Disable write buffer */ - writeb(0x00, &sc520_mmcr->dbctl); - - /* Disable ECC */ - writeb(0x00, &sc520_mmcr->eccctl); - - /* Set slowest SDRAM timing */ - writeb(0x1e, &sc520_mmcr->drctmctl); - - /* Issue a NOP to all SDRAM banks */ - sc520_issue_sdram_op_mode_select(0x01); - - /* Delay for 100 microseconds */ - udelay(100); - - /* Issue 'All Banks Precharge' command */ - sc520_issue_sdram_op_mode_select(0x02); - - /* Issue 2 'Auto Refresh Enable' command */ - sc520_issue_sdram_op_mode_select(0x04); - sc520_dummy_write(); - - /* Issue 'Load Mode Register' command */ - sc520_issue_sdram_op_mode_select(0x03); - - /* Issue 8 more 'Auto Refresh Enable' commands */ - sc520_issue_sdram_op_mode_select(0x04); - for (i = 0; i < 7; i++) - sc520_dummy_write(); - - /* Set control register to 'Normal Mode' */ - writeb(0x00, &sc520_mmcr->drcctl); -} - -static void sc520_sizemem(void) -{ - struct sc520_sdram_info sdram_info[4]; - u8 bank_config = 0x00; - u8 end_addr = 0x00; - u16 drccfg = 0x0000; - u32 drcbendadr = 0x00000000; - u8 i; - - /* Use PARs to disable caching of maximum allowable 256MB SDRAM */ - writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]); - writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]); - - sc520_setup_sizemem(); - - gd->ram_size = 0; - - /* Size each SDRAM bank */ - for (i = 0; i <= 3; i++) { - sc520_get_bank_info(i, &sdram_info[i]); - - if (sdram_info[i].banks != 0) { - /* Update Configuration register */ - bank_config = sdram_info[i].columns - 8; - - if (sdram_info[i].banks == 4) - bank_config |= 0x08; - - drccfg |= bank_config << (i * 4); - - /* Update End Address register */ - end_addr += sdram_info[i].size; - drcbendadr |= (end_addr | 0x80) << (i * 8); - - gd->ram_size += sdram_info[i].size << 22; - } - - /* Issue 'All Banks Precharge' command */ - sc520_issue_sdram_op_mode_select(0x02); - - /* Set control register to 'Normal Mode' */ - writeb(0x00, &sc520_mmcr->drcctl); - } - - writel(drcbendadr, &sc520_mmcr->drcbendadr); - writew(drccfg, &sc520_mmcr->drccfg); - - /* Clear PARs preventing caching of SDRAM */ - writel(0x00000000, &sc520_mmcr->par[3]); - writel(0x00000000, &sc520_mmcr->par[4]); -} - -int dram_init(void) -{ - ulong dram_ctrl; - ulong dram_present = 0x00000000; - - /* - * We read-back the configuration of the dram - * controller that the assembly code wrote - */ - dram_ctrl = readl(&sc520_mmcr->drcbendadr); - - gd->bd->bi_dram[0].start = 0; - if (dram_ctrl & 0x80) { - /* bank 0 enabled */ - gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; - dram_present = gd->bd->bi_dram[1].start; - gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start; - } else { - gd->bd->bi_dram[0].size = 0; - gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start; - } - - if (dram_ctrl & 0x8000) { - /* bank 1 enabled */ - gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14; - dram_present = gd->bd->bi_dram[2].start; - gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start - - gd->bd->bi_dram[1].start; - } else { - gd->bd->bi_dram[1].size = 0; - gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start; - } - - if (dram_ctrl & 0x800000) { - /* bank 2 enabled */ - gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6; - dram_present = gd->bd->bi_dram[3].start; - gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start - - gd->bd->bi_dram[2].start; - } else { - gd->bd->bi_dram[2].size = 0; - gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start; - } - - if (dram_ctrl & 0x80000000) { - /* bank 3 enabled */ - dram_present = (dram_ctrl & 0x7f000000) >> 2; - gd->bd->bi_dram[3].size = dram_present - - gd->bd->bi_dram[3].start; - } else { - gd->bd->bi_dram[3].size = 0; - } - - gd->ram_size = dram_present; - - return 0; -} diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c deleted file mode 100644 index cc601e56e4..0000000000 --- a/arch/x86/cpu/sc520/sc520_ssi.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/ssi.h> -#include <asm/arch/sc520.h> - -int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) -{ - u8 temp = 0; - - if (freq >= 8192) - temp |= CTL_CLK_SEL_4; - else if (freq >= 4096) - temp |= CTL_CLK_SEL_8; - else if (freq >= 2048) - temp |= CTL_CLK_SEL_16; - else if (freq >= 1024) - temp |= CTL_CLK_SEL_32; - else if (freq >= 512) - temp |= CTL_CLK_SEL_64; - else if (freq >= 256) - temp |= CTL_CLK_SEL_128; - else if (freq >= 128) - temp |= CTL_CLK_SEL_256; - else - temp |= CTL_CLK_SEL_512; - - if (!lsb_first) - temp |= MSBF_ENB; - - if (inv_clock) - temp |= CLK_INV_ENB; - - if (inv_phase) - temp |= PHS_INV_ENB; - - writeb(temp, &sc520_mmcr->ssictl); - - return 0; -} - -u8 ssi_txrx_byte(u8 data) -{ - writeb(data, &sc520_mmcr->ssixmit); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) - ; - writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) - ; - - return readb(&sc520_mmcr->ssircv); -} - -void ssi_tx_byte(u8 data) -{ - writeb(data, &sc520_mmcr->ssixmit); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) - ; - writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd); -} - -u8 ssi_rx_byte(void) -{ - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) - ; - writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) - ; - - return readb(&sc520_mmcr->ssircv); -} diff --git a/arch/x86/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c deleted file mode 100644 index 41f121f86f..0000000000 --- a/arch/x86/cpu/sc520/sc520_timer.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2008-2011 - * Graeme Russ, <graeme.russ@gmail.com> - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/interrupt.h> -#include <asm/arch/sc520.h> - -void sc520_timer_isr(void) -{ - /* Ack the GP Timer Interrupt */ - writeb(0x02, &sc520_mmcr->gptmrsta); -} - -int timer_init(void) -{ - /* Register the SC520 specific timer interrupt handler */ - register_timer_isr(sc520_timer_isr); - - /* Install interrupt handler for GP Timer 1 */ - irq_install_handler (0, timer_isr, NULL); - - /* Map GP Timer 1 to Master PIC IR0 */ - writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]); - - /* Disable GP Timers 1 & 2 - Allow configuration writes */ - writew(0x4000, &sc520_mmcr->gptmr1ctl); - writew(0x4000, &sc520_mmcr->gptmr2ctl); - - /* Reset GP Timers 1 & 2 */ - writew(0x0000, &sc520_mmcr->gptmr1cnt); - writew(0x0000, &sc520_mmcr->gptmr2cnt); - - /* Setup GP Timer 2 as a 100kHz (10us) prescaler */ - writew(83, &sc520_mmcr->gptmr2maxcmpa); - writew(0xc001, &sc520_mmcr->gptmr2ctl); - - /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */ - writew(100, &sc520_mmcr->gptmr1maxcmpa); - writew(0xe009, &sc520_mmcr->gptmr1ctl); - - unmask_irq(0); - - /* Clear the GP Timer 1 status register to get the show rolling*/ - writeb(0x02, &sc520_mmcr->gptmrsta); - - return 0; -} - -/* Allow boards to override udelay implementation */ -void __udelay(unsigned long usec) - __attribute__((weak, alias("sc520_udelay"))); - -void sc520_udelay(unsigned long usec) -{ - int m = 0; - long u; - - readw(&sc520_mmcr->swtmrmilli); - readw(&sc520_mmcr->swtmrmicro); - - do { - m += readw(&sc520_mmcr->swtmrmilli); - u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000); - } while (u < usec); -} diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index 0c6f0e31d8..2313cd793a 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -86,7 +86,7 @@ SECTIONS __bios_start = LOADADDR(.bios); __bios_size = SIZEOF(.bios); -#ifndef CONFIG_X86_NO_RESET_VECTOR +#ifdef CONFIG_X86_RESET_VECTOR /* * The following expressions place the 16-bit Real-Mode code and diff --git a/arch/x86/include/asm/arch-sc520/pci.h b/arch/x86/include/asm/arch-sc520/pci.h deleted file mode 100644 index 12ba656ff0..0000000000 --- a/arch/x86/include/asm/arch-sc520/pci.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_IC_SC520_PCI_H_ -#define _ASM_IC_SC520_PCI_H_ 1 - -/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ -#define SC520_REG_ADDR 0x00000cf8 -#define SC520_REG_DATA 0x00000cfc - -#define SC520_ISA_MEM_PHYS 0x00000000 -#define SC520_ISA_MEM_BUS 0x00000000 -#define SC520_ISA_MEM_SIZE 0x01000000 - -#define SC520_ISA_IO_PHYS 0x00000000 -#define SC520_ISA_IO_BUS 0x00000000 -#define SC520_ISA_IO_SIZE 0x00001000 - -/* PCI I/O space from 0x1000 to 0xdfff - * (make 0xe000-0xfdff available for stuff like PCCard boot) */ -#define SC520_PCI_IO_PHYS 0x00001000 -#define SC520_PCI_IO_BUS 0x00001000 -#define SC520_PCI_IO_SIZE 0x0000d000 - -/* system memory from 0x00000000 to 0x0fffffff */ -#define SC520_PCI_MEMORY_PHYS 0x00000000 -#define SC520_PCI_MEMORY_BUS 0x00000000 -#define SC520_PCI_MEMORY_SIZE 0x10000000 - -/* PCI bus memory from 0x10000000 to 0x26ffffff - * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ -#define SC520_PCI_MEM_PHYS 0x10000000 -#define SC520_PCI_MEM_BUS 0x10000000 -#define SC520_PCI_MEM_SIZE 0x17000000 - -/* pin number used for PCI interrupt mappings */ -#define SC520_PCI_INTA 0 -#define SC520_PCI_INTB 1 -#define SC520_PCI_INTC 2 -#define SC520_PCI_INTD 3 -#define SC520_PCI_GPIRQ0 4 -#define SC520_PCI_GPIRQ1 5 -#define SC520_PCI_GPIRQ2 6 -#define SC520_PCI_GPIRQ3 7 -#define SC520_PCI_GPIRQ4 8 -#define SC520_PCI_GPIRQ5 9 -#define SC520_PCI_GPIRQ6 10 -#define SC520_PCI_GPIRQ7 11 -#define SC520_PCI_GPIRQ8 12 -#define SC520_PCI_GPIRQ9 13 -#define SC520_PCI_GPIRQ10 14 - -extern int sc520_pci_ints[]; - -void pci_sc520_init(struct pci_controller *hose); -int pci_set_regions(struct pci_controller *hose); -int pci_sc520_set_irq(int pci_pin, int irq); - -#endif diff --git a/arch/x86/include/asm/arch-sc520/sc520.h b/arch/x86/include/asm/arch-sc520/sc520.h deleted file mode 100644 index 9dc29d39bc..0000000000 --- a/arch/x86/include/asm/arch-sc520/sc520.h +++ /dev/null @@ -1,372 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_IC_SC520_H_ -#define _ASM_IC_SC520_H_ 1 - -#ifndef __ASSEMBLY__ - -void init_sc520(void); -unsigned long init_sc520_dram(void); -void sc520_udelay(unsigned long usec); - -/* Memory mapped configuration registers */ -typedef struct sc520_mmcr { - u16 revid; /* ElanSC520 microcontroller revision id */ - u8 cpuctl; /* am5x86 CPU control */ - - u8 pad_0x003[0x0d]; - - u8 drcctl; /* SDRAM control */ - u8 pad_0x011[0x01]; - u8 drctmctl; /* SDRAM timing control */ - u8 pad_0x013[0x01]; - u16 drccfg; /* SDRAM bank configuration*/ - u8 pad_0x016[0x02]; - u32 drcbendadr; /* SDRAM bank 0-3 ending address*/ - u8 pad_0x01c[0x04]; - u8 eccctl; /* ECC control */ - u8 eccsta; /* ECC status */ - u8 eccckbpos; /* ECC check bit position */ - u8 ecccktest; /* ECC Check Code Test */ - u32 eccsbadd; /* ECC single-bit error address */ - u32 eccmbadd; /* ECC multi-bit error address */ - - u8 pad_0x02c[0x14]; - - u8 dbctl; /* SDRAM buffer control */ - - u8 pad_0x041[0x0f]; - - u16 bootcsctl; /* /BOOTCS control */ - u8 pad_0x052[0x02]; - u16 romcs1ctl; /* /ROMCS1 control */ - u16 romcs2ctl; /* /ROMCS2 control */ - - u8 pad_0x058[0x08]; - - u16 hbctl; /* host bridge control */ - u16 hbtgtirqctl; /* host bridge target interrupt control */ - u16 hbtgtirqsta; /* host bridge target interrupt status */ - u16 hbmstirqctl; /* host bridge target interrupt control */ - u16 hbmstirqsta; /* host bridge master interrupt status */ - u8 pad_0x06a[0x02]; - u32 mstintadd; /* host bridge master interrupt address */ - - u8 sysarbctl; /* system arbiter control */ - u8 pciarbsta; /* PCI bus arbiter status */ - u16 sysarbmenb; /* system arbiter master enable */ - u32 arbprictl; /* arbiter priority control */ - - u8 pad_0x078[0x08]; - - u8 adddecctl; /* address decode control */ - u8 pad_0x081[0x01]; - u16 wpvsta; /* write-protect violation status */ - u8 pad_0x084[0x04]; - u32 par[16]; /* programmable address regions */ - - u8 pad_0x0c8[0x0b38]; - - u8 gpecho; /* GP echo mode */ - u8 gpcsdw; /* GP chip select data width */ - u16 gpcsqual; /* GP chip select qualification */ - u8 pad_0xc04[0x4]; - u8 gpcsrt; /* GP chip select recovery time */ - u8 gpcspw; /* GP chip select pulse width */ - u8 gpcsoff; /* GP chip select offset */ - u8 gprdw; /* GP read pulse width */ - u8 gprdoff; /* GP read offset */ - u8 gpwrw; /* GP write pulse width */ - u8 gpwroff; /* GP write offset */ - u8 gpalew; /* GP ale pulse width */ - u8 gpaleoff; /* GP ale offset */ - - u8 pad_0xc11[0x0f]; - - u16 piopfs15_0; /* PIO15-PIO0 pin function select */ - u16 piopfs31_16; /* PIO31-PIO16 pin function select */ - u8 cspfs; /* chip select pin function select */ - u8 pad_0xc25[0x01]; - u8 clksel; /* clock select */ - u8 pad_0xc27[0x01]; - u16 dsctl; /* drive strength control */ - u16 piodir15_0; /* PIO15-PIO0 direction */ - u16 piodir31_16; /* PIO31-PIO16 direction */ - u8 pad_0xc2e[0x02]; - u16 piodata15_0 ; /* PIO15-PIO0 data */ - u16 piodata31_16; /* PIO31-PIO16 data */ - u16 pioset15_0; /* PIO15-PIO0 set */ - u16 pioset31_16; /* PIO31-PIO16 set */ - u16 pioclr15_0; /* PIO15-PIO0 clear */ - u16 pioclr31_16; /* PIO31-PIO16 clear */ - - u8 pad_0xc3c[0x24]; - - u16 swtmrmilli; /* software timer millisecond count */ - u16 swtmrmicro; /* software timer microsecond count */ - u8 swtmrcfg; /* software timer configuration */ - - u8 pad_0xc65[0x0b]; - - u8 gptmrsta; /* GP timers status register */ - u8 pad_0xc71; - u16 gptmr0ctl; /* GP timer 0 mode/control */ - u16 gptmr0cnt; /* GP timer 0 count */ - u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */ - u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */ - u16 gptmr1ctl; /* GP timer 1 mode/control */ - u16 gptmr1cnt; /* GP timer 1 count */ - u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */ - u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/ - u16 gptmr2ctl; /* GP timer 2 mode/control */ - u16 gptmr2cnt; /* GP timer 2 count */ - u8 pad_0xc86[0x08]; - u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */ - - u8 pad_0xc90[0x20]; - - u16 wdtmrctl; /* watchdog timer control */ - u16 wdtmrcntl; /* watchdog timer count low */ - u16 wdtmrcnth; /* watchdog timer count high */ - - u8 pad_0xcb6[0x0a]; - - u8 uart1ctl; /* UART 1 general control */ - u8 uart1sta; /* UART 1 general status */ - u8 uart1fcrshad; /* UART 1 FIFO control shadow */ - u8 pad_0xcc3[0x01]; - u8 uart2ctl; /* UART 2 general control */ - u8 uart2sta; /* UART 2 general status */ - u8 uart2fcrshad; /* UART 2 FIFO control shadow */ - - u8 pad_0xcc7[0x09]; - - u8 ssictl; /* SSI control */ - u8 ssixmit; /* SSI transmit */ - u8 ssicmd; /* SSI command */ - u8 ssista; /* SSI status */ - u8 ssircv; /* SSI receive */ - - u8 pad_0xcd5[0x2b]; - - u8 picicr; /* interrupt control */ - u8 pad_0xd01[0x01]; - u8 pic_mode[3]; /* PIC interrupt mode */ - u8 pad_0xd05[0x03]; - u16 swint16_1; /* software interrupt 16-1 control */ - u8 swint22_17; /* software interrupt 22-17/NMI control */ - u8 pad_0xd0b[0x05]; - u16 intpinpol; /* interrupt pin polarity */ - u8 pad_0xd12[0x02]; - u16 pcihostmap; /* PCI host bridge interrupt mapping */ - u8 pad_0xd16[0x02]; - u16 eccmap; /* ECC interrupt mapping */ - u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */ - u8 pad_0xd1d[0x03]; - u8 pit_int_map[3]; /* PIT interrupt mapping */ - u8 pad_0xd23[0x05]; - u8 uart_int_map[2]; /* UART interrupt mapping */ - u8 pad_0xd2a[0x06]; - u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/ - u8 pad_0xd34[0x0c]; - u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */ - u8 ssimap; /* SSI interrupt mapping register */ - u8 wdtmap; /* watchdog timer interrupt mapping */ - u8 rtcmap; /* RTC interrupt mapping register */ - u8 wpvmap; /* write-protect interrupt mapping */ - u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */ - u8 ferrmap; /* floating point error interrupt mapping */ - u8 pad_0xd47[0x09]; - u8 gp_int_map[11]; /* GP IRQ interrupt mapping */ - - u8 pad_0xd5b[0x15]; - - u8 sysinfo; /* system board information */ - u8 pad_0xd71[0x01]; - u8 rescfg; /* reset configuration */ - u8 pad_0xd73[0x01]; - u8 ressta; /* reset status */ - - u8 pad_0xd75[0x0b]; - - u8 gpdmactl; /* GP-DMA Control */ - u8 gpdmammio; /* GP-DMA memory-mapped I/O */ - u16 gpdmaextchmapa; /* GP-DMA resource channel map a */ - u16 gpdmaextchmapb; /* GP-DMA resource channel map b */ - u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */ - u8 pad_0xd8d[0x03]; - u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */ - u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */ - u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */ - u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */ - u8 pad_0xd94[0x4]; - u8 gpdmabcctl; /* buffer chaining control */ - u8 gpdmabcsta; /* buffer chaining status */ - u8 gpdmabsintenb; /* buffer chaining interrupt enable */ - u8 gpdmabcval; /* buffer chaining valid */ - u8 pad_0xd9c[0x04]; - u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */ - u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */ - u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */ - u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */ - u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */ - u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */ - u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */ - u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */ - u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */ - u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */ - u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */ - u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */ - u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */ - u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */ - u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */ - u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */ - - u8 pad_0xdc0[0x0240]; -} sc520_mmcr_t; - -extern sc520_mmcr_t *sc520_mmcr; - -#endif - -/* Memory Mapped Control Registers (MMCR) Base Address */ -#define SC520_MMCR_BASE 0xfffef000 - -/* - * PARs for maximum allowable 256MB of SDRAM @ 0x00000000 - * Two PARs are required due to maximum PAR size of 128MB - * These are used in the SDRAM sizing code to disable caching - * - * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000 - * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800 - * \ / | | | | \----+----/ \-----+------/ - * | | | | | | +---------- Start at 0x00000000 - * | | | | | | 0x08000000 - * | | | | | +----------------------- 128MB Region Size - * | | | | | ((2047 + 1) * 64kB) - * | | | | +------------------------------ 64kB Page Size - * | | | +-------------------------------- Writes Enabled - * | | +---------------------------------- Caching Enabled - * | +------------------------------------ Execution Enabled - * +--------------------------------------- SDRAM - */ -#define SC520_SDRAM1_PAR 0xe3ffc000 -#define SC520_SDRAM2_PAR 0xe3ffc800 - -#define SC520_PAR_WRITE_DIS 0x04000000 -#define SC520_PAR_CACHE_DIS 0x08000000 -#define SC520_PAR_EXEC_DIS 0x10000000 - -/* - * Programmable Address Regions to cover 256MB SDRAM (Maximum supported) - * required for DRAM sizing code - */ - -/* MMCR Register bits (not all of them :) ) */ - -/* SSI Stuff */ -#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ -#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ -#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ -#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ -#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ -#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ -#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ -#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */ - -#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ -#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ -#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ -#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */ - -#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ -#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ -#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ -#define SSISTA_BSY 0x02 /* SSI Busy */ -#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ - -/* BITS for SC520_ADDDECCTL: */ -#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ -#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ -#define RTC_DIS 0x04 /* RTC Disable */ -#define UART2_DIS 0x02 /* UART2 Disable */ -#define UART1_DIS 0x01 /* UART1 Disable */ - -/* - * Defines used for SDRAM Sizing (number of columns and rows) - * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the - * Elan SC520 Microcontroller User's Manual (Order #22004B) - */ -#define CACHELINESZ 0x00000010 - -#define COL11_ADR 0x0e001e00 -#define COL10_ADR 0x0e000e00 -#define COL09_ADR 0x0e000600 -#define COL08_ADR 0x0e000200 -#define COL11_DATA 0x0b0b0b0b -#define COL10_DATA 0x0a0a0a0a -#define COL09_DATA 0x09090909 -#define COL08_DATA 0x08080808 - -#define ROW14_ADR 0x0f000000 -#define ROW13_ADR 0x07000000 -#define ROW12_ADR 0x03000000 -#define ROW11_ADR 0x01000000 -#define ROW10_ADR 0x00000000 -#define ROW14_DATA 0x3f3f3f3f -#define ROW13_DATA 0x1f1f1f1f -#define ROW12_DATA 0x0f0f0f0f -#define ROW11_DATA 0x07070707 -#define ROW10_DATA 0xaaaaaaaa - -/* 0x28000000 - 0x3fffffff is used by the flash banks */ - -/* 0x40000000 - 0xffffffff is not adressable by the SC520 */ - -/* priority numbers used for interrupt channel mappings */ -#define SC520_IRQ_DISABLED 0 -#define SC520_IRQ0 1 -#define SC520_IRQ1 2 -#define SC520_IRQ2 4 /* same as IRQ9 */ -#define SC520_IRQ3 11 -#define SC520_IRQ4 12 -#define SC520_IRQ5 13 -#define SC520_IRQ6 21 -#define SC520_IRQ7 22 -#define SC520_IRQ8 3 -#define SC520_IRQ9 4 -#define SC520_IRQ10 5 -#define SC520_IRQ11 6 -#define SC520_IRQ12 7 -#define SC520_IRQ13 8 -#define SC520_IRQ14 9 -#define SC520_IRQ15 10 - -#endif diff --git a/arch/x86/include/asm/arch-sc520/ssi.h b/arch/x86/include/asm/arch-sc520/ssi.h deleted file mode 100644 index bd48eab161..0000000000 --- a/arch/x86/include/asm/arch-sc520/ssi.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2008 - * Graeme Russ <graeme.russ@gmail.com>. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_IC_SSI_H_ -#define _ASM_IC_SSI_H_ 1 - -int ssi_set_interface(int, int, int, int); -void ssi_chip_select(int); -u8 ssi_txrx_byte(u8); -void ssi_tx_byte(u8); -u8 ssi_rx_byte(void); - - -#endif diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h deleted file mode 100644 index 0f12a893b4..0000000000 --- a/arch/x86/include/asm/realmode.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_REALMODE_H_ -#define __ASM_REALMODE_H_ -#include <asm/ptrace.h> - -extern ulong __realmode_start; -extern ulong __realmode_size; -extern char realmode_enter; - -int bios_setup(void); -int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out); -int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out); - -#endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 0a52cc896c..9b24dc5fdf 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -25,16 +25,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o -ifeq ($(CONFIG_X86_NO_REAL_MODE),) -SOBJS-$(CONFIG_SYS_PC_BIOS) += bios.o -SOBJS-$(CONFIG_SYS_PCI_BIOS) += bios_pci.o -COBJS-y += realmode.o -SOBJS-y += realmode_switch.o - -COBJS-$(CONFIG_SYS_PC_BIOS) += bios_setup.o -COBJS-$(CONFIG_VIDEO_VGA) += video_bios.o -endif - COBJS-y += board.o COBJS-y += bootm.o COBJS-y += cmd_boot.o diff --git a/arch/x86/lib/bios.S b/arch/x86/lib/bios.S deleted file mode 100644 index 239aaa9cfa..0000000000 --- a/arch/x86/lib/bios.S +++ /dev/null @@ -1,569 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Based on msbios.c from rolo 1.6: - *---------------------------------------------------------------------- - * (C) Copyright 2000 - * Sysgo Real-Time Solutions GmbH - * Klein-Winternheim, Germany - *---------------------------------------------------------------------- - */ - -#include "bios.h" - -/* - * During it's initialization phase, before switching to protected - * mode, the Linux Kernel makes a few BIOS calls. This won't work - * if the board does not have a BIOS. - * - * This is a very minimalisic BIOS that supplies just enough - * functionality to keep the Linux Kernel happy. It is NOT - * a general purpose replacement for a real BIOS !! - */ - -.section .bios, "ax" -.code16 -.org 0 - /* a call to f000:0 should warmboot */ - jmp realmode_reset - -.globl rm_int00 -.hidden rm_int00 -.type rm_int00, @function -rm_int00: - pushw $0 - jmp any_interrupt16 -.globl rm_int01 -.hidden rm_int01 -.type rm_int01, @function -rm_int01: - pushw $1 - jmp any_interrupt16 -.globl rm_int02 -.hidden rm_int02 -.type rm_int02, @function -rm_int02: - pushw $2 - jmp any_interrupt16 -.globl rm_int03 -.hidden rm_int03 -.type rm_int03, @function -rm_int03: - pushw $3 - jmp any_interrupt16 -.globl rm_int04 -.hidden rm_int04 -.type rm_int04, @function -rm_int04: - pushw $4 - jmp any_interrupt16 -.globl rm_int05 -.hidden rm_int05 -.type rm_int05, @function -rm_int05: - pushw $5 - jmp any_interrupt16 -.globl rm_int06 -.hidden rm_int06 -.type rm_int06, @function -rm_int06: - pushw $6 - jmp any_interrupt16 -.globl rm_int07 -.hidden rm_int07 -.type rm_int07, @function -rm_int07: - pushw $7 - jmp any_interrupt16 -.globl rm_int08 -.hidden rm_int08 -.type rm_int08, @function -rm_int08: - pushw $8 - jmp any_interrupt16 -.globl rm_int09 -.hidden rm_int09 -.type rm_int09, @function -rm_int09: - pushw $9 - jmp any_interrupt16 -.globl rm_int0a -.hidden rm_int0a -.type rm_int0a, @function -rm_int0a: - pushw $10 - jmp any_interrupt16 -.globl rm_int0b -.hidden rm_int0b -.type rm_int0b, @function -rm_int0b: - pushw $11 - jmp any_interrupt16 -.globl rm_int0c -.hidden rm_int0c -.type rm_int0c, @function -rm_int0c: - pushw $12 - jmp any_interrupt16 -.globl rm_int0d -.hidden rm_int0d -.type rm_int0d, @function -rm_int0d: - pushw $13 - jmp any_interrupt16 -.globl rm_int0e -.hidden rm_int0e -.type rm_int0e, @function -rm_int0e: - pushw $14 - jmp any_interrupt16 -.globl rm_int0f -.hidden rm_int0f -.type rm_int0f, @function -rm_int0f: - pushw $15 - jmp any_interrupt16 -.globl rm_int10 -.hidden rm_int10 -.type rm_int10, @function -rm_int10: - pushw $16 - jmp any_interrupt16 -.globl rm_int11 -.hidden rm_int11 -.type rm_int11, @function -rm_int11: - pushw $17 - jmp any_interrupt16 -.globl rm_int12 -.hidden rm_int12 -.type rm_int12, @function -rm_int12: - pushw $18 - jmp any_interrupt16 -.globl rm_int13 -.hidden rm_int13 -.type rm_int13, @function -rm_int13: - pushw $19 - jmp any_interrupt16 -.globl rm_int14 -.hidden rm_int14 -.type rm_int14, @function -rm_int14: - pushw $20 - jmp any_interrupt16 -.globl rm_int15 -.hidden rm_int15 -.type rm_int15, @function -rm_int15: - pushw $21 - jmp any_interrupt16 -.globl rm_int16 -.hidden rm_int16 -.type rm_int16, @function -rm_int16: - pushw $22 - jmp any_interrupt16 -.globl rm_int17 -.hidden rm_int17 -.type rm_int17, @function -rm_int17: - pushw $23 - jmp any_interrupt16 -.globl rm_int18 -.hidden rm_int18 -.type rm_int18, @function -rm_int18: - pushw $24 - jmp any_interrupt16 -.globl rm_int19 -.hidden rm_int19 -.type rm_int19, @function -rm_int19: - pushw $25 - jmp any_interrupt16 -.globl rm_int1a -.hidden rm_int1a -.type rm_int1a, @function -rm_int1a: - pushw $26 - jmp any_interrupt16 -.globl rm_int1b -.hidden rm_int1b -.type rm_int1b, @function -rm_int1b: - pushw $27 - jmp any_interrupt16 -.globl rm_int1c -.hidden rm_int1c -.type rm_int1c, @function -rm_int1c: - pushw $28 - jmp any_interrupt16 -.globl rm_int1d -.hidden rm_int1d -.type rm_int1d, @function -rm_int1d: - pushw $29 - jmp any_interrupt16 -.globl rm_int1e -.hidden rm_int1e -.type rm_int1e, @function -rm_int1e: - pushw $30 - jmp any_interrupt16 -.globl rm_int1f -.hidden rm_int1f -.type rm_int1f, @function -rm_int1f: - pushw $31 - jmp any_interrupt16 -.globl rm_def_int -.hidden rm_def_int -.type rm_def_int, @function -rm_def_int: - iret - - /* - * All interrupt jumptable entries jump to here after pushing the - * interrupt vector number onto the stack. - */ -any_interrupt16: - MAKE_BIOS_STACK - -gs movw OFFS_VECTOR(%bp), %ax - cmpw $0x10, %ax - je Lint_10h - cmpw $0x11, %ax - je Lint_11h - cmpw $0x12, %ax - je Lint_12h - cmpw $0x13, %ax - je Lint_13h - cmpw $0x15, %ax - je Lint_15h - cmpw $0x16, %ax - je Lint_16h - cmpw $0x1a, %ax - je Lint_1ah - movw $0xffff, %ax - jmp Lout -Lint_10h: - /* VGA BIOS services */ - call bios_10h - jmp Lout -Lint_11h: - call bios_11h - jmp Lout -Lint_12h: - call bios_12h - jmp Lout -Lint_13h: - /* BIOS disk services */ - call bios_13h - jmp Lout -Lint_15h: - /* Misc. BIOS services */ - call bios_15h - jmp Lout -Lint_16h: - /* keyboard services */ - call bios_16h - jmp Lout -Lint_1ah: - /* PCI bios */ - call bios_1ah - jmp Lout -Lout: - cmpw $0, %ax - je Lhandeled - - /* - * Insert code for unhandeled INTs here. - * - * ROLO prints a message to the console we could do that but then - * we're in 16bit mode so we'll have to get back into 32bit mode - * to use the console I/O routines (if we do this we should make - * int 0x10 and int 0x16 work as well) - */ -Lhandeled: - RESTORE_CALLERS_STACK - - /* dump vector number */ - addw $2,%sp - - /* return from interrupt */ - iret - -/* - ************************************************************ - * BIOS interrupt 10h -- VGA services - ************************************************************ - */ -bios_10h: -gs movw OFFS_AX(%bp), %ax - shrw $8, %ax - cmpw $0x3, %ax - je Lcur_pos - cmpw $0xf, %ax - je Lvid_state - cmpw $0x12, %ax - je Lvid_cfg - movw $0xffff, %ax - ret -Lcur_pos: - /* Read Cursor Position and Size */ -gs movw $0, OFFS_CX(%bp) -gs movw $0, OFFS_DX(%bp) - xorw %ax, %ax - ret -Lvid_state: - /* Get Video State - 80 columns, 80x25, 16 colors */ -gs movw $(80 << 8|0x03), OFFS_AX(%bp) -gs movw $0, OFFS_BX(%bp) - xorw %ax, %ax - ret -Lvid_cfg: - /* Video Subsystem Configuration (EGA/VGA) - indicate CGA/MDA/HGA */ -gs movw $0x10, OFFS_BX(%bp) - xorw %ax, %ax - ret - -/* - ************************************************************ - * BIOS interrupt 11h -- Equipment determination - ************************************************************ - */ - -bios_11h: -cs movw bios_equipment, %ax -gs movw %ax, OFFS_AX(%bp) - xorw %ax, %ax - ret - -/* - ************************************************************ - * BIOS interrupt 12h -- Get Memory Size - ************************************************************ - */ -bios_12h: -cs movw ram_in_64kb_chunks, %ax - cmpw $0xa, %ax - ja b12_more_than_640k - shlw $6, %ax - jmp b12_return -b12_more_than_640k: - movw $0x280, %ax -b12_return: - /* return number of kilobytes in ax */ -gs movw %ax, OFFS_AX(%bp) - -gs movw OFFS_FLAGS(%bp), %ax - - /* clear carry -- function succeeded */ - andw $0xfffe, %ax -gs movw %ax, OFFS_FLAGS(%bp) - - xorw %ax, %ax - ret - -/* - ************************************************************ - * BIOS interrupt 13h -- Disk services - ************************************************************ - */ -bios_13h: -gs movw OFFS_AX(%bp), %ax - shrw $8, %ax - cmpw $0x15, %ax - je Lfunc_15h - movw $0xffff, %ax - ret -Lfunc_15h: -gs movw OFFS_AX(%bp), %ax - - /* return AH=0->drive not present */ - andw $0x00ff, %ax -gs movw %ax, OFFS_AX(%bp) - xorw %ax, %ax - ret - -/* - *********************************************************** - * BIOS interrupt 15h -- Miscellaneous services - *********************************************************** - */ -bios_15h: -gs movw OFFS_AX(%bp), %ax - shrw $8, %ax - cmpw $0xc0, %ax - je Lfunc_c0h - cmpw $0xe8, %ax - je Lfunc_e8h - cmpw $0x88, %ax - je Lfunc_88h - movw $0xffff, %ax - ret - -Lfunc_c0h: - /* Return System Configuration Parameters (PS2 only) */ -gs movw OFFS_FLAGS(%bp), %ax - - /* return carry -- function not supported */ - orw $1, %ax -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax - ret - -Lfunc_e8h: -gs movw OFFS_AX(%bp), %ax - andw $0xff, %ax - cmpw $1, %ax - je Lfunc_e801h -gs movw OFFS_FLAGS(%bp), %ax - - /* return carry -- function not supported */ - orw $1, %ax -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax - ret - -Lfunc_e801h: - /* Get memory size for >64M Configurations */ -cs movw ram_in_64kb_chunks, %ax - cmpw $0x100, %ax - ja e801_more_than_16mb - - /* multiply by 64 */ - shlw $6, %ax - - /* 1st meg does not count */ - subw $0x400, %ax - - /* return memory size between 1M and 16M in 1kb chunks in AX and CX */ -gs movw %ax, OFFS_AX(%bp) -gs movw %ax, OFFS_CX(%bp) - - /* set BX and DX to 0*/ -gs movw $0, OFFS_BX(%bp) -gs movw $0, OFFS_DX(%bp) -gs movw OFFS_FLAGS(%bp), %ax - - /* clear carry -- function succeeded */ - andw $0xfffe, %ax -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax - ret - -e801_more_than_16mb: - /* subtract 16MB */ - subw $0x100, %ax - - /* return 0x3c00 (16MB-1MB) in AX and CX */ -gs movw $0x3c00, OFFS_AX(%bp) -gs movw $0x3c00, OFFS_CX(%bp) - - /* set BX and DX to number of 64kb chunks above 16MB */ -gs movw %ax, OFFS_BX(%bp) -gs movw %ax, OFFS_DX(%bp) - -gs movw OFFS_FLAGS(%bp), %ax - - /* clear carry -- function succeeded */ - andw $0xfffe, %ax -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax - ret - -Lfunc_88h: -cs movw ram_in_64kb_chunks, %ax - cmpw $0x100, %ax - jna b88_not_more_than16 - movw $0x100, %ax -b88_not_more_than16: - shlw $6, %ax - - /* 1st meg does not count */ - subw $0x400, %ax - - /* return number of kilobytes between 16MB and 16MB in ax */ -gs movw %ax, OFFS_AX(%bp) - -gs movw OFFS_FLAGS(%bp), %ax - - /* clear carry -- function succeeded */ - andw $0xfffe, %ax -gs movw %ax, OFFS_FLAGS(%bp) - - xorw %ax, %ax - ret - -/* - ************************************************************ - * BIOS interrupt 16h -- keyboard services - ************************************************************ - */ -bios_16h: -gs movw OFFS_AX(%bp), %ax - shrw $8, %ax - cmpw $0x03, %ax - je Lfunc_03h - movw $0xffff, %ax - ret -Lfunc_03h: - /* do nothing -- function not supported */ - xorw %ax, %ax - ret - -/* - ************************************************************ - * BIOS interrupt 1ah -- PCI bios - ************************************************************ - */ -bios_1ah: -gs movw OFFS_AX(%bp), %ax - cmpb $0xb1, %ah - je Lfunc_b1h - movw $0xffff, %ax - ret -Lfunc_b1h: - call realmode_pci_bios - - /* do nothing -- function not supported */ - xorw %ax, %ax - ret - - -.globl ram_in_64kb_chunks -.hidden ram_in_64kb_chunks -.type ram_in_64kb_chunks, @function -ram_in_64kb_chunks: - .word 0 - -.globl bios_equipment -.hidden bios_equipment -.type bios_equipment, @function -bios_equipment: - .word 0 diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h index a220983df1..96509b066e 100644 --- a/arch/x86/lib/bios.h +++ b/arch/x86/lib/bios.h @@ -145,9 +145,6 @@ extern void *rm_int1e; extern void *rm_int1f; extern void *rm_def_int; -extern void *realmode_reset; -extern void *realmode_pci_bios_call_entry; - #define RELOC_16_LONG(seg, off) (*(u32 *)(seg << 4 | (u32)&off)) #define RELOC_16_WORD(seg, off) (*(u16 *)(seg << 4 | (u32)&off)) #define RELOC_16_BYTE(seg, off) (*(u8 *)(seg << 4 | (u32)&off)) diff --git a/arch/x86/lib/bios_pci.S b/arch/x86/lib/bios_pci.S deleted file mode 100644 index 47c478b27d..0000000000 --- a/arch/x86/lib/bios_pci.S +++ /dev/null @@ -1,447 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * x86 realmode assembly implementation of a PCI BIOS - * for platforms that use one PCI hose and configuration - * access type 1. (The common case for low-end PC's) - */ - -#include "bios.h" - -#define PCI_BIOS_DEBUG - -.section .bios, "ax" -.code16 -.globl realmode_pci_bios_call_entry -.hidden realmode_pci_bios_call_entry -.type realmode_pci_bios_call_entry, @function -realmode_pci_bios_call_entry: - MAKE_BIOS_STACK - call realmode_pci_bios - RESTORE_CALLERS_STACK - ret - - -.globl realmode_pci_bios -realmode_pci_bios: -gs movw OFFS_AX(%bp), %ax - cmpb $1, %al - je pci_bios_present - cmpb $2, %al - je pci_bios_find_device - cmpb $3, %al - je pci_bios_find_class - cmpb $6, %al - je pci_bios_generate_special_cycle - cmpb $8, %al - je pci_bios_read_cfg_byte - cmpb $9, %al - je pci_bios_read_cfg_word - cmpb $10, %al - je pci_bios_read_cfg_dword - cmpb $11, %al - je pci_bios_write_cfg_byte - cmpb $12, %al - je pci_bios_write_cfg_word - cmpb $13, %al - je pci_bios_write_cfg_dword - cmpb $14, %al - je pci_bios_get_irq_routing - cmpb $15, %al - je pci_bios_set_irq - jmp unknown_function - -/*****************************************************************************/ - -pci_bios_present: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_present -#endif - movl $0x20494350, %eax -gs movl %eax, OFFS_EDX(%bp) - - /* We support cfg type 1 version 2.10 */ - movb $0x01, %al -gs movb %al, OFFS_AL(%bp) - movw $0x0210, %ax -gs movw %ax, OFFS_BX(%bp) - - /* last bus number */ -cs movb pci_last_bus, %al -gs movb %al, OFFS_CL(%bp) - jmp clear_carry - -/*****************************************************************************/ - -/* device 0-31, function 0-7 */ -pci_bios_find_device: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_find_device -#endif -gs movw OFFS_CX(%bp), %di - shll $16, %edi -gs movw OFFS_DX(%bp), %di - /* edi now holds device in upper 16 bits and vendor in lower 16 bits */ - -gs movw OFFS_SI(%bp), %si - - /* start at bus 0 dev 0 function 0 */ - xorw %bx, %bx -pfd_loop: - /* dword 0 is vendor/device */ - xorw %ax, %ax - call __pci_bios_select_register - movw $0xcfc, %dx - inl %dx, %eax - - /* our device ? */ - cmpl %edi, %eax - je pfd_found_one -pfd_next_dev: - /* check for multi function devices */ - movw %bx, %ax - andw $3, %ax - jnz pfd_function_not_zero - movw $0x000c, %ax - call __pci_bios_select_register - movw $0xcfe, %dx - inb %dx, %al - andb $0x80, %al - jz pfd_not_multi_function -pfd_function_not_zero: - /* next function, overflows in to device number, then bus number */ - incw %bx - jmp pfd_check_bus - -pfd_not_multi_function: - /* remove function bits */ - andw $0xfff8, %bx - - /* next device, overflows in to bus number */ - addw $0x0008, %bx -pfd_check_bus: -cs movb pci_last_bus, %ah - cmpb %ah, %bh - ja pfd_not_found - jmp pfd_loop -pfd_found_one: - decw %si - js pfd_done - jmp pfd_next_dev - -pfd_done: -gs movw %bx, OFFS_BX(%bp) - jmp clear_carry - -pfd_not_found: - /* device not found */ - movb $0x86, %ah - jmp set_carry - -/*****************************************************************************/ - -pci_bios_find_class: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_find_class -#endif -gs movl OFFS_ECX(%bp), %edi - - /* edi now holds class-code in lower 24 bits */ - andl $0x00ffffff, %edi -gs movw OFFS_SI(%bp), %si - - /* start at bus 0 dev 0 function 0 */ - xorw %bx, %bx -pfc_loop: - /* dword 8 is class-code high 24bits */ - movw $8, %ax - call __pci_bios_select_register - movw $0xcfc, %dx - inl %dx, %eax - shrl $8, %eax - andl $0x00ffffff, %eax - - /* our device ? */ - cmpl %edi, %eax - je pfc_found_one -pfc_next_dev: - /* check for multi function devices */ - andw $3, %bx - jnz pfc_function_not_zero - movw $0x000c, %ax - call __pci_bios_select_register - movw $0xcfe, %dx - inb %dx, %al - andb $0x80, %al - jz pfc_not_multi_function -pfc_function_not_zero: - /* next function, overflows in to device number, then bus number */ - incw %bx - jmp pfc_check_bus - -pfc_not_multi_function: - /* remove function bits */ - andw $0xfff8, %bx - - /* next device, overflows in to bus number */ - addw $0x0008, %bx -pfc_check_bus: -cs movb pci_last_bus, %ah - cmpb %ah, %bh - ja pfc_not_found - jmp pfc_loop -pfc_found_one: - decw %si - js pfc_done - jmp pfc_next_dev - -pfc_done: -gs movw %bx, OFFS_BX(%bp) - jmp clear_carry - -pfc_not_found: - /* device not found */ - movb $0x86, %ah - jmp set_carry - -/*****************************************************************************/ - -pci_bios_generate_special_cycle: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_generate_special_cycle -#endif - /* function not supported */ - movb $0x81, %ah - jmp set_carry - -/*****************************************************************************/ - -pci_bios_read_cfg_byte: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_read_cfg_byte -#endif - call pci_bios_select_register -gs movw OFFS_DI(%bp), %dx - andw $3, %dx - addw $0xcfc, %dx - inb %dx, %al -gs movb %al, OFFS_CL(%bp) - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_read_cfg_word: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_read_cfg_word -#endif - call pci_bios_select_register -gs movw OFFS_DI(%bp), %dx - andw $2, %dx - addw $0xcfc, %dx - inw %dx, %ax -gs movw %ax, OFFS_CX(%bp) - jmp clear_carry - - -/*****************************************************************************/ - -pci_bios_read_cfg_dword: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_read_cfg_dword -#endif - call pci_bios_select_register - movw $0xcfc, %dx - inl %dx, %eax -gs movl %eax, OFFS_ECX(%bp) - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_write_cfg_byte: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_write_cfg_byte -#endif - call pci_bios_select_register -gs movw OFFS_DI(%bp), %dx -gs movb OFFS_CL(%bp), %al - andw $3, %dx - addw $0xcfc, %dx - outb %al, %dx - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_write_cfg_word: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_write_cfg_word -#endif - call pci_bios_select_register -gs movw OFFS_DI(%bp), %dx -gs movw OFFS_CX(%bp), %ax - andw $2, %dx - addw $0xcfc, %dx - outw %ax, %dx - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_write_cfg_dword: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_write_cfg_dword -#endif - call pci_bios_select_register -gs movl OFFS_ECX(%bp), %eax - movw $0xcfc, %dx - outl %eax, %dx - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_get_irq_routing: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_get_irq_routing -#endif - /* function not supported */ - movb $0x81, %ah - jmp set_carry - -/*****************************************************************************/ - -pci_bios_set_irq: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_set_irq -#endif - /* function not supported */ - movb $0x81, %ah - jmp set_carry - -/*****************************************************************************/ - -unknown_function: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_unknown_function -#endif - /* function not supported */ - movb $0x81, %ah - jmp set_carry - -/*****************************************************************************/ - -pci_bios_select_register: -gs movw OFFS_BX(%bp), %bx -gs movw OFFS_DI(%bp), %ax -/* destroys eax, dx */ -__pci_bios_select_register: - /* BX holds device id, AX holds register index */ - pushl %ebx - andl $0xfc, %eax - andl $0xffff, %ebx - shll $8, %ebx - orl %ebx, %eax - orl $0x80000000, %eax - movw $0xcf8, %dx - outl %eax, %dx - popl %ebx - ret - - -clear_carry: -gs movw OFFS_FLAGS(%bp), %ax - - /* clear carry -- function succeeded */ - andw $0xfffe, %ax -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax -gs movb %ah, OFFS_AH(%bp) - ret - -set_carry: -gs movb %ah, OFFS_AH(%bp) -gs movw OFFS_FLAGS(%bp), %ax - - /* return carry -- function not supported */ - orw $1, %ax -gs movw %ax, OFFS_FLAGS(%bp) - movw $-1, %ax - ret - -/*****************************************************************************/ - -.globl pci_last_bus -pci_last_bus: - .byte 0 - -#ifdef PCI_BIOS_DEBUG -.globl num_pci_bios_present -num_pci_bios_present: - .long 0 - -.globl num_pci_bios_find_device -num_pci_bios_find_device: - .long 0 - -.globl num_pci_bios_find_class -num_pci_bios_find_class: - .long 0 - -.globl num_pci_bios_generate_special_cycle -num_pci_bios_generate_special_cycle: - .long 0 - -.globl num_pci_bios_read_cfg_byte -num_pci_bios_read_cfg_byte: - .long 0 - -.globl num_pci_bios_read_cfg_word -num_pci_bios_read_cfg_word: - .long 0 - -.globl num_pci_bios_read_cfg_dword -num_pci_bios_read_cfg_dword: - .long 0 - -.globl num_pci_bios_write_cfg_byte -num_pci_bios_write_cfg_byte: - .long 0 - -.globl num_pci_bios_write_cfg_word -num_pci_bios_write_cfg_word: - .long 0 - -.globl num_pci_bios_write_cfg_dword -num_pci_bios_write_cfg_dword: - .long 0 - -.globl num_pci_bios_get_irq_routing -num_pci_bios_get_irq_routing: - .long 0 - -.globl num_pci_bios_set_irq -num_pci_bios_set_irq: - .long 0 - -.globl num_pci_bios_unknown_function -num_pci_bios_unknown_function: - .long 0 -#endif diff --git a/arch/x86/lib/bios_setup.c b/arch/x86/lib/bios_setup.c deleted file mode 100644 index 265f7d671e..0000000000 --- a/arch/x86/lib/bios_setup.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Partly based on msbios.c from rolo 1.6: - *---------------------------------------------------------------------- - * (C) Copyright 2000 - * Sysgo Real-Time Solutions GmbH - * Klein-Winternheim, Germany - *---------------------------------------------------------------------- - */ - -#include <common.h> -#include <pci.h> -#include <asm/realmode.h> -#include <asm/io.h> -#include "bios.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define NUMVECTS 256 - -static int set_jmp_vector(int entry_point, void *target) -{ - if (entry_point & ~0xffff) - return -1; - - if (((u32)target - 0xf0000) & ~0xffff) - return -1; - - printf("set_jmp_vector: 0xf000:%04x -> %p\n", - entry_point, target); - - /* jmp opcode */ - writeb(0xea, 0xf0000 + entry_point); - - /* offset */ - writew(((u32)target-0xf0000), 0xf0000 + entry_point + 1); - - /* segment */ - writew(0xf000, 0xf0000 + entry_point + 3); - - return 0; -} - -/* Install an interrupt vector */ -static void setvector(int vector, u16 segment, void *handler) -{ - u16 *ptr = (u16 *)(vector * 4); - ptr[0] = ((u32)handler - (segment << 4)) & 0xffff; - ptr[1] = segment; - -#if 0 - printf("setvector: int%02x -> %04x:%04x\n", - vector, ptr[1], ptr[0]); -#endif -} - -int bios_setup(void) -{ - /* The BIOS section is not relocated and still in the ROM. */ - ulong bios_start = (ulong)&__bios_start; - ulong bios_size = (ulong)&__bios_size; - - static int done; - int vector; -#ifdef CONFIG_PCI - struct pci_controller *pri_hose; -#endif - if (done) - return 0; - - done = 1; - - if (bios_size > 65536) { - printf("BIOS too large (%ld bytes, max is 65536)\n", - bios_size); - return -1; - } - - memcpy(BIOS_BASE, (void *)bios_start, bios_size); - - /* clear bda */ - memset(BIOS_DATA, 0, BIOS_DATA_SIZE); - - /* enter some values to the bda */ - writew(0x3f8, BIOS_DATA); /* com1 addr */ - writew(0x2f8, BIOS_DATA+2); /* com2 addr */ - writew(0x3e8, BIOS_DATA+4); /* com3 addr */ - writew(0x2e8, BIOS_DATA+6); /* com4 addr */ - writew(0x278, BIOS_DATA+8); /* lpt1 addr */ - /* - * The kernel wants to read the base memory size - * from 40:13. Put a zero there to avoid an error message - */ - writew(0, BIOS_DATA+0x13); /* base memory size */ - - - /* setup realmode interrupt vectors */ - for (vector = 0; vector < NUMVECTS; vector++) - setvector(vector, BIOS_CS, &rm_def_int); - - setvector(0x00, BIOS_CS, &rm_int00); - setvector(0x01, BIOS_CS, &rm_int01); - setvector(0x02, BIOS_CS, &rm_int02); - setvector(0x03, BIOS_CS, &rm_int03); - setvector(0x04, BIOS_CS, &rm_int04); - setvector(0x05, BIOS_CS, &rm_int05); - setvector(0x06, BIOS_CS, &rm_int06); - setvector(0x07, BIOS_CS, &rm_int07); - setvector(0x08, BIOS_CS, &rm_int08); - setvector(0x09, BIOS_CS, &rm_int09); - setvector(0x0a, BIOS_CS, &rm_int0a); - setvector(0x0b, BIOS_CS, &rm_int0b); - setvector(0x0c, BIOS_CS, &rm_int0c); - setvector(0x0d, BIOS_CS, &rm_int0d); - setvector(0x0e, BIOS_CS, &rm_int0e); - setvector(0x0f, BIOS_CS, &rm_int0f); - setvector(0x10, BIOS_CS, &rm_int10); - setvector(0x11, BIOS_CS, &rm_int11); - setvector(0x12, BIOS_CS, &rm_int12); - setvector(0x13, BIOS_CS, &rm_int13); - setvector(0x14, BIOS_CS, &rm_int14); - setvector(0x15, BIOS_CS, &rm_int15); - setvector(0x16, BIOS_CS, &rm_int16); - setvector(0x17, BIOS_CS, &rm_int17); - setvector(0x18, BIOS_CS, &rm_int18); - setvector(0x19, BIOS_CS, &rm_int19); - setvector(0x1a, BIOS_CS, &rm_int1a); - setvector(0x1b, BIOS_CS, &rm_int1b); - setvector(0x1c, BIOS_CS, &rm_int1c); - setvector(0x1d, BIOS_CS, &rm_int1d); - setvector(0x1e, BIOS_CS, &rm_int1e); - setvector(0x1f, BIOS_CS, &rm_int1f); - - set_jmp_vector(0xfff0, &realmode_reset); - set_jmp_vector(0xfe6e, &realmode_pci_bios_call_entry); - - /* fill in data area */ - RELOC_16_WORD(0xf000, ram_in_64kb_chunks) = gd->ram_size >> 16; - RELOC_16_WORD(0xf000, bios_equipment) = 0; /* FixMe */ - - /* If we assume only one PCI hose, this PCI hose - * will own PCI bus #0, and the last PCI bus of - * that PCI hose will be the last PCI bus in the - * system. - * (This, ofcause break on multi hose systems, - * but our PCI BIOS only support one hose anyway) - */ -#ifdef CONFIG_PCI - pri_hose = pci_bus_to_hose(0); - if (NULL != pri_hose) { - /* fill in last pci bus number for use by the realmode - * PCI BIOS */ - RELOC_16_BYTE(0xf000, pci_last_bus) = pri_hose->last_busno; - } -#endif - return 0; -} diff --git a/arch/x86/lib/realmode.c b/arch/x86/lib/realmode.c deleted file mode 100644 index 75511b2bdf..0000000000 --- a/arch/x86/lib/realmode.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/ptrace.h> -#include <asm/realmode.h> - -#define REALMODE_MAILBOX ((char *)0xe00) - -int realmode_setup(void) -{ - /* The realmode section is not relocated and still in the ROM. */ - ulong realmode_start = (ulong)&__realmode_start; - ulong realmode_size = (ulong)&__realmode_size; - - /* copy the realmode switch code */ - if (realmode_size > (REALMODE_MAILBOX - (char *)REALMODE_BASE)) { - printf("realmode switch too large (%ld bytes, max is %d)\n", - realmode_size, - (int)(REALMODE_MAILBOX - (char *)REALMODE_BASE)); - return -1; - } - - memcpy((char *)REALMODE_BASE, (void *)realmode_start, realmode_size); - asm("wbinvd\n"); - - return 0; -} - -int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out) -{ - - /* setup out thin bios emulation */ - if (bios_setup()) - return -1; - - if (realmode_setup()) - return -1; - - in->eip = off; - in->xcs = seg; - if ((in->esp & 0xffff) < 4) - printf("Warning: entering realmode with sp < 4 will fail\n"); - - memcpy(REALMODE_MAILBOX, in, sizeof(struct pt_regs)); - asm("wbinvd\n"); - - __asm__ volatile ( - "lcall $0x20,%0\n" : : "i" (&realmode_enter)); - - asm("wbinvd\n"); - memcpy(out, REALMODE_MAILBOX, sizeof(struct pt_regs)); - - return out->eax; -} - -/* - * This code is supposed to access a realmode interrupt - * it does currently not work for me - */ -int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out) -{ - /* place two instructions at 0x700 */ - writeb(0xcd, 0x700); /* int $lvl */ - writeb(lvl, 0x701); - writeb(0xcb, 0x702); /* lret */ - asm("wbinvd\n"); - - enter_realmode(0x00, 0x700, in, out); - - return out->eflags & 0x00000001; -} diff --git a/arch/x86/lib/realmode_switch.S b/arch/x86/lib/realmode_switch.S deleted file mode 100644 index c4c4c4378e..0000000000 --- a/arch/x86/lib/realmode_switch.S +++ /dev/null @@ -1,232 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* 32bit -> 16bit -> 32bit mode switch code */ - -/* - * Stack frame at 0xe00 - * e00 ebx; - * e04 ecx; - * e08 edx; - * e0c esi; - * e10 edi; - * e14 ebp; - * e18 eax; - * e1c ds; - * e20 es; - * e24 fs; - * e28 gs; - * e2c orig_eax; - * e30 eip; - * e34 cs; - * e38 eflags; - * e3c esp; - * e40 ss; - */ - -#define a32 .byte 0x67; /* address size prefix 32 */ -#define o32 .byte 0x66; /* operand size prefix 32 */ - -.section .realmode, "ax" -.code16 - - /* 16bit protected mode code here */ -.globl realmode_enter -realmode_enter: -o32 pusha -o32 pushf - cli - sidt saved_idt - sgdt saved_gdt - movl %esp, %eax - movl %eax, saved_protected_mode_esp - - movl $0x10, %eax - movl %eax, %esp - movw $0x28, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %fs - movw %ax, %gs - - lidt realmode_idt_ptr - /* Go back into real mode by clearing PE to 0 */ - movl %cr0, %eax - andl $0x7ffffffe, %eax - movl %eax, %cr0 - - /* switch to real mode */ - ljmp $0x0,$do_realmode - -do_realmode: - /* realmode code from here */ - movw %cs,%ax - movw %ax,%ds - movw %ax,%es - movw %ax,%fs - movw %ax,%gs - - /* create a temporary stack */ - movw $0xc0, %ax - movw %ax, %ss - movw $0x200, %ax - movw %ax, %sp - - popl %ebx - popl %ecx - popl %edx - popl %esi - popl %edi - popl %ebp - popl %eax - movl %eax, temp_eax - popl %eax - movw %ax, %ds - popl %eax - movw %ax, %es - popl %eax - movw %ax, %fs - popl %eax - movw %ax, %gs - popl %eax /* orig_eax */ - popl %eax -cs movw %ax, temp_ip - popl %eax -cs movw %ax, temp_cs -o32 popf - popl %eax - popw %ss - movl %eax, %esp -cs movl temp_eax, %eax - - /* self-modifying code, better flush the cache */ - wbinvd - - .byte 0x9a /* lcall */ -temp_ip: - .word 0 /* new ip */ -temp_cs: - .word 0 /* new cs */ - -realmode_ret: - /* save eax, esp and ss */ -cs movl %eax, saved_eax - movl %esp, %eax -cs movl %eax, saved_esp - movw %ss, %ax -cs movw %ax, saved_ss - - /* - * restore the stack, note that we set sp to 0x244; - * pt_regs is 0x44 bytes long and we push the structure - * backwards on to the stack, bottom first - */ - movw $0xc0, %ax - movw %ax, %ss - movw $0x244, %ax - movw %ax, %sp - - xorl %eax,%eax -cs movw saved_ss, %ax - pushl %eax -cs movl saved_esp, %eax - pushl %eax -o32 pushf - xorl %eax,%eax -cs movw temp_cs, %ax - pushl %eax -cs movw temp_ip, %ax - pushl %eax - pushl $0 - movw %gs, %ax - pushl %eax - movw %fs, %ax - pushl %eax - movw %es, %ax - pushl %eax - movw %ds, %ax - pushl %eax - movl saved_eax, %eax - pushl %eax - pushl %ebp - pushl %edi - pushl %esi - pushl %edx - pushl %ecx - pushl %ebx - -o32 cs lidt saved_idt -o32 cs lgdt saved_gdt - - /* Go back into protected mode reset PE to 1 */ - movl %cr0, %eax - orl $1,%eax - movl %eax, %cr0 - - /* flush prefetch queue */ - jmp next_line -next_line: - movw $return_ptr, %ax - movw %ax,%bp -o32 cs ljmp *(%bp) - -.code32 -protected_mode: - /* Reload segment registers */ - movl $0x18, %eax - movw %ax, %fs - movw %ax, %ds - movw %ax, %gs - movw %ax, %es - movw %ax, %ss - movl saved_protected_mode_esp, %eax - movl %eax, %esp - popf - popa - ret - -temp_eax: - .long 0 - -saved_ss: - .word 0 -saved_esp: - .long 0 -saved_eax: - .long 0 - -realmode_idt_ptr: - .word 0x400 - .word 0x0, 0x0 - -saved_gdt: - .word 0, 0, 0, 0 -saved_idt: - .word 0, 0, 0, 0 - -saved_protected_mode_esp: - .long 0 - -return_ptr: - .long protected_mode - .word 0x10 diff --git a/arch/x86/lib/video.c b/arch/x86/lib/video.c index 20e2416ae1..81824f3144 100644 --- a/arch/x86/lib/video.c +++ b/arch/x86/lib/video.c @@ -26,7 +26,6 @@ #include <stdio_dev.h> #include <i8042.h> #include <asm/ptrace.h> -#include <asm/realmode.h> #include <asm/io.h> #include <asm/pci.h> @@ -222,10 +221,5 @@ int video_init(void) int drv_video_init(void) { -#ifndef CONFIG_X86_NO_REAL_MODE - if (video_bios_init()) - return 1; -#endif - return video_init(); } diff --git a/arch/x86/lib/video_bios.c b/arch/x86/lib/video_bios.c deleted file mode 100644 index 1e06759d9e..0000000000 --- a/arch/x86/lib/video_bios.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <pci.h> -#include <malloc.h> -#include <asm/ptrace.h> -#include <asm/realmode.h> -#include <asm/io.h> -#include <asm/pci.h> -#include "bios.h" - -#undef PCI_BIOS_DEBUG -#undef VGA_BIOS_DEBUG - -#ifdef VGA_BIOS_DEBUG -#define PRINTF(fmt, args...) printf(fmt, ##args) -#else -#define PRINTF(fmt, args...) -#endif - -#define PCI_CLASS_VIDEO 3 -#define PCI_CLASS_VIDEO_STD 0 -#define PCI_CLASS_VIDEO_PROG_IF_VGA 0 - -DEFINE_PCI_DEVICE_TABLE(supported) = { - {PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID}, - {} -}; - -static u32 probe_pci_video(void) -{ - struct pci_controller *hose; - pci_dev_t devbusfn = pci_find_devices(supported, 0); - - if ((devbusfn != -1)) { - u32 old; - u32 addr; - - /* PCI video device detected */ - printf("Found PCI VGA device at %02x.%02x.%x\n", - PCI_BUS(devbusfn), - PCI_DEV(devbusfn), - PCI_FUNC(devbusfn)); - - /* Enable I/O decoding as well, PCI viudeo boards - * support I/O accesses, but they provide no - * bar register for this since the ports are fixed. - */ - pci_write_config_word(devbusfn, - PCI_COMMAND, - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | - PCI_COMMAND_MASTER); - - /* Test the ROM decoder, do the device support a rom? */ - pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old); - pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, - (u32)PCI_ROM_ADDRESS_MASK); - pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr); - pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old); - - if (!addr) { - printf("PCI VGA have no ROM?\n"); - return 0; - } - - /* device have a rom */ - if (pci_shadow_rom(devbusfn, (void *)0xc0000)) { - printf("Shadowing of PCI VGA BIOS failed\n"); - return 0; - } - - /* Now enable lagacy VGA port access */ - hose = pci_bus_to_hose(PCI_BUS(devbusfn)); - if (pci_enable_legacy_video_ports(hose)) { - printf("PCI VGA enable failed\n"); - return 0; - } - - - /* return the pci device info, that we'll need later */ - return PCI_BUS(devbusfn) << 8 | - PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn) & 7); - } - - return 0; -} - -static int probe_isa_video(void) -{ - u32 ptr; - char *buf; - - ptr = isa_map_rom(0xc0000, 0x8000); - - if (!ptr) - return -1; - - buf = malloc(0x8000); - if (!buf) { - isa_unmap_rom(ptr); - return -1; - } - - if (readw(ptr) != 0xaa55) { - free(buf); - isa_unmap_rom(ptr); - return -1; - } - - /* shadow the rom */ - memcpy(buf, (void *)ptr, 0x8000); - isa_unmap_rom(ptr); - memcpy((void *)0xc0000, buf, 0x8000); - - free(buf); - - return 0; -} - -int video_bios_init(void) -{ - struct pt_regs regs; - int size; - int i; - u8 sum; - - /* clear the video bios area in case we warmbooted */ - memset((void *)0xc0000, 0, 0x8000); - memset(®s, 0, sizeof(struct pt_regs)); - - if (probe_isa_video()) - /* No ISA board found, try the PCI bus */ - regs.eax = probe_pci_video(); - - /* Did we succeed in mapping any video bios */ - if (readw(0xc0000) == 0xaa55) { - PRINTF("Found video bios signature\n"); - size = readb(0xc0002) * 512; - PRINTF("size %d\n", size); - sum = 0; - - for (i = 0; i < size; i++) - sum += readb(0xc0000 + i); - - PRINTF("Checksum is %sOK\n", sum ? "NOT " : ""); - - if (sum) - return 1; - - /* - * Some video bioses (ATI Mach64) seem to think that - * the original int 10 handler is always at - * 0xf000:0xf065 , place an iret instruction there - */ - writeb(0xcf, 0xff065); - - regs.esp = 0x8000; - regs.xss = 0x2000; - enter_realmode(0xc000, 3, ®s, ®s); - - PRINTF("INT 0x10 vector after: %04x:%04x\n", - readw(0x42), readw(0x40)); - PRINTF("BIOS returned %scarry\n", - regs.eflags & 0x00000001 ? "" : "NOT "); -#ifdef PCI_BIOS_DEBUG - print_bios_bios_stat(); -#endif - return regs.eflags & 0x00000001; - - } - - return 1; - -} diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 46af391f29..4e9e1f77e5 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -33,7 +33,6 @@ #include <asm/io.h> #include <asm/ptrace.h> #include <asm/zimage.h> -#include <asm/realmode.h> #include <asm/byteorder.h> #include <asm/bootparam.h> #ifdef CONFIG_SYS_COREBOOT @@ -175,16 +174,9 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, else *load_address = (void *)ZIMAGE_LOAD_ADDR; -#if (defined CONFIG_ZBOOT_32 || defined CONFIG_X86_NO_REAL_MODE) printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base); memset(setup_base, 0, sizeof(*setup_base)); setup_base->hdr = params->hdr; -#else - /* load setup */ - printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n", - (ulong)setup_base, setup_size); - memmove(setup_base, image, setup_size); -#endif if (bootproto >= 0x0204) kernel_size = hdr->syssize * 16; @@ -241,10 +233,8 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, struct setup_header *hdr = &setup_base->hdr; int bootproto = get_boot_protocol(hdr); -#if (defined CONFIG_ZBOOT_32 || defined CONFIG_X86_NO_REAL_MODE) setup_base->e820_entries = install_e820_map( ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); -#endif if (bootproto == 0x0100) { setup_base->screen_info.cl_magic = COMMAND_LINE_MAGIC; @@ -300,7 +290,6 @@ void boot_zimage(void *setup_base, void *load_address) #ifdef CONFIG_SYS_COREBOOT timestamp_add_now(TS_U_BOOT_START_KERNEL); #endif -#if defined CONFIG_ZBOOT_32 /* * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params * structure, and then jump to the kernel. We assume that %cs is @@ -317,18 +306,6 @@ void boot_zimage(void *setup_base, void *load_address) "b"(0), "D"(0) : "%ebp" ); -#else - struct pt_regs regs; - - memset(®s, 0, sizeof(struct pt_regs)); - regs.xds = (u32)setup_base >> 4; - regs.xes = regs.xds; - regs.xss = regs.xds; - regs.esp = 0x9000; - regs.eflags = 0; - enter_realmode(((u32)setup_base + SETUP_START_OFFSET) >> 4, 0, - ®s, ®s); -#endif } void setup_pcat_compatibility(void) |
