diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arc/dts/.gitignore | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 65 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/board.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun4i.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c | 19 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 146 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/display.h | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/gpio.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/Kconfig | 25 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/include/mach/hardware.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/spl.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/timer.c | 83 | ||||
| -rw-r--r-- | arch/sandbox/Kconfig | 15 |
17 files changed, 99 insertions, 292 deletions
diff --git a/arch/arc/dts/.gitignore b/arch/arc/dts/.gitignore new file mode 100644 index 0000000000..b60ed208c7 --- /dev/null +++ b/arch/arc/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index df4d4739ff..1c6baa14b2 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1362,7 +1362,7 @@ int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, } clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK, (div & AUDIO_0_RATIO_MASK)); - } else if(i2s_id == 1) { + } else if (i2s_id == 1) { if (div > AUDIO_1_RATIO_MASK) { debug("%s: Frequency ratio is out of range\n", __func__); @@ -1579,45 +1579,49 @@ unsigned long get_pll_clk(int pllreg) if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos542x_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); - } else { + } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) return exynos4x12_get_pll_clk(pllreg); return exynos4_get_pll_clk(pllreg); } + + return 0; } unsigned long get_arm_clk(void) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { return exynos5_get_arm_clk(); - else { + } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) return exynos4x12_get_arm_clk(); return exynos4_get_arm_clk(); } + + return 0; } unsigned long get_i2c_clk(void) { - if (cpu_is_exynos5()) { + if (cpu_is_exynos5()) return clock_get_periph_rate(PERIPH_ID_I2C0); - } else if (cpu_is_exynos4()) { + else if (cpu_is_exynos4()) return exynos4_get_i2c_clk(); - } else { - debug("I2C clock is not set for this CPU\n"); - return 0; - } + + return 0; } unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { return clock_get_periph_rate(PERIPH_ID_PWM0); - } else { + } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) return exynos4x12_get_pwm_clk(); return exynos4_get_pwm_clk(); } + + return 0; } unsigned long get_uart_clk(int dev_index) @@ -1644,11 +1648,13 @@ unsigned long get_uart_clk(int dev_index) if (cpu_is_exynos5()) { return clock_get_periph_rate(id); - } else { + } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) return exynos4x12_get_uart_clk(dev_index); return exynos4_get_uart_clk(dev_index); } + + return 0; } unsigned long get_mmc_clk(int dev_index) @@ -1673,11 +1679,12 @@ unsigned long get_mmc_clk(int dev_index) return -1; } - if (cpu_is_exynos5()) { + if (cpu_is_exynos5()) return clock_get_periph_rate(id); - } else { + else if (cpu_is_exynos4()) return exynos4_get_mmc_clk(dev_index); - } + + return 0; } void set_mmc_clk(int dev_index, unsigned int div) @@ -1691,16 +1698,16 @@ void set_mmc_clk(int dev_index, unsigned int div) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); - } else { + } else if (cpu_is_exynos4()) { exynos4_set_mmc_clk(dev_index, div); } } unsigned long get_lcd_clk(void) { - if (cpu_is_exynos4()) + if (cpu_is_exynos4()) { return exynos4_get_lcd_clk(); - else { + } else if (cpu_is_exynos5()) { if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); else if (proid_is_exynos5800()) @@ -1708,13 +1715,15 @@ unsigned long get_lcd_clk(void) else return exynos5_get_lcd_clk(); } + + return 0; } void set_lcd_clk(void) { - if (cpu_is_exynos4()) + if (cpu_is_exynos4()) { exynos4_set_lcd_clk(); - else { + } else if (cpu_is_exynos5()) { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); else if (proid_is_exynos5420()) @@ -1736,9 +1745,9 @@ int set_spi_clk(int periph_id, unsigned int rate) if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); - } else { - return 0; } + + return 0; } int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, @@ -1746,22 +1755,22 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, { if (cpu_is_exynos5()) return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id); - else - return 0; + + return 0; } int set_i2s_clk_source(unsigned int i2s_id) { if (cpu_is_exynos5()) return exynos5_set_i2s_clk_source(i2s_id); - else - return 0; + + return 0; } int set_epll_clk(unsigned long rate) { if (cpu_is_exynos5()) return exynos5_set_epll_clk(rate); - else - return 0; + + return 0; } diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 6718ae2205..e6730c0dfa 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -68,6 +68,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c index c736fa3b47..f7b4915037 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c @@ -508,7 +508,7 @@ static void mctl_ddr3_initialize(void) /* * Perform impedance calibration on the DRAM controller side of the wire. */ -static void mctl_set_impedance(u32 zq, u32 odt_en) +static void mctl_set_impedance(u32 zq, bool odt_en) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; u32 reg_val; @@ -556,7 +556,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en) clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); /* Set I/O configure register */ - writel(DRAM_IOCR_ODT_EN(odt_en), &dram->iocr); + writel(DRAM_IOCR_ODT_EN, &dram->iocr); } static unsigned long dramc_init_helper(struct dram_para *para) diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c index 3d7964d1af..165c052122 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c @@ -26,12 +26,14 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> +#include <linux/kconfig.h> static const struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, .type = 3, .zq = CONFIG_DRAM_ZQ, - .odt_en = 1, + .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), + .odt_correction = CONFIG_DRAM_ODT_CORRECTION, .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ .mr0 = 6736, @@ -97,7 +99,6 @@ static void mctl_init(u32 *bus_width) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; struct sunxi_mctl_phy_reg * const mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - int correction; if (dram_para.tpr13 & 0x20) writel(0x40b, &mctl_phy->dcr); @@ -138,7 +139,7 @@ static void mctl_init(u32 *bus_width) writel(0x01000081, &mctl_phy->dtcr); - if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) { + if (dram_para.clock <= 240 || !dram_para.odt_en) { clrbits_le32(&mctl_phy->dx0gcr, 0x600); clrbits_le32(&mctl_phy->dx1gcr, 0x600); } @@ -251,13 +252,11 @@ static void mctl_init(u32 *bus_width) } else *bus_width = 16; - correction = (dram_para.odt_en >> 8) & 0xff; - if (correction) { - if (dram_para.odt_en & 0x80000000) - correction = -correction; - - mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction); - mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction); + if (dram_para.odt_correction) { + mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, + dram_para.odt_correction); + mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, + dram_para.odt_correction); } mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01); diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c index d03f00dc4b..ebba438319 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c @@ -14,12 +14,12 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> +#include <linux/kconfig.h> /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */ #define DRAM_CLK_MUL 2 #define DRAM_CLK_DIV 4 #define DRAM_SIGMA_DELTA_ENABLE 1 -#define DRAM_ODT_EN 0 struct dram_para { u8 cs1; @@ -195,7 +195,7 @@ static int mctl_train_dram(struct dram_para *para) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; mctl_data_train_cfg(para); - mctl_set_pir(0x1f3); + mctl_set_pir(0x5f3); return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; } @@ -215,7 +215,7 @@ static int mctl_channel_init(struct dram_para *para) clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0); /* Set ODT */ - if ((CONFIG_DRAM_CLK > 400) && DRAM_ODT_EN) { + if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) { setbits_le32(DXnGCR0(0), 0x3 << 9); setbits_le32(DXnGCR0(1), 0x3 << 9); } else { diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index a8122c1a67..ee547fbcee 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -348,152 +348,6 @@ struct ccsr_serdes { u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ }; -#define DDR_SDRAM_CFG 0x470c0008 -#define DDR_CS0_BNDS 0x008000bf -#define DDR_CS0_CONFIG 0x80014302 -#define DDR_TIMING_CFG_0 0x50550004 -#define DDR_TIMING_CFG_1 0xbcb38c56 -#define DDR_TIMING_CFG_2 0x0040d120 -#define DDR_TIMING_CFG_3 0x010e1000 -#define DDR_TIMING_CFG_4 0x00000001 -#define DDR_TIMING_CFG_5 0x03401400 -#define DDR_SDRAM_CFG_2 0x00401010 -#define DDR_SDRAM_MODE 0x00061c60 -#define DDR_SDRAM_MODE_2 0x00180000 -#define DDR_SDRAM_INTERVAL 0x18600618 -#define DDR_DDR_WRLVL_CNTL 0x8655f605 -#define DDR_DDR_WRLVL_CNTL_2 0x05060607 -#define DDR_DDR_WRLVL_CNTL_3 0x05050505 -#define DDR_DDR_CDR1 0x80040000 -#define DDR_DDR_CDR2 0x00000001 -#define DDR_SDRAM_CLK_CNTL 0x02000000 -#define DDR_DDR_ZQ_CNTL 0x89080600 -#define DDR_CS0_CONFIG_2 0 -#define DDR_SDRAM_CFG_MEM_EN 0x80000000 - -/* DDR memory controller registers */ -struct ccsr_ddr { - u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ - u32 resv1[1]; - u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ - u32 resv2[1]; - u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ - u32 resv3[1]; - u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ - u32 resv4[25]; - u32 cs0_config; /* Chip Select Configuration */ - u32 cs1_config; /* Chip Select Configuration */ - u32 cs2_config; /* Chip Select Configuration */ - u32 cs3_config; /* Chip Select Configuration */ - u32 resv5[12]; - u32 cs0_config_2; /* Chip Select Configuration 2 */ - u32 cs1_config_2; /* Chip Select Configuration 2 */ - u32 cs2_config_2; /* Chip Select Configuration 2 */ - u32 cs3_config_2; /* Chip Select Configuration 2 */ - u32 resv6[12]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 sdram_data_init; /* SDRAM Data initialization */ - u32 resv7[1]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u32 resv8[5]; - u32 init_addr; /* training init addr */ - u32 init_ext_addr; /* training init extended addr */ - u32 resv9[4]; - u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ - u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ - u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ - u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ - u32 ddr_zq_cntl; /* ZQ calibration control*/ - u32 ddr_wrlvl_cntl; /* write leveling control*/ - u32 resv10[1]; - u32 ddr_sr_cntr; /* self refresvh counter */ - u32 ddr_sdram_rcw_1; /* Control Words 1 */ - u32 ddr_sdram_rcw_2; /* Control Words 2 */ - u32 resv11[2]; - u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ - u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ - u32 resv12[2]; - u32 ddr_sdram_rcw_3; /* Control Words 3 */ - u32 ddr_sdram_rcw_4; /* Control Words 4 */ - u32 ddr_sdram_rcw_5; /* Control Words 5 */ - u32 ddr_sdram_rcw_6; /* Control Words 6 */ - u32 resv13[20]; - u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ - u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ - u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ - u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ - u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ - u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ - u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ - u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ - u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ - u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ - u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ - u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ - u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ - u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ - u32 resv14[4]; - u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ - u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ - u32 resv15[2]; - u32 sdram_cfg_3; /* SDRAM Control Configuration 3 */ - u32 resv16[15]; - u32 deskew_cntl; /* SDRAM Deskew Control */ - u32 resv17[545]; - u32 ddr_dsr1; /* Debug Status 1 */ - u32 ddr_dsr2; /* Debug Status 2 */ - u32 ddr_cdr1; /* Control Driver 1 */ - u32 ddr_cdr2; /* Control Driver 2 */ - u32 resv18[50]; - u32 ip_rev1; /* IP Block Revision 1 */ - u32 ip_rev2; /* IP Block Revision 2 */ - u32 eor; /* Enhanced Optimization Register */ - u32 resv19[63]; - u32 mtcr; /* Memory Test Control Register */ - u32 resv20[7]; - u32 mtp1; /* Memory Test Pattern 1 */ - u32 mtp2; /* Memory Test Pattern 2 */ - u32 mtp3; /* Memory Test Pattern 3 */ - u32 mtp4; /* Memory Test Pattern 4 */ - u32 mtp5; /* Memory Test Pattern 5 */ - u32 mtp6; /* Memory Test Pattern 6 */ - u32 mtp7; /* Memory Test Pattern 7 */ - u32 mtp8; /* Memory Test Pattern 8 */ - u32 mtp9; /* Memory Test Pattern 9 */ - u32 mtp10; /* Memory Test Pattern 10 */ - u32 resv21[6]; - u32 ddr_mt_st_ext_addr; /* Memory Test Start Extended Address */ - u32 ddr_mt_st_addr; /* Memory Test Start Address */ - u32 ddr_mt_end_ext_addr; /* Memory Test End Extended Address */ - u32 ddr_mt_end_addr; /* Memory Test End Address */ - u32 resv22[36]; - u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ - u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ - u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ - u32 resv23[5]; - u32 capture_data_hi; /* Data Path Read Capture High */ - u32 capture_data_lo; /* Data Path Read Capture Low */ - u32 capture_ecc; /* Data Path Read Capture ECC */ - u32 resv24[5]; - u32 err_detect; /* Error Detect */ - u32 err_disable; /* Error Disable */ - u32 err_int_en; - u32 capture_attributes; /* Error Attrs Capture */ - u32 capture_address; /* Error Addr Capture */ - u32 capture_ext_address; /* Error Extended Addr Capture */ - u32 err_sbe; /* Single-Bit ECC Error Management */ - u32 resv25[105]; -}; - #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 #define CCI400_CTRLORD_EN_BARRIER 0 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index bacd70adf6..6465f215e8 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -331,6 +331,9 @@ struct sunxi_ccm_reg { #define AHB_RESET_OFFSET_LCD1 5 #define AHB_RESET_OFFSET_LCD0 4 +/* ahb_reset2 offsets */ +#define AHB_RESET_OFFSET_LVDS 0 + /* apb2 reset */ #define APB2_RESET_UART_SHIFT (16) #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 5e94253203..ae954171f3 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -363,6 +363,11 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) +#else +#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ +#endif #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) @@ -372,8 +377,15 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_LCDC_LVDS_ANA0 0x40040320 +#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) +#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) +#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) +#else #define SUNXI_LCDC_LVDS_ANA0 0x3f310000 #define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) +#endif #define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) #define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h index 40c385a5bc..139e3366a6 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h @@ -164,8 +164,7 @@ struct dram_para { #define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */ -#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) -#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) +#define DRAM_IOCR_ODT_EN ((3 << 30) | (3 << 0)) #define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) #define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h index 06adee2723..316a3338f8 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h @@ -19,6 +19,7 @@ struct dram_para { u32 type; u32 zq; u32 odt_en; + s32 odt_correction; u32 para1; u32 para2; u32 mr0; diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 59d8210e88..148123a87f 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -155,6 +155,7 @@ enum sunxi_gpio_number { #define SUN5I_GPB_TWI2 2 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 +#define SUN8I_GPB_UART2 2 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 483c3a07fa..1de5b0710a 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,5 +1,13 @@ if ARCH_ZYNQ +config ZYNQ_CUSTOM_INIT + bool "Use custom ps7_init provided by Xilinx tool" + help + U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants. + If you want to override them with customized ones + or ps7_init code for your board is missing, please say Y here + and add ones into board/xilinx/zynq/custom_hw_platform/ directory. + choice prompt "Xilinx Zynq board select" optional @@ -14,13 +22,25 @@ config TARGET_ZYNQ_PICOZED bool "Zynq PicoZed" config TARGET_ZYNQ_ZC70X - bool "Zynq ZC702/ZC706 Board" + bool "Zynq ZC702/ZC706 Board (deprecated)" + select ZYNQ_CUSTOM_INIT + help + This option is deprecated. Use TARGET_ZYNQ_ZC702 + or TARGET_ZYNQ_706. + +config TARGET_ZYNQ_ZC702 + bool "Zynq ZC702 Board" + +config TARGET_ZYNQ_ZC706 + bool "Zynq ZC706 Board" config TARGET_ZYNQ_ZC770 bool "Zynq ZC770 Board" + select ZYNQ_CUSTOM_INIT config TARGET_ZYNQ_ZYBO bool "Zynq Zybo Board" + select ZYNQ_CUSTOM_INIT endchoice @@ -37,7 +57,8 @@ config SYS_CONFIG_NAME default "zynq_zed" if TARGET_ZYNQ_ZED default "zynq_microzed" if TARGET_ZYNQ_MICROZED default "zynq_picozed" if TARGET_ZYNQ_PICOZED - default "zynq_zc70x" if TARGET_ZYNQ_ZC70X + default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 \ + || TARGET_ZYNQ_ZC70X default "zynq_zc770" if TARGET_ZYNQ_ZC770 default "zynq_zybo" if TARGET_ZYNQ_ZYBO diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index e2e0b7321a..9a51d6ba3b 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -12,7 +12,6 @@ #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 -#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 #define ZYNQ_GEM_BASEADDR0 0xE000B000 #define ZYNQ_GEM_BASEADDR1 0xE000C000 #define ZYNQ_SDHCI_BASEADDR0 0xE0100000 diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 13025f034b..e7df6d3d7b 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -85,6 +85,6 @@ __weak void ps7_init(void) { /* * This function is overridden by the one in - * board/xilinx/zynq/ps7_init_gpl.c, if it exists. + * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists. */ } diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index 5ed9642df9..8ff82dc930 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -78,91 +78,10 @@ int timer_init(void) } /* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -ulong get_timer_masked(void) -{ - ulong now; - - now = readl(&timer_base->counter) / - (gd->arch.timer_rate_hz / CONFIG_SYS_HZ); - - if (gd->arch.lastinc >= now) { - /* Normal mode */ - gd->arch.tbl += gd->arch.lastinc - now; - } else { - /* We have an overflow ... */ - gd->arch.tbl += gd->arch.lastinc + (TIMER_LOAD_VAL / - (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - - now + 1; - } - gd->arch.lastinc = now; - - return gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - u32 countticks; - u32 timeend; - u32 timediff; - u32 timenow; - - if (usec == 0) - return; - - countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec), - 1000000); - - /* decrementing timer */ - timeend = readl(&timer_base->counter) - countticks; - -#if TIMER_LOAD_VAL != 0xFFFFFFFF - /* do not manage multiple overflow */ - if (countticks >= TIMER_LOAD_VAL) - countticks = TIMER_LOAD_VAL - 1; -#endif - - do { - timenow = readl(&timer_base->counter); - - if (timenow >= timeend) { - /* normal case */ - timediff = timenow - timeend; - } else { - if ((TIMER_LOAD_VAL - timeend + timenow) <= - countticks) { - /* overflow */ - timediff = TIMER_LOAD_VAL - timeend + timenow; - } else { - /* missed the exact match */ - break; - } - } - } while (timediff > 0); -} - -/* Timer without interrupts */ -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* * This function is derived from PowerPC code (timebase clock frequency). * On ARM it returns the number of timer ticks per second. */ ulong get_tbclk(void) { - return CONFIG_SYS_HZ; + return gd->arch.timer_rate_hz; } diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 8aac96f8d9..f078c9e504 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -10,9 +10,6 @@ config SYS_BOARD config SYS_CONFIG_NAME default "sandbox" -config DM_TEST - default y - config PCI bool "PCI support" help @@ -20,16 +17,4 @@ config PCI used on some devices to allow the CPU to communicate with its peripherals. -config NET - default y - -config NETDEVICES - default y - -config DM_ETH - default y - -config ETH_SANDBOX_RAW - default y - endmenu |
