diff options
Diffstat (limited to 'arch')
36 files changed, 280 insertions, 373 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 66ecc2ee4d..5fa182536d 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -116,6 +116,10 @@ else OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn endif +ifdef CONFIG_OF_EMBED +OBJCOPYFLAGS += -j .dtb.init.rodata +endif + ifneq ($(CONFIG_IMX_CONFIG),) ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index bbe9d1a8de..fc66872a31 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -94,6 +94,18 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->emif_rd_wr_exec_thresh, &emif_reg[nr]->emif_rd_wr_exec_thresh); + /* + * for most SOCs these registers won't need to be changed so only + * write to these registers if someone explicitly has set the + * register's value. + */ + if(regs->emif_cos_config) { + writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map); + writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map); + writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map); + writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config); + } + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index a7a3e88cd7..8b7527c5b4 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -115,7 +115,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, #endif #ifdef CONFIG_AM43XX writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); - while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0) + while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0) ; writel(0x80000000, &ddrctrl->ddrioctrl); diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index bd65a08ba2..7dd83ec9e1 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -80,7 +80,7 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) div = __raw_readl(&imx_ccm->analog_pll_sys); div &= BM_ANADIG_PLL_SYS_DIV_SELECT; - return infreq * (div >> 1); + return (infreq * div) >> 1; case PLL_BUS: div = __raw_readl(&imx_ccm->analog_pll_528); div &= BM_ANADIG_PLL_528_DIV_SELECT; diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 172527987d..f20bdebf3f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -124,10 +124,9 @@ static void clear_ldo_ramp(void) } /* - * Set the VDDSOC + * Set the PMU_REG_CORE register * - * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set - * them to the specified millivolt level. + * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. * Possible values are from 0.725V to 1.450V in steps of * 0.025V (25mV). */ diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index e0ed3bfb43..1ea086d520 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -34,7 +34,7 @@ void zynq_ddrc_init(void) /* ECC is enabled when memory is in 16bit mode and it is enabled */ if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) && (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) { - puts("Memory: ECC enabled\n"); + puts("ECC enabled "); /* * Clear the first 1MB because it is not initialized from * first stage bootloader. To get ECC to work all memory has @@ -42,6 +42,6 @@ void zynq_ddrc_init(void) */ memset((void *)0, 0, 1 * 1024 * 1024); } else { - puts("Memory: ECC disabled\n"); + puts("ECC disabled "); } } diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index aa10fab4dd..8dd69b3c80 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -489,6 +489,12 @@ struct ctrl_stat { #define OMAP_GPIO_SETDATAOUT 0x0194 /* Control Device Register */ + + /* Control Device Register */ +#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F +#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8 +#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F + struct ctrl_dev { unsigned int deviceid; /* offset 0x00 */ unsigned int resv1[7]; @@ -502,10 +508,25 @@ struct ctrl_dev { unsigned int macid1h; /* offset 0x3c */ unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ - unsigned int resv5[106]; + unsigned int resv5[7]; + unsigned int mreqprio_0; /* offset 0x70 */ + unsigned int mreqprio_1; /* offset 0x74 */ + unsigned int resv6[97]; unsigned int efuse_sma; /* offset 0x1FC */ }; +/* Bandwidth Limiter Portion of the L3Fast Configuration Register */ +#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0 +#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0 +#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800 + +struct l3f_cfg_bwlimiter { + u32 padding0[2]; + u32 modena_init0_bw_fractional; + u32 modena_init0_bw_integer; + u32 modena_init0_watermark_0; +}; + /* gmii_sel register defines */ #define GMII1_SEL_MII 0x0 #define GMII1_SEL_RMII 0x1 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 15399dcc74..efdecf4613 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -13,6 +13,9 @@ /* Module base addresses */ +/* L3 Fast Configuration Bandwidth Limiter Base Address */ +#define L3F_CFG_BWLIMITER 0x44005200 + /* UART Base Address */ #define UART0_BASE 0x44E09000 @@ -40,6 +43,11 @@ #define VTP0_CTRL_ADDR 0x44E10E0C #define VTP1_CTRL_ADDR 0x48140E10 +/* USB CTRL Base Address */ +#define USB1_CTRL 0x44e10628 +#define USB1_CTRL_CM_PWRDN BIT(0) +#define USB1_CTRL_OTG_PWRDN BIT(1) + /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 0855d16ce5..e5c0b0d08f 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -29,6 +29,8 @@ #define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 #define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR #define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC +#define AM4372_BOARD_VERSION_START SRAM_SCRATCH_SPACE_ADDR + 0xD +#define AM4372_BOARD_VERSION_END SRAM_SCRATCH_SPACE_ADDR + 0x14 #define QSPI_BASE 0x47900000 #endif #endif diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 2e414adf3d..1a9604e710 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -158,7 +158,7 @@ MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CT MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10, 0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm) MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) @@ -206,7 +206,7 @@ MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x03F0, 0x00DC, 3, 0x07B0, 0, 0) MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x03F0, 0x00DC, 4, 0x07A0, 0, 0) MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x03F4, 0x00E0, 2, 0x0000, 0, 0) MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 853e59bb6e..7ca690700c 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -124,6 +124,8 @@ struct i2c_ctlr { /* bit fields definitions for IO Packet Header 3 format */ #define PKT_HDR3_READ_MODE_SHIFT 19 #define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) +#define PKT_HDR3_REPEAT_START_SHIFT 16 +#define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT) #define PKT_HDR3_SLAVE_ADDR_SHIFT 0 #define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 45668ca4dd..b8d6bdca9b 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -642,11 +642,16 @@ struct emif_reg_struct { u32 emif_ddr_phy_ctrl_1; u32 emif_ddr_phy_ctrl_1_shdw; u32 emif_ddr_phy_ctrl_2; - u32 padding7[12]; + u32 padding7[4]; + u32 emif_prio_class_serv_map; + u32 emif_connect_id_serv_1_map; + u32 emif_connect_id_serv_2_map; + u32 padding8[5]; u32 emif_rd_wr_exec_thresh; - u32 padding8[7]; + u32 emif_cos_config; + u32 padding9[6]; u32 emif_ddr_phy_status[21]; - u32 padding9[27]; + u32 padding10[27]; u32 emif_ddr_ext_phy_ctrl_1; u32 emif_ddr_ext_phy_ctrl_1_shdw; u32 emif_ddr_ext_phy_ctrl_2; @@ -1137,6 +1142,10 @@ struct emif_regs { u32 emif_rd_wr_lvl_rmp_ctl; u32 emif_rd_wr_lvl_ctl; u32 emif_rd_wr_exec_thresh; + u32 emif_prio_class_serv_map; + u32 emif_connect_id_serv_1_map; + u32 emif_connect_id_serv_2_map; + u32 emif_cos_config; }; struct lpddr2_mr_regs { diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c index 7cddb85a7f..b8be3182a0 100644 --- a/arch/blackfin/cpu/jtag-console.c +++ b/arch/blackfin/cpu/jtag-console.c @@ -112,11 +112,11 @@ static void jtag_send(const char *raw_str, uint32_t len) if (cooked_str != raw_str) free((char *)cooked_str); } -static void jtag_putc(const char c) +static void jtag_putc(struct stdio_dev *dev, const char c) { jtag_send(&c, 1); } -static void jtag_puts(const char *s) +static void jtag_puts(struct stdio_dev *dev, const char *s) { jtag_send(s, strlen(s)); } @@ -133,7 +133,7 @@ static int jtag_tstc_dbg(void) } /* Higher layers want to know when any data is available */ -static int jtag_tstc(void) +static int jtag_tstc(struct stdio_dev *dev) { return jtag_tstc_dbg() || leftovers_len; } @@ -142,7 +142,7 @@ static int jtag_tstc(void) * [32bit length][actual data] */ static uint32_t leftovers; -static int jtag_getc(void) +static int jtag_getc(struct stdio_dev *dev) { int ret; uint32_t emudat; @@ -173,7 +173,7 @@ static int jtag_getc(void) leftovers = emudat; } - return jtag_getc(); + return jtag_getc(dev); } int drv_jtag_console_init(void) diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h index d0fd537d88..2d8b293c3e 100644 --- a/arch/blackfin/include/asm/config-pre.h +++ b/arch/blackfin/include/asm/config-pre.h @@ -9,9 +9,6 @@ #ifndef __ASM_BLACKFIN_CONFIG_PRE_H__ #define __ASM_BLACKFIN_CONFIG_PRE_H__ -/* Misc helper functions */ -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - /* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE. * Depending on your cpu, some of these may not be valid, check your HRM. * The actual values here are meaningless as long as they're unique. diff --git a/arch/blackfin/lib/cache.c b/arch/blackfin/lib/cache.c index 0a321a448f..e8a0cb5deb 100644 --- a/arch/blackfin/lib/cache.c +++ b/arch/blackfin/lib/cache.c @@ -111,3 +111,13 @@ int dcache_status(void) { return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE; } + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + blackfin_dcache_flush_invalidate_range((const void *)start, (const void *)stop); +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + blackfin_dcache_flush_range((const void *)start, (const void *)stop); +} diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 5a789540fc..af1fd56068 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -20,6 +20,13 @@ #include <asm/fec.h> #endif +/* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */ +#ifdef CONFIG_M5235 +#define out_be_fbcs_reg out_be16 +#else +#define out_be_fbcs_reg out_be32 +#endif + /* * Breath some life into the CPU... * @@ -45,57 +52,57 @@ void cpu_init_f(void) out_8(&gpio->par_cs, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4); - out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); - out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5); - out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); - out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6); - out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); - out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); + out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE); + out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); #endif #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7); - out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); - out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); + out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE); + out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); #endif diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 07a9b359b5..4e363a4190 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -115,7 +115,7 @@ void setup_5441x_clocks(void) gd->cpu_clk = vco / temp; /* cpu clock */ gd->arch.flb_clk = vco / temp; /* FlexBus clock */ gd->arch.flb_clk >>= 1; - if (in_be16(ccm->misccr2) & 2) /* fsys/4 */ + if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */ gd->arch.flb_clk >>= 1; temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1; diff --git a/arch/m68k/include/asm/posix_types.h b/arch/m68k/include/asm/posix_types.h index b97d267423..4fbc0405f7 100644 --- a/arch/m68k/include/asm/posix_types.h +++ b/arch/m68k/include/asm/posix_types.h @@ -15,7 +15,7 @@ typedef long __kernel_off_t; typedef int __kernel_pid_t; typedef unsigned int __kernel_uid_t; typedef unsigned int __kernel_gid_t; -typedef unsigned long __kernel_size_t; +typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; typedef long __kernel_ptrdiff_t; typedef long __kernel_time_t; diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c index 42e0dc96f7..4105a28509 100644 --- a/arch/powerpc/cpu/mpc512x/serial.c +++ b/arch/powerpc/cpu/mpc512x/serial.c @@ -384,7 +384,7 @@ struct stdio_dev *open_port(int num, int baudrate) sprintf(env_val, "%d", baudrate); setenv(env_var, env_val); - if (port->start()) + if (port->start(port)) return NULL; set_bit(num, &initialized); @@ -407,7 +407,7 @@ int close_port(int num) if (!port) return -1; - ret = port->stop(); + ret = port->stop(port); clear_bit(num, &initialized); return ret; @@ -418,7 +418,7 @@ int write_port(struct stdio_dev *port, char *buf) if (!port || !buf) return -1; - port->puts(buf); + port->puts(port, buf); return 0; } @@ -433,8 +433,8 @@ int read_port(struct stdio_dev *port, char *buf, int size) if (!size) return 0; - while (port->tstc()) { - buf[cnt++] = port->getc(); + while (port->tstc(port)) { + buf[cnt++] = port->getc(port); if (cnt > size) break; } diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index b1fb062a08..55238df456 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -56,9 +56,6 @@ GOT_ENTRY(__init_end) GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) -#if defined(CONFIG_FADS) - GOT_ENTRY(environment) -#endif END_GOT /* diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 5c96b5fe16..eb4432f6d7 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -97,14 +97,8 @@ static int check_CPU (long clock, uint pvr, uint immr) pre = 'M'; m = 1; if (id_str == NULL) id_str = -# if defined(CONFIG_MPC852T) - "PC852T"; -# elif defined(CONFIG_MPC859T) +# if defined(CONFIG_MPC859T) "PC859T"; -# elif defined(CONFIG_MPC859DSL) - "PC859DSL"; -# elif defined(CONFIG_MPC866T) - "PC866T"; # else "PC866x"; /* Unknown chip from MPC866 family */ # endif diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 9c3102dc69..e51fec7260 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -138,8 +138,6 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_MHPC) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ - defined(CONFIG_RPXLITE) || \ - defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; @@ -206,10 +204,6 @@ void cpu_init_f (volatile immap_t * immr) __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); -#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM) - rpxlite_init (); -#endif - #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ /* write config value */ immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index 65dfeabba4..d12b3df4a1 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -377,26 +377,6 @@ static void fec_pin_init(int fecidx) */ immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; -#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) - { - volatile fec_t *fecp; - - /* - * only two FECs please - */ - if ((unsigned int)fecidx >= 2) - hang(); - - if (fecidx == 0) - fecp = &immr->im_cpm.cp_fec1; - else - fecp = &immr->im_cpm.cp_fec2; - - /* our PHYs are the limit at 2.5 MHz */ - fecp->fec_mii_speed <<= 1; - } -#endif - #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) /* use MDC for MII */ immr->im_ioport.iop_pdpar |= 0x0080; @@ -562,32 +542,6 @@ static int fec_init (struct eth_device *dev, bd_t * bd) (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); int i; - if (efis->ether_index == 0) { -#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */ -#if defined(CONFIG_MPC885ADS) - *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST); -#else - /* configure FADS for fast (FEC) ethernet, half-duplex */ - /* The LXT970 needs about 50ms to recover from reset, so - * wait for it by discovering the PHY before leaving eth_init(). - */ - { - volatile uint *bcsr4 = (volatile uint *) BCSR4; - - *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1)) - | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | - BCSR4_FETHRST); - - /* reset the LXT970 PHY */ - *bcsr4 &= ~BCSR4_FETHRST; - udelay (10); - *bcsr4 |= BCSR4_FETHRST; - udelay (10); - } -#endif /* CONFIG_MPC885ADS */ -#endif /* CONFIG_FADS */ - } - #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* the MII interface is connected to FEC1 * so for the miiphy_xxx function to work we must diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 5da697366d..01029ff68a 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -197,19 +197,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) reset_phy(); #endif -#ifdef CONFIG_FADS -#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T) - /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */ - *((uint *) BCSR4) &= ~BCSR4_ETHLOOP; - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#else - *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN); - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif -#endif - pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]); rxIdx = 0; @@ -461,20 +448,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined #endif -#ifdef CONFIG_RPXLITE - *((uchar *) BCSR0) |= BCSR0_ETHEN; -#endif - -#if defined(CONFIG_QS860T) - /* - * PB27=FDE-, set output low for full duplex - * PB26=Link Test Enable, normally high output - */ - immr->im_cpm.cp_pbdir |= 0x00000030; - immr->im_cpm.cp_pbdat |= 0x00000020; - immr->im_cpm.cp_pbdat &= ~0x00000010; -#endif /* QS860T */ - #if defined(CONFIG_NETVIA) #if defined(PA_ENET_PDN) immr->im_ioport.iop_papar &= ~PA_ENET_PDN; @@ -502,13 +475,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - /* - * Work around transmit problem with first eth packet - */ -#if defined (CONFIG_FADS) - udelay (10000); /* wait 10 ms */ -#endif - return 1; } diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index 932141144c..b1625fba16 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -173,20 +173,6 @@ static int smc_init (void) # endif #endif -#if defined(CONFIG_FADS) - /* Enable RS232 */ -#if defined(CONFIG_8xx_CONS_SMC1) - *((uint *) BCSR1) &= ~BCSR1_RS232EN_1; -#else - *((uint *) BCSR1) &= ~BCSR1_RS232EN_2; -#endif -#endif /* CONFIG_FADS */ - -#if defined(CONFIG_RPXLITE) - /* Enable Monitor Port Transceiver */ - *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; -#endif /* CONFIG_RPXLITE */ - /* Set the physical address of the host memory buffers in * the buffer descriptors. */ diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index fc351585be..9590bfd3fd 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -798,22 +798,6 @@ static void video_encoder_init (void) i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif -#ifdef CONFIG_FADS - /* Reset ADV7176 chip */ - debug ("[VIDEO ENCODER] Resetting encoder...\n"); - (*(int *) BCSR4) &= ~(1 << 21); - - /* Wait for 5 ms inside the reset */ - debug ("[VIDEO ENCODER] Waiting for encoder reset...\n"); - udelay (5000); - - /* Take ADV7176 out of reset */ - (*(int *) BCSR4) |= 1 << 21; - - /* Wait for 5 ms after the reset */ - udelay (5000); -#endif /* CONFIG_FADS */ - /* Send configuration */ #ifdef DEBUG { @@ -860,16 +844,6 @@ static void video_ctrl_init (void *memptr) debug ("[VIDEO CTRL] Turning off video controller...\n"); SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 0); -#ifdef CONFIG_FADS - /* Turn on Video Port LED */ - debug ("[VIDEO CTRL] Turning off video port led...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 1); - - /* Disable internal clock */ - debug ("[VIDEO CTRL] Disabling internal clock...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 0); -#endif - /* Generate and make active a new video mode */ debug ("[VIDEO CTRL] Generating video mode...\n"); video_mode_generate (); @@ -892,15 +866,6 @@ static void video_ctrl_init (void *memptr) immap->im_ioport.iop_pdpar = 0x1fff; immap->im_ioport.iop_pddir = 0x0000; -#ifdef CONFIG_FADS - /* Turn on Video Port Clock - ONLY AFTER SET VCCR TO ENABLE EXTERNAL CLOCK */ - debug ("[VIDEO CTRL] Turning on video clock...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 1); - - /* Turn on Video Port LED */ - debug ("[VIDEO CTRL] Turning on video port led...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0); -#endif #ifdef CONFIG_RRVISION debug ("PC5->Output(1): enable PAL clock"); immap->im_ioport.iop_pcpar &= ~(0x0400); @@ -983,7 +948,7 @@ static inline void console_newline (void) } } -void video_putc (const char c) +void video_putc(struct stdio_dev *dev, const char c) { if (!video_enable) { serial_putc (c); @@ -1020,7 +985,7 @@ void video_putc (const char c) } } -void video_puts (const char *s) +void video_puts(struct stdio_dev *dev, const char *s) { int count = strlen (s); @@ -1029,7 +994,7 @@ void video_puts (const char *s) serial_putc (*s++); else while (count--) - video_putc (*s++); + video_putc(dev, *s++); } /************************************************************************/ @@ -1153,9 +1118,7 @@ static void *video_logo (void) { u16 *screen = video_fb_address, width = VIDEO_COLS; #ifdef VIDEO_INFO -# ifndef CONFIG_FADS char temp[32]; -# endif char info[80]; #endif /* VIDEO_INFO */ @@ -1173,7 +1136,7 @@ static void *video_logo (void) sprintf (info, " Wolfgang DENK, wd@denx.de"); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, info); -#ifndef CONFIG_FADS /* all normal boards */ + /* leave one blank line */ sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash", @@ -1182,15 +1145,6 @@ static void *video_logo (void) gd->bd->bi_flashsize >> 20 ); video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4, info); -#else /* FADS :-( */ - sprintf (info, "MPC823 CPU at 50 MHz on FADS823 board"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, - info); - - sprintf(info, "2MiB FLASH - 8MiB DRAM - 4MiB SRAM"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, - info); -#endif #endif return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN; diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 7e077d5a9f..4baee7774c 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -19,8 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUGF(fmt,args...) #endif -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - #if defined(CONFIG_405GP) void get_sys_info (PPC4xx_SYS_INFO * sysInfo) diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 3f4005b5d7..1aa397c5e7 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <dm/root.h> #include <os.h> #include <asm/state.h> @@ -14,6 +15,9 @@ void reset_cpu(ulong ignored) if (state_uninit()) os_exit(2); + if (dm_uninit()) + os_exit(2); + /* This is considered normal termination for now */ os_exit(0); } diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index aad3b8b147..b3d70515dc 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -6,6 +6,7 @@ #include <common.h> #include <os.h> #include <asm/getopt.h> +#include <asm/io.h> #include <asm/sections.h> #include <asm/state.h> @@ -218,6 +219,7 @@ SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1, int main(int argc, char *argv[]) { struct sandbox_state *state; + gd_t data; int ret; ret = state_init(); @@ -236,6 +238,12 @@ int main(int argc, char *argv[]) if (state->ram_buf_rm && state->ram_buf_fname) os_unlink(state->ram_buf_fname); + memset(&data, '\0', sizeof(data)); + gd = &data; +#ifdef CONFIG_SYS_MALLOC_F_LEN + gd->malloc_base = CONFIG_MALLOC_F_ADDR; +#endif + /* Do pre- and post-relocation init */ board_init_f(0); diff --git a/arch/sandbox/include/asm/config.h b/arch/sandbox/include/asm/config.h index 6c1bff99c2..ec7729eb4c 100644 --- a/arch/sandbox/include/asm/config.h +++ b/arch/sandbox/include/asm/config.h @@ -7,7 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_GLOBAL_DATA #define CONFIG_SANDBOX_ARCH /* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */ diff --git a/arch/sandbox/include/asm/arch-sandbox/sound.h b/arch/sandbox/include/asm/sound.h index a32e8c802d..a32e8c802d 100644 --- a/arch/sandbox/include/asm/arch-sandbox/sound.h +++ b/arch/sandbox/include/asm/sound.h diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds deleted file mode 100644 index 254d9f274b..0000000000 --- a/arch/sh/cpu/sh2/u-boot.lds +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh2/start.o (.text)) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds deleted file mode 100644 index 57544ce040..0000000000 --- a/arch/sh/cpu/sh4/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2008-2009 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh4/start.o (.text)) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss (NOLOAD) : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/u-boot.lds index 26de08606a..30c7a9d3f8 100644 --- a/arch/sh/cpu/sh3/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -1,10 +1,10 @@ /* * Copyright (C) 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * Copyright (C) 2007 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * + * Copyright (C) 2008-2009 + * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * * Copyright (C) 2008 * Mark Jonas <mark.jonas@de.bosch.com> * @@ -28,7 +28,7 @@ SECTIONS .text : { - KEEP(arch/sh/cpu/sh3/start.o (.text)) + KEEP(*/start.o (.text)) . = ALIGN(8192); common/env_embedded.o (.ppcenv) . = ALIGN(8192); diff --git a/arch/sparc/cpu/u-boot.lds b/arch/sparc/cpu/u-boot.lds new file mode 100644 index 0000000000..1ade3b344b --- /dev/null +++ b/arch/sparc/cpu/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2007-2008 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") +OUTPUT_ARCH(sparc) +ENTRY(_start) +SECTIONS +{ + +/* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + + .text : { + _load_addr = .; + _text = .; + + *(.start) + */start.o (.text) +/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ + . = ALIGN(8192); +/* PROM CODE, Will be relocated to the end of memory, + * no global data accesses please. + */ + __prom_start = .; + *(.prom.pgt) + *(.prom.data) + *(.prom.text) + . = ALIGN(16); + __prom_end = .; + *(.text) + *(.fixup) + *(.gnu.warning) +/* *(.got1)*/ + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + . = ALIGN(4); + _etext = .; + + /* CMD Table */ + + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + .data : + { + *(.data) + *(.data1) + *(.data.rel) + *(.data.rel.*) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = ALIGN(4); + __got_start = .; + .got : { + *(.got) +/* *(.data.rel) + *(.data.rel.local)*/ + . = ALIGN(16); + } + __got_end = .; + +/* .data.rel : { } */ + + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(16); /* to speed clearing of bss up */ + } + __bss_end = . ; + __bss_end = . ; + PROVIDE (end = .); + +/* Relocated into main memory */ + + /* Start of main memory */ + /*. = 0x40000000;*/ + + .stack (NOLOAD) : { *(.stack) } + + /* PROM CODE */ + + /* global data in RAM passed to kernel after booting */ + + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + +} diff --git a/arch/x86/lib/video.c b/arch/x86/lib/video.c index dfd2a8496e..975949daa3 100644 --- a/arch/x86/lib/video.c +++ b/arch/x86/lib/video.c @@ -104,7 +104,7 @@ static void __video_putc(const char c, int *x, int *y) } } -static void video_putc(const char c) +static void video_putc(struct stdio_dev *dev, const char c) { int x, y, pos; @@ -123,7 +123,7 @@ static void video_putc(const char c) outb_p(0xff & (pos >> 1), vidport+1); } -static void video_puts(const char *s) +static void video_puts(struct stdio_dev *dev, const char *s) { int x, y, pos; char c; @@ -178,8 +178,6 @@ int video_init(void) vga_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; vga_dev.putc = video_putc; /* 'putc' function */ vga_dev.puts = video_puts; /* 'puts' function */ - vga_dev.tstc = NULL; /* 'tstc' function */ - vga_dev.getc = NULL; /* 'getc' function */ if (stdio_register(&vga_dev) == 0) return 1; @@ -191,8 +189,6 @@ int video_init(void) strcpy(kbd_dev.name, "kbd"); kbd_dev.ext = 0; kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbd_dev.putc = NULL; /* 'putc' function */ - kbd_dev.puts = NULL; /* 'puts' function */ kbd_dev.tstc = i8042_tstc; /* 'tstc' function */ kbd_dev.getc = i8042_getc; /* 'getc' function */ |
