diff options
Diffstat (limited to 'arch')
21 files changed, 158 insertions, 72 deletions
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index f013dc3cad..36b7f11fbe 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -32,4 +32,31 @@ config CMD_PINMON The boot mode pins are latched when the system reset is deasserted and determine which device the system should load a boot image from. +config SOC_INIT + bool + default SPL_BUILD + +config DRAM_INIT + bool + default SPL_BUILD + +choice + prompt "DDR3 Frequency select" + depends on DRAM_INIT + +config DDR_FREQ_1600 + bool "DDR3 1600" + depends on MACH_PH1_PRO4 || MACH_PH1_LD4 + +config DDR_FREQ_1333 + bool "DDR3 1333" + depends on MACH_PH1_LD4 || MACH_PH1_SLD8 + +endchoice + +config DDR_FREQ + int + default 1333 if DDR_FREQ_1333 + default 1600 if DDR_FREQ_1600 + endmenu diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile index dd57469d9c..0f64d2591c 100644 --- a/arch/arm/cpu/armv7/uniphier/Makefile +++ b/arch/arm/cpu/armv7/uniphier/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-y += timer.o obj-y += reset.o obj-y += cache_uniphier.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o obj-y += dram_init.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c index 4302277dfc..89e44bb95b 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c +++ b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c @@ -5,11 +5,13 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> +#include <linux/compiler.h> #include <asm/arch/led.h> #include <asm/arch/board.h> -void bcu_init(void); +void __weak bcu_init(void) +{ +}; void sbc_init(void); void sg_init(void); void pll_init(void); @@ -18,12 +20,15 @@ void clkrst_init(void); int board_postclk_init(void) { +#ifdef CONFIG_SOC_INIT bcu_init(); sbc_init(); sg_init(); + uniphier_board_reset(); + pll_init(); uniphier_board_init(); @@ -33,7 +38,7 @@ int board_postclk_init(void) clkrst_init(); led_write(B, 2, , ); - +#endif pin_init(); led_write(B, 3, , ); diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c index 5465a0e6bf..7de657b7af 100644 --- a/arch/arm/cpu/armv7/uniphier/dram_init.c +++ b/arch/arm/cpu/armv7/uniphier/dram_init.c @@ -16,7 +16,7 @@ int dram_init(void) DECLARE_GLOBAL_DATA_PTR; gd->ram_size = CONFIG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_DRAM_INIT led_write(B, 4, , ); { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index 781b511a97..fba1cc7498 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ - sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c index 0047223181..62f5b0148d 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c @@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c index 1344ac1caa..ebcbaabf65 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c @@ -149,10 +149,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR Frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile index e11f4f6d8b..74129bc86a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ - sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c deleted file mode 100644 index 7198829988..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/led.h> -#include <asm/arch/board.h> - -void sbc_init(void); -void sg_init(void); -void pll_init(void); -void pin_init(void); -void clkrst_init(void); - -int board_postclk_init(void) -{ - sbc_init(); - - sg_init(); - - pll_init(); - - uniphier_board_init(); - - led_write(B, 1, , ); - - clkrst_init(); - - led_write(B, 2, , ); - - pin_init(); - - led_write(B, 3, , ); - - return 0; -} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c index 503c247d6b..4e3d47615b 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c @@ -41,5 +41,12 @@ void pin_init(void) sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */ #endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */ + sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */ +#endif + writel(1, SG_LOADPINCTRL); } diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c index 6da921e920..1843d0469f 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c @@ -13,3 +13,13 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c index dd462875bb..328b2f4d9a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c @@ -122,10 +122,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR frequency. -#endif - #if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile index 781b511a97..fba1cc7498 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ - sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c deleted file mode 100644 index 287b33c21d..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/board_postclk_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c index 59d054a310..72ec599f69 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c @@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c index ff2dcb1640..a44f999fbf 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c @@ -129,10 +129,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 -#error Unsupported DDR frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c index b0dc9673b4..50d1fed647 100644 --- a/arch/arm/cpu/armv7/uniphier/reset.c +++ b/arch/arm/cpu/armv7/uniphier/reset.c @@ -8,14 +8,11 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/sc-regs.h> -#include <asm/arch/board.h> void reset_cpu(unsigned long ignored) { u32 tmp; - uniphier_board_reset(); - writel(5, SC_IRQTIMSET); /* default value */ tmp = readl(SC_SLFRSTSEL); diff --git a/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h new file mode 100644 index 0000000000..e9c5fb4af8 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLAT_UNIPHIER_EHCI_H +#define __PLAT_UNIPHIER_EHCI_H + +#include <linux/types.h> +#include <asm/io.h> +#include "mio-regs.h" + +struct uniphier_ehci_platform_data { + unsigned long base; +}; + +extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[]; + +static inline void uniphier_ehci_reset(int index, int on) +{ + u32 tmp; + + tmp = readl(MIO_USB_RSTCTRL(index)); + if (on) + tmp &= ~MIO_USB_RSTCTRL_XRST; + else + tmp |= MIO_USB_RSTCTRL_XRST; + writel(tmp, MIO_USB_RSTCTRL(index)); +} + +#endif /* __PLAT_UNIPHIER_EHCI_H */ diff --git a/arch/arm/include/asm/arch-uniphier/mio-regs.h b/arch/arm/include/asm/arch-uniphier/mio-regs.h new file mode 100644 index 0000000000..3306934ff7 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/mio-regs.h @@ -0,0 +1,20 @@ +/* + * UniPhier MIO (Media I/O) registers + * + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_MIO_REGS_H +#define ARCH_MIO_REGS_H + +#define MIO_BASE 0x59810000 + +#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020) +#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110) +#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114) + +#define MIO_USB_RSTCTRL_XRST (0x1 << 0) + +#endif /* ARCH_MIO_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/platdevice.h b/arch/arm/include/asm/arch-uniphier/platdevice.h index cdf7d132d4..62a512659c 100644 --- a/arch/arm/include/asm/arch-uniphier/platdevice.h +++ b/arch/arm/include/asm/arch-uniphier/platdevice.h @@ -21,4 +21,6 @@ U_BOOT_DEVICE(serial##n) = { \ .platdata = &serial_device##n \ }; +#include <asm/arch/ehci-uniphier.h> + #endif /* ARCH_PLATDEVICE_H */ diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h index 79d7ec7148..fa5e6ae0f2 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -88,7 +88,18 @@ #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16) #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16) -#ifndef __ASSEMBLY__ +#ifdef __ASSEMBLY__ + + .macro set_pinsel, n, value, ra, rd + ldr \ra, =SG_PINSEL_ADDR(\n) + ldr \rd, [\ra] + and \rd, \rd, #SG_PINSEL_MASK(\n) + orr \rd, \rd, #SG_PINSEL_MODE(\n, \value) + str \rd, [\ra] + .endm + +#else + #include <linux/types.h> #include <asm/io.h> |
