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-rw-r--r--arch/arm/cpu/armv7/omap4/clocks.c4
-rw-r--r--arch/arm/cpu/armv7/tegra2/board.c2
-rw-r--r--arch/arm/include/asm/global_data.h1
-rw-r--r--arch/arm/lib/board.c29
-rw-r--r--arch/powerpc/cpu/mpc512x/serial.c2
-rw-r--r--arch/powerpc/cpu/mpc86xx/interrupts.c12
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c2
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c2
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c2
-rw-r--r--arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c17
-rw-r--r--arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c8
-rw-r--r--arch/powerpc/cpu/ppc4xx/4xx_pcie.c3
-rw-r--r--arch/powerpc/cpu/ppc4xx/denali_data_eye.c10
-rw-r--r--arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c52
-rw-r--r--arch/powerpc/lib/board.c10
-rw-r--r--arch/sandbox/lib/board.c2
-rw-r--r--arch/sh/lib/board.c2
17 files changed, 94 insertions, 66 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index 4f0e0cd881..095ba39aeb 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -603,7 +603,7 @@ static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
+ debug("Enable clock domain - %p\n", clkctrl_reg);
}
static inline void wait_for_clk_enable(u32 *clkctrl_addr)
@@ -630,7 +630,7 @@ static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
{
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - 0x%08x\n", clkctrl_addr);
+ debug("Enable clock module - %p\n", clkctrl_addr);
if (wait_for_enable)
wait_for_clk_enable(clkctrl_addr);
}
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
index 9061d181d5..751102d180 100644
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -40,7 +40,7 @@ unsigned int query_sdram_size(void)
u32 reg;
reg = readl(&pmc->pmc_scratch20);
- debug("pmc->pmc_scratch20 (ODMData) = 0x%08lX\n", reg);
+ debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
/* bits 31:28 in OdmData are used for RAM size */
switch ((reg) >> 28) {
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index fac98d559a..c3ff789999 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -76,6 +76,7 @@ typedef struct global_data {
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long tlb_addr;
#endif
+ const void *fdt_blob; /* Our device tree, NULL if none */
void **jt; /* jump table */
char env_buf[32]; /* buffer for getenv() before reloc. */
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index c7648449b0..368fc5d6b3 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -48,6 +48,8 @@
#include <nand.h>
#include <onenand_uboot.h>
#include <mmc.h>
+#include <libfdt.h>
+#include <fdtdec.h>
#include <post.h>
#include <logbuff.h>
@@ -234,6 +236,9 @@ init_fnc_t *init_sequence[] = {
#if defined(CONFIG_BOARD_EARLY_INIT_F)
board_early_init_f,
#endif
+#ifdef CONFIG_OF_CONTROL
+ fdtdec_check_fdt,
+#endif
timer_init, /* initialize timer */
#ifdef CONFIG_FSL_ESDHC
get_clocks,
@@ -274,6 +279,16 @@ void board_init_f(ulong bootflag)
memset((void *)gd, 0, sizeof(gd_t));
gd->mon_len = _bss_end_ofs;
+#ifdef CONFIG_OF_EMBED
+ /* Get a pointer to the FDT */
+ gd->fdt_blob = _binary_dt_dtb_start;
+#elif defined CONFIG_OF_SEPARATE
+ /* FDT is at end of image */
+ gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE);
+#endif
+ /* Allow the early environment to override the fdt address */
+ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
+ (uintptr_t)gd->fdt_blob);
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
@@ -477,13 +492,14 @@ void board_init_r(gd_t *id, ulong dest_addr)
flash_size = flash_init();
if (flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
+ char *s = getenv("flashchecksum");
+
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
- s = getenv("flashchecksum");
if (s && (*s == 'y')) {
printf(" CRC: %08X", crc32(0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
@@ -566,12 +582,15 @@ void board_init_r(gd_t *id, ulong dest_addr)
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#if defined(CONFIG_CMD_NET)
- s = getenv("bootfile");
- if (s != NULL)
- copy_filename(BootFile, s, sizeof(BootFile));
+ {
+ char *s = getenv("bootfile");
+
+ if (s != NULL)
+ copy_filename(BootFile, s, sizeof(BootFile));
+ }
#endif
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c
index 5ee9ceff49..7c53346ea0 100644
--- a/arch/powerpc/cpu/mpc512x/serial.c
+++ b/arch/powerpc/cpu/mpc512x/serial.c
@@ -140,7 +140,7 @@ void serial_setbrg_dev(unsigned int idx)
if (br_env)
baudrate = simple_strtoul(br_env, NULL, 10);
- debug("%s: idx %d, baudrate %d\n", __func__, idx, baudrate);
+ debug("%s: idx %d, baudrate %ld\n", __func__, idx, baudrate);
}
/* calculate divisor for setting PSC CTUR and CTLR registers */
diff --git a/arch/powerpc/cpu/mpc86xx/interrupts.c b/arch/powerpc/cpu/mpc86xx/interrupts.c
index 14821f4243..aff1f6db5d 100644
--- a/arch/powerpc/cpu/mpc86xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc86xx/interrupts.c
@@ -59,28 +59,28 @@ int interrupt_init_cpu(unsigned long *decrementer_count)
pic->gcr = MPC86xx_PICGCR_MODE;
*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
- debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n",
+ debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %ld\n",
(get_tbclk() / 1000000),
*decrementer_count);
#ifdef CONFIG_INTERRUPTS
pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
- debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1);
+ debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
- debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2);
+ debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
- debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3);
+ debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
- debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8);
+ debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
#endif
#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
- debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9);
+ debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
#endif
pic->ctpr = 0; /* 40080 clear current task priority register */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
index 9184764418..376be2fb37 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
@@ -41,7 +41,7 @@ compute_ranksize(unsigned int mem_type, unsigned char row_dens)
/* Bottom 2 bits up to the top. */
bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
bsize <<= 24ULL;
- debug("DDR: DDR I rank density = 0x%08x\n", bsize);
+ debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
return bsize;
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
index b565e338ad..f637f3d045 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
@@ -40,7 +40,7 @@ compute_ranksize(unsigned int mem_type, unsigned char row_dens)
/* Bottom 5 bits up to the top. */
bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));
bsize <<= 27ULL;
- debug("DDR: DDR II rank density = 0x%08x\n", bsize);
+ debug("DDR: DDR II rank density = 0x%16llx\n", bsize);
return bsize;
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 838cebed57..ffb503a777 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -71,7 +71,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd)
bsize = 1ULL << (nbit_sdram_cap_bsize - 3
+ nbit_primary_bus_width - nbit_sdram_width);
- debug("DDR: DDR III rank density = 0x%16lx\n", bsize);
+ debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
return bsize;
}
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
index ec7291f9c8..e05daf23b7 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
@@ -820,7 +820,7 @@ static void program_tr0(unsigned long *dimm_populated,
break;
}
- debug("tr0: %x\n", tr0);
+ debug("tr0: %lx\n", tr0);
mtsdram(SDRAM0_TR0, tr0);
}
@@ -1051,7 +1051,7 @@ static void program_tr1(void)
}
tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
- debug("tr1: %x\n", tr1);
+ debug("tr1: %lx\n", tr1);
/*
* program SDRAM Timing Register 1 TR1
@@ -1124,7 +1124,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
- debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
+ debug("DIMM%ld: row=%d col=%d banks=%d\n", dimm_num,
num_row_addr, num_col_addr, num_banks);
/*
@@ -1193,9 +1193,11 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
(4 << 20) * bank_size_id;
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
- debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
- dimm_num, i, ctrl_bank_num[dimm_num]+i,
- bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
+ debug("DIMM%ld-bank %ld (SDRAM0_B%ldCR): "
+ "bank_size_bytes=%ld\n",
+ dimm_num, i,
+ ctrl_bank_num[dimm_num] + i,
+ bank_parms[ctrl_bank_num[dimm_num] + i].bank_size_bytes);
}
}
}
@@ -1239,7 +1241,8 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
bank_parms[sorted_bank_num[bx_cr_num]].cr;
mtdcr(SDRAM0_CFGDATA, temp);
bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
- debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
+ debug("SDRAM0_B%ldCR=0x%08lx\n",
+ sorted_bank_num[bx_cr_num], temp);
}
}
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index b909fcab0d..4b8e65a51d 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -907,8 +907,8 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
mtsdram(SDRAM_RQDC, rqdc_reg);
mtsdram(SDRAM_RFDC, rfdc_reg);
- debug("RQDC: 0x%08X\n", rqdc_reg);
- debug("RFDC: 0x%08X\n", rfdc_reg);
+ debug("RQDC: 0x%08lX\n", rqdc_reg);
+ debug("RFDC: 0x%08lX\n", rfdc_reg);
/* if something passed, then return the size of the largest window */
if (passed != 0) {
@@ -1214,7 +1214,7 @@ u32 DQS_autocalibration(void)
SDRAM_RQDC_RQFD_ENCODE(tcal.autocal.rqfd));
mfsdram(SDRAM_RQDC, rqdc_reg);
- debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
+ debug("*** best_result: read value SDRAM_RQDC 0x%08lx\n",
rqdc_reg);
#if defined(CONFIG_DDR_RFDC_FIXED)
@@ -1227,7 +1227,7 @@ u32 DQS_autocalibration(void)
#endif /* CONFIG_DDR_RFDC_FIXED */
mfsdram(SDRAM_RFDC, rfdc_reg);
- debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",
+ debug("*** best_result: read value SDRAM_RFDC 0x%08lx\n",
rfdc_reg);
mfsdram(SDRAM_RDCC, val);
debug("*** SDRAM_RDCC 0x%08x\n", val);
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
index b76890e099..a87e93b80c 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
@@ -265,7 +265,8 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
*/
pcie_dmer_disable ();
- debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
+ debug("%s: cfg_data=%p offset=%08x\n", __func__,
+ hose->cfg_data, offset);
switch (len) {
case 1:
*val = in_8(hose->cfg_data + offset);
diff --git a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c
index 9bba0caec7..19b65be61c 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c
@@ -317,7 +317,7 @@ void denali_core_search_data_eye(void)
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
- debug("DDR0_09=0x%08lx\n", val);
+ debug("DDR0_09=0x%08x\n", val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
@@ -327,7 +327,7 @@ void denali_core_search_data_eye(void)
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
- debug("DDR0_22=0x%08lx\n", val);
+ debug("DDR0_22=0x%08x\n", val);
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
@@ -337,7 +337,7 @@ void denali_core_search_data_eye(void)
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
- debug("DDR0_17=0x%08lx\n", val);
+ debug("DDR0_17=0x%08x\n", val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
@@ -347,7 +347,7 @@ void denali_core_search_data_eye(void)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
- debug("DDR0_18=0x%08lx\n", val);
+ debug("DDR0_18=0x%08x\n", val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
@@ -357,7 +357,7 @@ void denali_core_search_data_eye(void)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
- debug("DDR0_19=0x%08lx\n", val);
+ debug("DDR0_19=0x%08x\n", val);
/* -----------------------------------------------------------+
* Assert 'start' parameter.
diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
index c35b11348a..ce769a7156 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
@@ -360,7 +360,7 @@ static void get_spd_info(unsigned long dimm_ranks[],
printf("Install at least one DDR2 DIMM.\n\n");
spd_ddr_init_hang();
}
- debug("Total number of ranks = %d\n", *ranks);
+ debug("Total number of ranks = %ld\n", *ranks);
}
/*------------------------------------------------------------------
@@ -387,7 +387,7 @@ static void check_frequency(unsigned long *dimm_ranks,
if (dimm_ranks[dimm_num]) {
cycle_time =
get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
- debug("cycle_time=%d ps\n", cycle_time);
+ debug("cycle_time=%ld ps\n", cycle_time);
if (cycle_time > (calc_cycle_time + 10)) {
/*
@@ -470,10 +470,10 @@ static void get_dimm_size(unsigned long dimm_ranks[],
}
}
}
- debug("Number of rows = %d\n", *rows);
- debug("Number of columns = %d\n", *cols);
- debug("Number of banks = %d\n", *banks);
- debug("Data width = %d\n", *width);
+ debug("Number of rows = %ld\n", *rows);
+ debug("Number of columns = %ld\n", *cols);
+ debug("Number of banks = %ld\n", *banks);
+ debug("Data width = %ld\n", *width);
if (*rows > 14) {
printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
*rows);
@@ -568,7 +568,7 @@ static void program_ddr0_03(unsigned long dimm_ranks[],
/*------------------------------------------------------------------
* Get the board configuration info.
*-----------------------------------------------------------------*/
- debug("sdram_freq = %d\n", sdram_freq);
+ debug("sdram_freq = %ld\n", sdram_freq);
/*------------------------------------------------------------------
* Handle the timing. We need to find the worst case timing of all
@@ -601,7 +601,7 @@ static void program_ddr0_03(unsigned long dimm_ranks[],
get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
tcyc_addr[cas_index]));
- debug("cas_index = %d: cycle_time_ps = %d\n",
+ debug("cas_index = %ld: cycle_time_ps = %ld\n",
cas_index, cycle_time_ps);
/*
* DDR2 devices use the following bitmask for CAS latency:
@@ -640,10 +640,10 @@ static void program_ddr0_03(unsigned long dimm_ranks[],
cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
- debug("cycle_2_0_clk = %d\n", cycle_2_0_clk);
- debug("cycle_3_0_clk = %d\n", cycle_3_0_clk);
- debug("cycle_4_0_clk = %d\n", cycle_4_0_clk);
- debug("cycle_5_0_clk = %d\n", cycle_5_0_clk);
+ debug("cycle_2_0_clk = %ld\n", cycle_2_0_clk);
+ debug("cycle_3_0_clk = %ld\n", cycle_3_0_clk);
+ debug("cycle_4_0_clk = %ld\n", cycle_4_0_clk);
+ debug("cycle_5_0_clk = %ld\n", cycle_5_0_clk);
if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
*cas_latency = 2;
@@ -673,7 +673,7 @@ static void program_ddr0_03(unsigned long dimm_ranks[],
cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
spd_ddr_init_hang();
}
- debug("CAS latency = %d\n", *cas_latency);
+ debug("CAS latency = %ld\n", *cas_latency);
mtsdram(DDR0_03, ddr0_03);
}
@@ -728,11 +728,11 @@ static void program_ddr0_04(unsigned long dimm_ranks[],
t_rtp_ps = max(t_rtp_ps, ps);
}
}
- debug("t_rc_ps = %d\n", t_rc_ps);
+ debug("t_rc_ps = %ld\n", t_rc_ps);
t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
- debug("t_rrd_ps = %d\n", t_rrd_ps);
+ debug("t_rrd_ps = %ld\n", t_rrd_ps);
t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
- debug("t_rtp_ps = %d\n", t_rtp_ps);
+ debug("t_rtp_ps = %ld\n", t_rtp_ps);
t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
DDR0_04_TRRD_ENCODE(t_rrd_clk) |
@@ -769,9 +769,9 @@ static void program_ddr0_05(unsigned long dimm_ranks[],
t_ras_ps = max(t_ras_ps, ps);
}
}
- debug("t_rp_ps = %d\n", t_rp_ps);
+ debug("t_rp_ps = %ld\n", t_rp_ps);
t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
- debug("t_ras_ps = %d\n", t_ras_ps);
+ debug("t_ras_ps = %ld\n", t_ras_ps);
t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
@@ -828,9 +828,9 @@ static void program_ddr0_06(unsigned long dimm_ranks[],
t_rfc_ps = max(t_rfc_ps, ps);
}
}
- debug("t_wtr_ps = %d\n", t_wtr_ps);
+ debug("t_wtr_ps = %ld\n", t_wtr_ps);
t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
- debug("t_rfc_ps = %d\n", t_rfc_ps);
+ debug("t_rfc_ps = %ld\n", t_rfc_ps);
t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
DDR0_06_TRFC_ENCODE(t_rfc_clk));
@@ -857,7 +857,7 @@ static void program_ddr0_11(unsigned long sdram_freq)
unsigned long const t_xsnr_ps = 200000; /* 200 ns */
unsigned long t_xsnr_clk;
- debug("t_xsnr_ps = %d\n", t_xsnr_ps);
+ debug("t_xsnr_ps = %ld\n", t_xsnr_ps);
t_xsnr_clk =
(MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
@@ -928,9 +928,9 @@ static void program_ddr0_26(unsigned long sdram_freq)
unsigned long t_ref_clk;
/* Round down t_ras_max_clk and t_ref_clk */
- debug("t_ras_max_ps = %d\n", t_ras_max_ps);
+ debug("t_ras_max_ps = %ld\n", t_ras_max_ps);
t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
- debug("t_ref_ps = %d\n", t_ref_ps);
+ debug("t_ref_ps = %ld\n", t_ref_ps);
t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
DDR0_26_TREF_ENCODE(t_ref_clk));
@@ -941,7 +941,7 @@ static void program_ddr0_27(unsigned long sdram_freq)
unsigned long const t_init_ps = 200000000; /* 200 us. init */
unsigned long t_init_clk;
- debug("t_init_ps = %d\n", t_init_ps);
+ debug("t_init_ps = %ld\n", t_init_ps);
t_init_clk =
(MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
@@ -975,7 +975,7 @@ static void program_ddr0_43(unsigned long dimm_ranks[],
t_wr_ps = max(t_wr_ps, ps);
}
}
- debug("t_wr_ps = %d\n", t_wr_ps);
+ debug("t_wr_ps = %ld\n", t_wr_ps);
t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
}
@@ -1003,7 +1003,7 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
t_rcd_ps = max(t_rcd_ps, ps);
}
}
- debug("t_rcd_ps = %d\n", t_rcd_ps);
+ debug("t_rcd_ps = %ld\n", t_rcd_ps);
t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
}
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 6cb0ed6344..508075fa88 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -623,7 +623,6 @@ void board_init_f (ulong bootflag)
*/
void board_init_r (gd_t *id, ulong dest_addr)
{
- char *s;
bd_t *bd;
ulong malloc_start;
@@ -727,6 +726,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
flash_size = 0;
} else if ((flash_size = flash_init ()) > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
+ char *s;
+
print_size (flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
@@ -927,8 +928,11 @@ void board_init_r (gd_t *id, ulong dest_addr)
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#if defined(CONFIG_CMD_NET)
- if ((s = getenv ("bootfile")) != NULL) {
- copy_filename (BootFile, s, sizeof (BootFile));
+ {
+ char *s = getenv("bootfile");
+
+ if (s != NULL)
+ copy_filename(BootFile, s, sizeof(BootFile));
}
#endif
diff --git a/arch/sandbox/lib/board.c b/arch/sandbox/lib/board.c
index 1fd8fa651d..ae5a517605 100644
--- a/arch/sandbox/lib/board.c
+++ b/arch/sandbox/lib/board.c
@@ -250,7 +250,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
/* enable exceptions */
enable_interrupts();
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
index 6148e6baff..d9c0c228e0 100644
--- a/arch/sh/lib/board.c
+++ b/arch/sh/lib/board.c
@@ -141,7 +141,7 @@ init_fnc_t *init_sequence[] =
stdio_init,
console_init_r,
interrupt_init,
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
board_late_init,
#endif
#if defined(CONFIG_CMD_NET)
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