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-rw-r--r--arch/arm/Kconfig267
-rw-r--r--arch/arm/cpu/arm1136/mx35/generic.c2
-rw-r--r--arch/arm/cpu/arm926ejs/at91/led.c1
-rw-r--r--arch/arm/cpu/arm926ejs/cache.c5
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/Kconfig7
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/Kconfig3
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/mxs.c2
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_boot.c2
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/timer.c2
-rw-r--r--arch/arm/cpu/arm926ejs/nomadik/Kconfig3
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/Kconfig3
-rw-r--r--arch/arm/cpu/arm926ejs/spear/cpu.c2
-rw-r--r--arch/arm/cpu/arm926ejs/versatile/Kconfig3
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c61
-rw-r--r--arch/arm/cpu/armv7/am33xx/sys_info.c7
-rw-r--r--arch/arm/cpu/armv7/exynos/Kconfig10
-rw-r--r--arch/arm/cpu/armv7/highbank/Kconfig3
-rw-r--r--arch/arm/cpu/armv7/keystone/Kconfig6
-rw-r--r--arch/arm/cpu/armv7/keystone/Makefile5
-rw-r--r--arch/arm/cpu/armv7/keystone/clock-k2l.c138
-rw-r--r--arch/arm/cpu/armv7/keystone/clock.c17
-rw-r--r--arch/arm/cpu/armv7/keystone/cmd_clock.c24
-rw-r--r--arch/arm/cpu/armv7/keystone/cmd_ddr3.c248
-rw-r--r--arch/arm/cpu/armv7/keystone/ddr3.c244
-rw-r--r--arch/arm/cpu/armv7/keystone/init.c63
-rw-r--r--arch/arm/cpu/armv7/keystone/keystone_nav.c376
-rw-r--r--arch/arm/cpu/armv7/keystone/msmc.c26
-rw-r--r--arch/arm/cpu/armv7/keystone/spl.c53
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c4
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c19
-rw-r--r--arch/arm/cpu/armv7/omap-common/boot-common.c4
-rw-r--r--arch/arm/cpu/armv7/omap3/Kconfig25
-rw-r--r--arch/arm/cpu/armv7/omap3/board.c31
-rw-r--r--arch/arm/cpu/armv7/omap3/emif4.c2
-rw-r--r--arch/arm/cpu/armv7/omap3/sys_info.c4
-rw-r--r--arch/arm/cpu/armv7/omap4/Kconfig3
-rw-r--r--arch/arm/cpu/armv7/omap5/Kconfig3
-rw-r--r--arch/arm/cpu/armv7/rmobile/Kconfig8
-rw-r--r--arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S11
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/Kconfig3
-rw-r--r--arch/arm/cpu/armv7/socfpga/misc.c2
-rw-r--r--arch/arm/cpu/armv7/socfpga/u-boot-spl.lds9
-rw-r--r--arch/arm/cpu/armv7/start.S6
-rw-r--r--arch/arm/cpu/armv7/sunxi/Makefile16
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c42
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun4i.c13
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun6i.c76
-rw-r--r--arch/arm/cpu/armv7/sunxi/cpu_info.c10
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram.c68
-rw-r--r--arch/arm/cpu/armv7/sunxi/pinmux.c32
-rw-r--r--arch/arm/cpu/armv7/sunxi/prcm.c35
-rw-r--r--arch/arm/cpu/armv7/tegra20/display.c3
-rw-r--r--arch/arm/cpu/armv7/uniphier/Kconfig15
-rw-r--r--arch/arm/cpu/armv7/uniphier/Makefile2
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c15
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c15
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile1
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c15
-rw-r--r--arch/arm/cpu/armv7/zynq/Kconfig3
-rw-r--r--arch/arm/cpu/armv7/zynq/ddrc.c1
-rw-r--r--arch/arm/cpu/armv7/zynq/spl.c2
-rw-r--r--arch/arm/cpu/at91-common/spl.c2
-rw-r--r--arch/arm/cpu/tegra-common/sys_info.c2
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/am335x-bone-common.dtsi4
-rw-r--r--arch/arm/dts/dt-bindings/gpio/gpio.h15
-rw-r--r--arch/arm/dts/dt-bindings/pinctrl/am33xx.h42
-rw-r--r--arch/arm/dts/dt-bindings/pinctrl/omap.h55
-rw-r--r--arch/arm/dts/exynos4210-pinctrl-uboot.dtsi2
-rw-r--r--arch/arm/dts/exynos4210-trats.dts4
-rw-r--r--arch/arm/dts/exynos4210-universal_c210.dts4
-rw-r--r--arch/arm/dts/exynos4412-odroid.dts4
-rw-r--r--arch/arm/dts/exynos4412-trats2.dts6
-rw-r--r--arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi5
-rw-r--r--arch/arm/dts/exynos4x12-pinctrl.dtsi54
-rw-r--r--arch/arm/dts/sun7i-a20-pcduino3.dts177
-rw-r--r--arch/arm/dts/sun7i-a20.dtsi988
-rw-r--r--arch/arm/dts/sunxi-common-regulators.dtsi89
-rw-r--r--arch/arm/imx-common/cpu.c2
-rw-r--r--arch/arm/imx-common/iomux-v3.c15
-rw-r--r--arch/arm/imx-common/misc.c1
-rw-r--r--arch/arm/imx-common/spl.c2
-rw-r--r--arch/arm/imx-common/timer.c75
-rw-r--r--arch/arm/imx-common/video.c3
-rw-r--r--arch/arm/include/asm/arch-am33xx/mux.h2
-rw-r--r--arch/arm/include/asm/arch-am33xx/sys_proto.h2
-rw-r--r--arch/arm/include/asm/arch-at91/at91_shdwn.h35
-rw-r--r--arch/arm/include/asm/arch-bcm2835/mbox.h14
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h9
-rw-r--r--arch/arm/include/asm/arch-exynos/gpio.h59
-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2e.h43
-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2hk.h47
-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2l.h95
-rw-r--r--arch/arm/include/asm/arch-keystone/clock.h13
-rw-r--r--arch/arm/include/asm/arch-keystone/ddr3.h6
-rw-r--r--arch/arm/include/asm/arch-keystone/emac_defs.h237
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2e.h21
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2hk.h23
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2l.h108
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware.h102
-rw-r--r--arch/arm/include/asm/arch-keystone/msmc.h28
-rw-r--r--arch/arm/include/asm/arch-keystone/spl.h12
-rw-r--r--arch/arm/include/asm/arch-keystone/xhci-keystone.h21
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h12
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6sl_pins.h19
-rw-r--r--arch/arm/include/asm/arch-mxs/sys_proto.h2
-rw-r--r--arch/arm/include/asm/arch-omap3/mux.h4
-rw-r--r--arch/arm/include/asm/arch-omap3/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-rmobile/rcar-base.h2
-rw-r--r--arch/arm/include/asm/arch-socfpga/spl.h15
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock.h5
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h3
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h205
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu.h10
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h49
-rw-r--r--arch/arm/include/asm/arch-sunxi/mmc.h7
-rw-r--r--arch/arm/include/asm/arch-sunxi/prcm.h238
-rw-r--r--arch/arm/include/asm/arch-sunxi/timer.h23
-rw-r--r--arch/arm/include/asm/arch-sunxi/watchdog.h44
-rw-r--r--arch/arm/include/asm/arch-tegra/board.h11
-rw-r--r--arch/arm/include/asm/arch-uniphier/platdevice.h24
-rw-r--r--arch/arm/include/asm/imx-common/iomux-v3.h5
-rw-r--r--arch/arm/include/asm/imx-common/spi.h17
-rw-r--r--arch/arm/include/asm/imx-common/video.h5
-rw-r--r--arch/arm/include/asm/omap_gpio.h19
-rw-r--r--arch/arm/include/asm/spl.h2
-rw-r--r--arch/arm/include/asm/ti-common/keystone_nav.h (renamed from arch/arm/include/asm/arch-keystone/keystone_nav.h)16
-rw-r--r--arch/arm/include/asm/ti-common/keystone_net.h249
-rw-r--r--arch/arm/include/asm/ti-common/keystone_serdes.h55
-rw-r--r--arch/arm/include/asm/ti-common/ti-edma3.h121
-rw-r--r--arch/arm/include/asm/u-boot-arm.h15
-rw-r--r--arch/arm/lib/board.c41
-rw-r--r--arch/arm/lib/bootm.c6
-rw-r--r--arch/arm/lib/interrupts.c28
-rw-r--r--arch/arm/lib/relocate.S30
-rw-r--r--arch/arm/lib/vectors.S2
-rw-r--r--arch/blackfin/cpu/initcode.c1
-rw-r--r--arch/microblaze/Kconfig1
-rw-r--r--arch/mips/Kconfig110
-rw-r--r--arch/mips/config.mk44
-rw-r--r--arch/mips/cpu/mips32/config.mk14
-rw-r--r--arch/mips/cpu/mips64/config.mk14
-rw-r--r--arch/mips/cpu/u-boot.lds18
-rw-r--r--arch/powerpc/cpu/74xx_7xx/Kconfig16
-rw-r--r--arch/powerpc/cpu/74xx_7xx/start.S13
-rw-r--r--arch/powerpc/cpu/mpc5xxx/Kconfig5
-rw-r--r--arch/powerpc/cpu/mpc8260/Kconfig16
-rw-r--r--arch/powerpc/cpu/mpc8260/ether_fcc.c27
-rw-r--r--arch/powerpc/cpu/mpc8260/interrupts.c10
-rw-r--r--arch/powerpc/cpu/mpc8260/pci.c2
-rw-r--r--arch/powerpc/cpu/mpc8260/start.S14
-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig1
-rw-r--r--arch/powerpc/cpu/mpc83xx/start.S11
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig21
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init_early.c5
-rw-r--r--arch/powerpc/cpu/mpc8xx/Kconfig12
-rw-r--r--arch/powerpc/cpu/mpc8xx/cpu_init.c2
-rw-r--r--arch/powerpc/cpu/mpc8xx/fec.c40
-rw-r--r--arch/powerpc/cpu/ppc4xx/Kconfig1
-rw-r--r--arch/powerpc/cpu/ppc4xx/cpu_init.c3
-rw-r--r--arch/powerpc/include/asm/immap_512x.h1
-rw-r--r--arch/powerpc/include/asm/u-boot.h3
-rw-r--r--arch/sandbox/cpu/start.c3
-rw-r--r--arch/sandbox/include/asm/types.h5
-rw-r--r--arch/sh/lib/zimageboot.c1
-rw-r--r--arch/sparc/Kconfig43
-rw-r--r--arch/sparc/config.mk2
-rw-r--r--arch/sparc/cpu/leon2/config.mk10
-rw-r--r--arch/sparc/cpu/leon3/config.mk10
-rw-r--r--arch/x86/cpu/Makefile2
-rw-r--r--arch/x86/cpu/call64.S93
-rw-r--r--arch/x86/cpu/cpu.c144
-rw-r--r--arch/x86/cpu/start.S13
-rw-r--r--arch/x86/dts/coreboot.dtsi9
-rw-r--r--arch/x86/dts/link.dts18
-rw-r--r--arch/x86/include/asm/arch-coreboot/gpio.h15
-rw-r--r--arch/x86/include/asm/bootm.h16
-rw-r--r--arch/x86/include/asm/cpu.h55
-rw-r--r--arch/x86/include/asm/gpio.h1
-rw-r--r--arch/x86/include/asm/ibmpc.h10
-rw-r--r--arch/x86/include/asm/msr-index.h108
-rw-r--r--arch/x86/include/asm/types.h5
-rw-r--r--arch/x86/include/asm/zimage.h4
-rw-r--r--arch/x86/lib/bootm.c56
-rw-r--r--arch/x86/lib/physmem.c33
-rw-r--r--arch/x86/lib/relocate.c3
-rw-r--r--arch/x86/lib/zimage.c48
189 files changed, 5326 insertions, 1583 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8d05bb9ff9..79ccc06d5c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -7,139 +7,221 @@ config SYS_ARCH
config ARM64
bool
+config HAS_VBAR
+ bool
+
+config CPU_ARM720T
+ bool
+
+config CPU_ARM920T
+ bool
+
+config CPU_ARM926EJS
+ bool
+
+config CPU_ARM946ES
+ bool
+
+config CPU_ARM1136
+ bool
+
+config CPU_ARM1176
+ bool
+ select HAS_VBAR
+
+config CPU_V7
+ bool
+ select HAS_VBAR
+
+config CPU_PXA
+ bool
+
+config CPU_SA1100
+ bool
+
+config SYS_CPU
+ default "arm720t" if CPU_ARM720T
+ default "arm920t" if CPU_ARM920T
+ default "arm926ejs" if CPU_ARM926EJS
+ default "arm946es" if CPU_ARM946ES
+ default "arm1136" if CPU_ARM1136
+ default "arm1176" if CPU_ARM1176
+ default "armv7" if CPU_V7
+ default "pxa" if CPU_PXA
+ default "sa1100" if CPU_SA1100
+
choice
prompt "Target select"
config TARGET_INTEGRATORAP_CM720T
bool "Support integratorap_cm720t"
+ select CPU_ARM720T
config TARGET_INTEGRATORAP_CM920T
bool "Support integratorap_cm920t"
+ select CPU_ARM920T
config TARGET_INTEGRATORCP_CM920T
bool "Support integratorcp_cm920t"
+ select CPU_ARM920T
config TARGET_A320EVB
bool "Support a320evb"
+ select CPU_ARM920T
config TARGET_AT91RM9200EK
bool "Support at91rm9200ek"
+ select CPU_ARM920T
config TARGET_EB_CPUX9K2
bool "Support eb_cpux9k2"
+ select CPU_ARM920T
config TARGET_CPUAT91
bool "Support cpuat91"
+ select CPU_ARM920T
config TARGET_EDB93XX
bool "Support edb93xx"
+ select CPU_ARM920T
config TARGET_SCB9328
bool "Support scb9328"
+ select CPU_ARM920T
config TARGET_CM4008
bool "Support cm4008"
+ select CPU_ARM920T
config TARGET_CM41XX
bool "Support cm41xx"
+ select CPU_ARM920T
config TARGET_VCMA9
bool "Support VCMA9"
+ select CPU_ARM920T
config TARGET_SMDK2410
bool "Support smdk2410"
+ select CPU_ARM920T
config TARGET_INTEGRATORAP_CM926EJS
bool "Support integratorap_cm926ejs"
+ select CPU_ARM926EJS
config TARGET_INTEGRATORCP_CM926EJS
bool "Support integratorcp_cm926ejs"
+ select CPU_ARM926EJS
config TARGET_ASPENITE
bool "Support aspenite"
+ select CPU_ARM926EJS
config TARGET_GPLUGD
bool "Support gplugd"
+ select CPU_ARM926EJS
config TARGET_AFEB9260
bool "Support afeb9260"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9260EK
bool "Support at91sam9260ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9261EK
bool "Support at91sam9261ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9263EK
bool "Support at91sam9263ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9M10G45EK
bool "Support at91sam9m10g45ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9N12EK
bool "Support at91sam9n12ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9RLEK
bool "Support at91sam9rlek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9X5EK
bool "Support at91sam9x5ek"
+ select CPU_ARM926EJS
config TARGET_SNAPPER9260
bool "Support snapper9260"
+ select CPU_ARM926EJS
config TARGET_VL_MA2SC
bool "Support vl_ma2sc"
+ select CPU_ARM926EJS
config TARGET_SBC35_A9G20
bool "Support sbc35_a9g20"
+ select CPU_ARM926EJS
config TARGET_TNY_A9260
bool "Support tny_a9260"
+ select CPU_ARM926EJS
config TARGET_USB_A9263
bool "Support usb_a9263"
+ select CPU_ARM926EJS
config TARGET_ETHERNUT5
bool "Support ethernut5"
-
-config TARGET_TOP9000
- bool "Support top9000"
+ select CPU_ARM926EJS
config TARGET_MEESC
bool "Support meesc"
+ select CPU_ARM926EJS
config TARGET_OTC570
bool "Support otc570"
+ select CPU_ARM926EJS
config TARGET_CPU9260
bool "Support cpu9260"
+ select CPU_ARM926EJS
config TARGET_PM9261
bool "Support pm9261"
+ select CPU_ARM926EJS
config TARGET_PM9263
bool "Support pm9263"
+ select CPU_ARM926EJS
config TARGET_PM9G45
bool "Support pm9g45"
+ select CPU_ARM926EJS
config TARGET_CORVUS
bool "Support corvus"
+ select CPU_ARM926EJS
config TARGET_TAURUS
bool "Support taurus"
+ select CPU_ARM926EJS
config TARGET_STAMP9G20
bool "Support stamp9g20"
+ select CPU_ARM926EJS
config ARCH_DAVINCI
bool "TI DaVinci"
+ select CPU_ARM926EJS
help
Support for TI's DaVinci platform.
config KIRKWOOD
bool "Marvell Kirkwood"
+ select CPU_ARM926EJS
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
@@ -149,326 +231,468 @@ config TARGET_MAXBCM
config TARGET_DEVKIT3250
bool "Support devkit3250"
+ select CPU_ARM926EJS
config TARGET_JADECPU
bool "Support jadecpu"
+ select CPU_ARM926EJS
config TARGET_MX25PDK
bool "Support mx25pdk"
+ select CPU_ARM926EJS
config TARGET_TX25
bool "Support tx25"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_ZMX25
bool "Support zmx25"
+ select CPU_ARM926EJS
config TARGET_APF27
bool "Support apf27"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_IMX27LITE
bool "Support imx27lite"
+ select CPU_ARM926EJS
config TARGET_MAGNESIUM
bool "Support magnesium"
+ select CPU_ARM926EJS
config TARGET_APX4DEVKIT
bool "Support apx4devkit"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_XFI3
bool "Support xfi3"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_M28EVK
bool "Support m28evk"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_MX23EVK
bool "Support mx23evk"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_MX28EVK
bool "Support mx28evk"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_MX23_OLINUXINO
bool "Support mx23_olinuxino"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_BG0900
bool "Support bg0900"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_SANSA_FUZE_PLUS
bool "Support sansa_fuze_plus"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_SC_SPS_1
bool "Support sc_sps_1"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config ARCH_NOMADIK
bool "ST-Ericsson Nomadik"
+ select CPU_ARM926EJS
config ORION5X
bool "Marvell Orion"
+ select CPU_ARM926EJS
config TARGET_DKB
bool "Support dkb"
+ select CPU_ARM926EJS
config TARGET_SPEAR300
bool "Support spear300"
+ select CPU_ARM926EJS
config TARGET_SPEAR310
bool "Support spear310"
+ select CPU_ARM926EJS
config TARGET_SPEAR320
bool "Support spear320"
+ select CPU_ARM926EJS
config TARGET_SPEAR600
bool "Support spear600"
+ select CPU_ARM926EJS
config TARGET_X600
bool "Support x600"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config ARCH_VERSATILE
bool "ARM Ltd. Versatile family"
+ select CPU_ARM926EJS
config TARGET_INTEGRATORCP_CM1136
bool "Support integratorcp_cm1136"
+ select CPU_ARM1136
config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
+ select CPU_ARM1136
config TARGET_QONG
bool "Support qong"
+ select CPU_ARM1136
config TARGET_MX31ADS
bool "Support mx31ads"
+ select CPU_ARM1136
config TARGET_MX31PDK
bool "Support mx31pdk"
+ select CPU_ARM1136
+ select SUPPORT_SPL
config TARGET_TT01
bool "Support tt01"
+ select CPU_ARM1136
config TARGET_IMX31_LITEKIT
bool "Support imx31_litekit"
+ select CPU_ARM1136
config TARGET_WOODBURN
bool "Support woodburn"
+ select CPU_ARM1136
config TARGET_WOODBURN_SD
bool "Support woodburn_sd"
+ select CPU_ARM1136
+ select SUPPORT_SPL
config TARGET_FLEA3
bool "Support flea3"
+ select CPU_ARM1136
config TARGET_MX35PDK
bool "Support mx35pdk"
+ select CPU_ARM1136
config TARGET_RPI_B
bool "Support rpi_b"
+ select CPU_ARM1176
config TARGET_TNETV107X_EVM
bool "Support tnetv107x_evm"
+ select CPU_ARM1176
config TARGET_INTEGRATORAP_CM946ES
bool "Support integratorap_cm946es"
+ select CPU_ARM946ES
config TARGET_INTEGRATORCP_CM946ES
bool "Support integratorcp_cm946es"
+ select CPU_ARM946ES
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
+ select CPU_V7
config TARGET_VEXPRESS_CA5X2
bool "Support vexpress_ca5x2"
+ select CPU_V7
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
+ select CPU_V7
config TARGET_KWB
bool "Support kwb"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_TSERIES
bool "Support tseries"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_CM_T335
bool "Support cm_t335"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_PEPPER
bool "Support pepper"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_AM335X_IGEP0033
bool "Support am335x_igep0033"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_PCM051
bool "Support pcm051"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_DRACO
bool "Support draco"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_DXR2
bool "Support dxr2"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_PXM2
bool "Support pxm2"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_RUT
bool "Support rut"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_PENGWYN
bool "Support pengwyn"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_AM335X_EVM
bool "Support am335x_evm"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_TI814X_EVM
bool "Support ti814x_evm"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_TI816X_EVM
bool "Support ti816x_evm"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_SAMA5D3_XPLAINED
bool "Support sama5d3_xplained"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_SAMA5D3XEK
bool "Support sama5d3xek"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
+ select CPU_V7
config TARGET_BCM958300K
bool "Support bcm958300k"
+ select CPU_V7
config TARGET_BCM958622HR
bool "Support bcm958622hr"
+ select CPU_V7
config ARCH_EXYNOS
bool "Samsung EXYNOS"
+ select CPU_V7
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
+ select CPU_V7
config ARCH_HIGHBANK
bool "Calxeda Highbank"
+ select CPU_V7
config ARCH_KEYSTONE
bool "TI Keystone"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_M53EVK
bool "Support m53evk"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_IMA3_MX53
bool "Support ima3-mx53"
+ select CPU_V7
config TARGET_MX51EVK
bool "Support mx51evk"
+ select CPU_V7
config TARGET_MX53ARD
bool "Support mx53ard"
+ select CPU_V7
config TARGET_MX53EVK
bool "Support mx53evk"
+ select CPU_V7
config TARGET_MX53LOCO
bool "Support mx53loco"
+ select CPU_V7
config TARGET_MX53SMD
bool "Support mx53smd"
+ select CPU_V7
config TARGET_MX51_EFIKAMX
bool "Support mx51_efikamx"
+ select CPU_V7
config TARGET_VISION2
bool "Support vision2"
+ select CPU_V7
config TARGET_UDOO
bool "Support udoo"
+ select CPU_V7
config TARGET_WANDBOARD
bool "Support wandboard"
+ select CPU_V7
config TARGET_TITANIUM
bool "Support titanium"
+ select CPU_V7
config TARGET_NITROGEN6X
bool "Support nitrogen6x"
+ select CPU_V7
config TARGET_CGTQMX6EVAL
bool "Support cgtqmx6eval"
+ select CPU_V7
config TARGET_EMBESTMX6BOARDS
bool "Support embestmx6boards"
+ select CPU_V7
config TARGET_ARISTAINETOS
bool "Support aristainetos"
+ select CPU_V7
config TARGET_MX6QARM2
bool "Support mx6qarm2"
+ select CPU_V7
config TARGET_MX6QSABREAUTO
bool "Support mx6qsabreauto"
+ select CPU_V7
config TARGET_MX6SABRESD
bool "Support mx6sabresd"
+ select CPU_V7
config TARGET_MX6SLEVK
bool "Support mx6slevk"
+ select CPU_V7
config TARGET_MX6SXSABRESD
bool "Support mx6sxsabresd"
+ select CPU_V7
config TARGET_GW_VENTANA
bool "Support gw_ventana"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_HUMMINGBOARD
bool "Support hummingboard"
+ select CPU_V7
+
+config TARGET_KOSAGI_NOVENA
+ bool "Support Kosagi Novena"
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
+ select CPU_V7
config TARGET_OT1200
bool "Bachmann OT1200"
+ select CPU_V7
config OMAP34XX
bool "OMAP34XX SoC"
+ select CPU_V7
config OMAP44XX
bool "OMAP44XX SoC"
+ select CPU_V7
+ select SUPPORT_SPL
config OMAP54XX
bool "OMAP54XX SoC"
+ select CPU_V7
+ select SUPPORT_SPL
config RMOBILE
bool "Renesas ARM SoCs"
+ select CPU_V7
config TARGET_CM_FX6
bool "Support cm_fx6"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_SOCFPGA_CYCLONE5
bool "Support socfpga_cyclone5"
+ select CPU_V7
+ select SUPPORT_SPL
-config TARGET_SUN4I
- bool "Support sun4i"
-
-config TARGET_SUN5I
- bool "Support sun5i"
-
-config TARGET_SUN7I
- bool "Support sun7i"
+config ARCH_SUNXI
+ bool "Support sunxi (Allwinner) SoCs"
config TARGET_SNOWBALL
bool "Support snowball"
+ select CPU_V7
config TARGET_U8500_HREF
bool "Support u8500_href"
+ select CPU_V7
config TARGET_VF610TWR
bool "Support vf610twr"
+ select CPU_V7
config ZYNQ
bool "Xilinx Zynq Platform"
+ select CPU_V7
+ select SUPPORT_SPL
config TEGRA
bool "NVIDIA Tegra"
+ select SUPPORT_SPL
select SPL
select OF_CONTROL if !SPL_BUILD
+ select CPU_ARM720T if SPL_BUILD
+ select CPU_V7 if !SPL_BUILD
config TARGET_VEXPRESS_AEMV8A
bool "Support vexpress_aemv8a"
@@ -484,51 +708,70 @@ config TARGET_LS2085A_SIMU
config TARGET_LS1021AQDS
bool "Support ls1021aqds_nor"
+ select CPU_V7
config TARGET_LS1021ATWR
bool "Support ls1021atwr_nor"
+ select CPU_V7
config TARGET_BALLOON3
bool "Support balloon3"
+ select CPU_PXA
config TARGET_H2200
bool "Support h2200"
+ select CPU_PXA
config TARGET_PALMLD
bool "Support palmld"
+ select CPU_PXA
config TARGET_PALMTC
bool "Support palmtc"
+ select CPU_PXA
config TARGET_PALMTREO680
bool "Support palmtreo680"
+ select CPU_PXA
+ select SUPPORT_SPL
config TARGET_PXA255_IDP
bool "Support pxa255_idp"
+ select CPU_PXA
config TARGET_TRIZEPSIV
bool "Support trizepsiv"
+ select CPU_PXA
config TARGET_VPAC270
bool "Support vpac270"
+ select CPU_PXA
+ select SUPPORT_SPL
config TARGET_XAENIAX
bool "Support xaeniax"
+ select CPU_PXA
config TARGET_ZIPITZ2
bool "Support zipitz2"
+ select CPU_PXA
config TARGET_LP8X4X
bool "Support lp8x4x"
+ select CPU_PXA
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
+ select CPU_PXA
config TARGET_JORNADA
bool "Support jornada"
+ select CPU_SA1100
config ARCH_UNIPHIER
bool "Panasonic UniPhier platform"
+ select CPU_V7
+ select SUPPORT_SPL
endchoice
@@ -616,7 +859,6 @@ source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/embest/mx6boards/Kconfig"
-source "board/emk/top9000/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/esd/otc570/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
@@ -653,6 +895,7 @@ source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
+source "board/kosagi/novena/Kconfig"
source "board/logicpd/imx27lite/Kconfig"
source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index 8d3f92cae9..bc98edda7a 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -531,7 +531,7 @@ u32 spl_boot_mode(void)
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c
index 46ed055023..b8d5c785df 100644
--- a/arch/arm/cpu/arm926ejs/at91/led.c
+++ b/arch/arm/cpu/arm926ejs/at91/led.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
+#include <status_led.h>
#ifdef CONFIG_RED_LED
void red_led_on(void)
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index e86c2edd3b..8d7873c9af 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -99,7 +99,4 @@ void flush_cache(unsigned long start, unsigned long size)
/*
* Stub implementations for l2 cache operations
*/
-void __l2_cache_disable(void) {}
-
-void l2_cache_disable(void)
- __attribute__((weak, alias("__l2_cache_disable")));
+__weak void l2_cache_disable(void) {}
diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/cpu/arm926ejs/davinci/Kconfig
index 4c18ab631e..613f04d8b0 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Kconfig
+++ b/arch/arm/cpu/arm926ejs/davinci/Kconfig
@@ -8,18 +8,22 @@ config TARGET_ENBW_CMC
config TARGET_IPAM390
bool "IPAM390 board"
+ select SUPPORT_SPL
config TARGET_DA830EVM
bool "DA830 EVM board"
config TARGET_DA850EVM
bool "DA850 EVM board"
+ select SUPPORT_SPL
config TARGET_CAM_ENC_4XX
bool "CAM ENC 4xx board"
+ select SUPPORT_SPL
config TARGET_HAWKBOARD
bool "Hawkboard"
+ select SUPPORT_SPL
config TARGET_DAVINCI_DM355EVM
bool "DM355 EVM board"
@@ -53,9 +57,6 @@ config TARGET_CALIMAIN
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "davinci"
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
index 91ffedf732..6c037a16c9 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
@@ -59,9 +59,6 @@ config TARGET_GOFLEXHOME
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "kirkwood"
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 365542fe0b..ef130aea42 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -83,7 +83,9 @@ void mx28_fixup_vt(uint32_t start_addr)
int i;
for (i = 0; i < 8; i++) {
+ /* cppcheck-suppress nullPointer */
vt[i] = ldr_pc;
+ /* cppcheck-suppress nullPointer */
vt[i + 8] = start_addr + (4 * i);
}
}
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index d3e136991a..d29b9aaf3d 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -118,6 +118,8 @@ static void mxs_spl_fixup_vectors(void)
* fine.
*/
extern uint32_t _start;
+
+ /* cppcheck-suppress nullPointer */
memcpy(0x0, &_start, 0x60);
}
diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c
index 99d3fb8731..f2e72257d1 100644
--- a/arch/arm/cpu/arm926ejs/mxs/timer.c
+++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -91,6 +91,8 @@ unsigned long long get_ticks(void)
TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
#elif defined(CONFIG_MX28)
now = readl(&timrot_regs->hw_timrot_running_count0);
+#else
+#error "Don't know how to read timrot_regs"
#endif
if (lastdec >= now) {
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Kconfig b/arch/arm/cpu/arm926ejs/nomadik/Kconfig
index eda51fdc37..265f336469 100644
--- a/arch/arm/cpu/arm926ejs/nomadik/Kconfig
+++ b/arch/arm/cpu/arm926ejs/nomadik/Kconfig
@@ -8,9 +8,6 @@ config NOMADIK_NHK8815
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "nomadik"
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/cpu/arm926ejs/orion5x/Kconfig
index 2d0ab2be17..5a542629c7 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/Kconfig
+++ b/arch/arm/cpu/arm926ejs/orion5x/Kconfig
@@ -8,9 +8,6 @@ config TARGET_EDMINIV2
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "orion5x"
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 3757ffb2c2..697e0945d7 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -38,7 +38,7 @@ int arch_cpu_init(void)
#if defined(CONFIG_DW_UDC)
periph1_clken |= MISC_USBDENB;
#endif
-#if defined(CONFIG_DW_I2C)
+#if defined(CONFIG_SYS_I2C_DW)
periph1_clken |= MISC_I2CENB;
#endif
#if defined(CONFIG_ST_SMI)
diff --git a/arch/arm/cpu/arm926ejs/versatile/Kconfig b/arch/arm/cpu/arm926ejs/versatile/Kconfig
index 35c16d876c..d2e76f4afc 100644
--- a/arch/arm/cpu/arm926ejs/versatile/Kconfig
+++ b/arch/arm/cpu/arm926ejs/versatile/Kconfig
@@ -1,8 +1,5 @@
if ARCH_VERSATILE
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "versatile"
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 828d10bb5a..29b1d73438 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -9,7 +9,9 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
+#include <ns16550.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
@@ -36,6 +38,63 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+ { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+ { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+ { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+ { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+ { "gpio_omap", &am33xx_gpio[0] },
+ { "gpio_omap", &am33xx_gpio[1] },
+ { "gpio_omap", &am33xx_gpio[2] },
+ { "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+ { "gpio_omap", &am33xx_gpio[4] },
+ { "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+
+# ifndef CONFIG_OF_CONTROL
+/*
+ * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
+ * the CONFIGs. At the same time, we should move this to the board files.
+ */
+static const struct ns16550_platdata am33xx_serial[] = {
+ { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
+# ifdef CONFIG_SYS_NS16550_COM2
+ { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
+# ifdef CONFIG_SYS_NS16550_COM3
+ { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
+ { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
+ { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
+ { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
+# endif
+# endif
+};
+
+U_BOOT_DEVICES(am33xx_uarts) = {
+ { "serial_omap", &am33xx_serial[0] },
+# ifdef CONFIG_SYS_NS16550_COM2
+ { "serial_omap", &am33xx_serial[1] },
+# ifdef CONFIG_SYS_NS16550_COM3
+ { "serial_omap", &am33xx_serial[2] },
+ { "serial_omap", &am33xx_serial[3] },
+ { "serial_omap", &am33xx_serial[4] },
+ { "serial_omap", &am33xx_serial[5] },
+# endif
+# endif
+};
+# endif
+
+#else
+
static const struct gpio_bank gpio_bank_am33xx[] = {
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -49,6 +108,8 @@ static const struct gpio_bank gpio_bank_am33xx[] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+#endif
+
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int cpu_mmc_init(bd_t *bis)
{
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 2ce682f6b1..781d83fc72 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -18,6 +18,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <power/tps65910.h>
+#include <linux/compiler.h>
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
@@ -51,11 +52,11 @@ u32 get_cpu_type(void)
/**
* get_board_rev() - setup to pass kernel board revision information
- * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ * returns: 0 for the ATAG REVISION tag value.
*/
-u32 get_board_rev(void)
+u32 __weak get_board_rev(void)
{
- return BOARD_REV_ID;
+ return 0;
}
/**
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index 7a0d182e5f..090be9383f 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -4,6 +4,7 @@ choice
prompt "EXYNOS board select"
config TARGET_SMDKV310
+ select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
select OF_CONTROL if !SPL_BUILD
@@ -15,6 +16,7 @@ config TARGET_S5PC210_UNIVERSAL
config TARGET_ORIGEN
bool "Exynos4412 Origen board"
+ select SUPPORT_SPL
config TARGET_TRATS2
bool "Exynos4412 Trat2 board"
@@ -24,29 +26,31 @@ config TARGET_ODROID
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_SMDK5250
bool "SMDK5250 board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_SNOW
bool "Snow board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_SMDK5420
bool "SMDK5420 board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_PEACH_PIT
bool "Peach Pi board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "exynos"
diff --git a/arch/arm/cpu/armv7/highbank/Kconfig b/arch/arm/cpu/armv7/highbank/Kconfig
index 29ff99511c..0e73c04142 100644
--- a/arch/arm/cpu/armv7/highbank/Kconfig
+++ b/arch/arm/cpu/armv7/highbank/Kconfig
@@ -1,8 +1,5 @@
if ARCH_HIGHBANK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "highbank"
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig
index 8249b5e270..134ae87fe1 100644
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ b/arch/arm/cpu/armv7/keystone/Kconfig
@@ -9,10 +9,10 @@ config TARGET_K2HK_EVM
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
-endchoice
+config TARGET_K2L_EVM
+ bool "TI Keystone 2 Lamar EVM"
-config SYS_CPU
- default "armv7"
+endchoice
config SYS_SOC
default "keystone"
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
index f8519c0403..ed030db2c8 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -10,10 +10,9 @@ obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
+obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
-obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
obj-y += msmc.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
-obj-y += ddr3.o
+obj-y += ddr3.o cmd_ddr3.o
obj-y += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/cpu/armv7/keystone/clock-k2l.c
new file mode 100644
index 0000000000..1c5e4d54d8
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2l.c
@@ -0,0 +1,138 @@
+/*
+ * Keystone2: get clk rate for K2L
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+int dev_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+int arm_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD800,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) >>
+ PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3_PLL:
+ ret = external_clk[ddr3_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+ if (!(tmp & PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+ output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
+ case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
+ case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
+ case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
+ case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
+ case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
+ case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
+ case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
+ case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
+ case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
+ case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
+ case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
+ case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
+ case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
+ default:
+ break;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index 47fc89398d..d13fbc1a4b 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data)
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
- /* set PLL Select (bit 13) for PASS PLL */
- if (data->pll == PASS_PLL)
- tmp |= PLLCTL_PAPLL;
-
__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/* Reset bit: bit 14 for both DDR3 & PASS PLL */
@@ -261,3 +257,16 @@ inline int get_max_arm_speed(void)
return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
}
#endif
+
+void pass_pll_pa_clk_enable(void)
+{
+ u32 reg;
+
+ reg = readl(keystone_pll_regs[PASS_PLL].reg1);
+
+ reg |= PLLCTL_PAPLL;
+ writel(reg, keystone_pll_regs[PASS_PLL].reg1);
+
+ /* wait till clock is enabled */
+ sdelay(15000);
+}
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index d97c95be11..af1b701e82 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -58,20 +58,11 @@ pll_cmd_usage:
return cmd_usage(cmdtp);
}
-#ifdef CONFIG_SOC_K2HK
-U_BOOT_CMD(
- pllset, 5, 0, do_pll_cmd,
- "set pll multiplier and pre divider",
- "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
-);
-#endif
-#ifdef CONFIG_SOC_K2E
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
- "<pa|ddr3> <mult> <div> <OD>\n"
+ PLLSET_CMD_LIST " <mult> <div> <OD>\n"
);
-#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -95,12 +86,8 @@ U_BOOT_CMD(
getclk, 2, 0, do_getclk_cmd,
"get clock rate",
"<clk index>\n"
-#ifdef CONFIG_SOC_K2HK
- "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
-#endif
-#ifdef CONFIG_SOC_K2E
- "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
-#endif
+ "The indexes for clocks:\n"
+ CLOCK_INDEXES_LIST
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -141,5 +128,8 @@ U_BOOT_CMD(
psc, 3, 0, do_psc_cmd,
"<enable/disable psc module os disable domain>",
"<mod/domain index> <en|di|domain>\n"
- "See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
+ "Intended to control Power and Sleep Controller (PSC) domains and\n"
+ "modules. The module or domain index exectly corresponds to ones\n"
+ "listed in official TRM. For instance, to enable MSMC RAM clock\n"
+ "domain use command: psc 14 en.\n"
);
diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
new file mode 100644
index 0000000000..ea78ad8fd5
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
@@ -0,0 +1,248 @@
+/*
+ * Keystone2: DDR3 test commands
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr3.h>
+#include <common.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
+
+#define DDR_REMAP_ADDR 0x80000000
+#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
+
+#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
+ CONFIG_STACKSIZE) >> 17) - 2)
+
+#define DDR_TEST_BURST_SIZE 1024
+
+static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
+{
+ u32 index_start, value, index;
+
+ index_start = start_address;
+
+ while (1) {
+ /* Write a pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4)
+ __raw_writel(index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4) {
+ value = __raw_readl(index);
+ if (value != index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+
+ if (quick)
+ continue;
+
+ /* Write a pattern for complementary values */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4)
+ __raw_writel((u32)~index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4) {
+ value = __raw_readl(index);
+ if (value != ~index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+
+ /* Write a pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 2)
+ __raw_writew((u16)index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 2) {
+ value = __raw_readw(index);
+ if (value != (u16)index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readw(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+
+ /* Write a pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 1)
+ __raw_writeb((u8)index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 1) {
+ value = __raw_readb(index);
+ if (value != (u8)index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readb(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+ }
+
+ puts("ddr memory test PASSED!\n");
+ return 0;
+}
+
+static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
+{
+ u32 index, value, index2, value2;
+
+ for (index = address1, index2 = address2;
+ index < address1 + size;
+ index += 4, index2 += 4) {
+ value = __raw_readl(index);
+ value2 = __raw_readl(index2);
+
+ if (value != value2) {
+ printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
+ index, value, index2, value2);
+
+ return -1;
+ }
+ }
+
+ puts("ddr memory compare PASSED!\n");
+ return 0;
+}
+
+static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
+{
+ u32 value1, value2, value3;
+
+ puts("Disabling DDR ECC ...\n");
+ ddr3_disable_ecc(base);
+
+ value1 = __raw_readl(address);
+ value2 = value1 ^ ecc_err;
+ __raw_writel(value2, address);
+
+ value3 = __raw_readl(address);
+ printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
+ address, value1, value2, ecc_err, value3);
+
+ __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
+ base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+
+ puts("Enabling DDR ECC ...\n");
+ ddr3_enable_ecc(base, 1);
+
+ value1 = __raw_readl(address);
+ printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
+
+ ddr3_check_ecc_int(base);
+ return 0;
+}
+
+static int do_ddr_test(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ u32 start_addr, end_addr, size, ecc_err;
+
+ if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
+ if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
+ puts("ECC RMW isn't supported for this SOC\n");
+ return 1;
+ }
+
+ start_addr = simple_strtoul(argv[2], NULL, 16);
+ ecc_err = simple_strtoul(argv[3], NULL, 16);
+
+ if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
+ (start_addr > (CONFIG_SYS_SDRAM_BASE +
+ CONFIG_MAX_RAM_BANK_SIZE - 1))) {
+ puts("Invalid address!\n");
+ return cmd_usage(cmdtp);
+ }
+
+ ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
+ start_addr, ecc_err);
+ return 0;
+ }
+
+ if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
+ ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
+ return cmd_usage(cmdtp);
+
+ start_addr = simple_strtoul(argv[2], NULL, 16);
+ end_addr = simple_strtoul(argv[3], NULL, 16);
+
+ if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
+ (start_addr > (CONFIG_SYS_SDRAM_BASE +
+ CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
+ (end_addr < CONFIG_SYS_SDRAM_BASE) ||
+ (end_addr > (CONFIG_SYS_SDRAM_BASE +
+ CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
+ puts("Invalid start or end address!\n");
+ return cmd_usage(cmdtp);
+ }
+
+ puts("Please wait ...\n");
+ if (argc == 5) {
+ size = simple_strtoul(argv[4], NULL, 16);
+ ddr_memory_compare(start_addr, end_addr, size);
+ } else {
+ ddr_memory_test(start_addr, end_addr, 0);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(ddr, 5, 1, do_ddr_test,
+ "DDR3 test",
+ "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
+ " address to end address\n"
+ "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
+ " compare DDR data of (size) bytes from start address to end\n"
+ " address\n"
+ "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
+ " in DDR data at <addr>, the command will read a 32-bit data\n"
+ " from <addr>, and write (data ^ bit_err) back to <addr>\n"
+);
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index 2eabec10f9..923906afb5 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -9,9 +9,19 @@
#include <asm/io.h>
#include <common.h>
+#include <asm/arch/msmc.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/psc_defs.h>
+#include <asm/ti-common/ti-edma3.h>
+
+#define DDR3_EDMA_BLK_SIZE_SHIFT 10
+#define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
+#define DDR3_EDMA_BCNT 0x8000
+#define DDR3_EDMA_CCNT 1
+#define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
+#define DDR3_EDMA_SLOT_NUM 1
+
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
@@ -70,6 +80,240 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
+int ddr3_ecc_support_rmw(u32 base)
+{
+ u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
+
+ /* Check the DDR3 controller ID reg if the controllers
+ supports ECC RMW or not */
+ if (value == 0x40461C02)
+ return 1;
+
+ return 0;
+}
+
+static void ddr3_ecc_config(u32 base, u32 value)
+{
+ u32 data;
+
+ __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
+ udelay(100000); /* delay required to synchronize across clock domains */
+
+ if (value & KS2_DDR3_ECC_EN) {
+ /* Clear the 1-bit error count */
+ data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+ __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+
+ /* enable the ECC interrupt */
+ __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+ KS2_DDR3_WR_ECC_ERR_SYS,
+ base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
+
+ /* Clear the ECC error interrupt status */
+ __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+ KS2_DDR3_WR_ECC_ERR_SYS,
+ base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+ }
+}
+
+static void ddr3_reset_data(u32 base, u32 ddr3_size)
+{
+ u32 mpax[2];
+ u32 seg_num;
+ u32 seg, blks, dst, edma_blks;
+ struct edma3_slot_config slot;
+ struct edma3_channel_config edma_channel;
+ u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
+
+ /* Setup an edma to copy the 1k block to the entire DDR */
+ puts("\nClear entire DDR3 memory to enable ECC\n");
+
+ /* save the SES MPAX regs */
+ msmc_get_ses_mpax(8, 0, mpax);
+
+ /* setup edma slot 1 configuration */
+ slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+ EDMA3_SLOPT_COMP_CODE(0) |
+ EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+ slot.bcnt = DDR3_EDMA_BCNT;
+ slot.acnt = DDR3_EDMA_BLK_SIZE;
+ slot.ccnt = DDR3_EDMA_CCNT;
+ slot.src_bidx = 0;
+ slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
+ slot.src_cidx = 0;
+ slot.dst_cidx = 0;
+ slot.link = EDMA3_PARSET_NULL_LINK;
+ slot.bcntrld = 0;
+ edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
+
+ /* configure quik edma channel */
+ edma_channel.slot = DDR3_EDMA_SLOT_NUM;
+ edma_channel.chnum = 0;
+ edma_channel.complete_code = 0;
+ /* event trigger after dst update */
+ edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+ qedma3_start(KS2_EDMA0_BASE, &edma_channel);
+
+ /* DDR3 size in segments (4KB seg size) */
+ seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
+
+ for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
+ /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
+ access slave interface so that edma driver can access */
+ msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
+ KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
+
+ if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
+ edma_blks = KS2_MSMC_MAP_SEG_NUM <<
+ (KS2_MSMC_SEG_SIZE_SHIFT
+ - DDR3_EDMA_BLK_SIZE_SHIFT);
+ else
+ edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
+ - DDR3_EDMA_BLK_SIZE_SHIFT);
+
+ /* Use edma driver to scrub 2GB DDR memory */
+ for (dst = base, blks = 0; blks < edma_blks;
+ blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
+ edma3_set_src_addr(KS2_EDMA0_BASE,
+ edma_channel.slot, (u32)edma_src);
+ edma3_set_dest_addr(KS2_EDMA0_BASE,
+ edma_channel.slot, (u32)dst);
+
+ while (edma3_check_for_transfer(KS2_EDMA0_BASE,
+ &edma_channel))
+ udelay(10);
+ }
+ }
+
+ qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
+
+ /* restore the SES MPAX regs */
+ msmc_set_ses_mpax(8, 0, mpax);
+}
+
+static void ddr3_ecc_init_range(u32 base)
+{
+ u32 ecc_val = KS2_DDR3_ECC_EN;
+ u32 rmw = ddr3_ecc_support_rmw(base);
+
+ if (rmw)
+ ecc_val |= KS2_DDR3_ECC_RMW_EN;
+
+ __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+
+ ddr3_ecc_config(base, ecc_val);
+}
+
+void ddr3_enable_ecc(u32 base, int test)
+{
+ u32 ecc_val = KS2_DDR3_ECC_ENABLE;
+ u32 rmw = ddr3_ecc_support_rmw(base);
+
+ if (test)
+ ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
+
+ if (!rmw) {
+ if (!test)
+ /* by default, disable ecc when rmw = 0 and no
+ ecc test */
+ ecc_val = 0;
+ } else {
+ ecc_val |= KS2_DDR3_ECC_RMW_EN;
+ }
+
+ ddr3_ecc_config(base, ecc_val);
+}
+
+void ddr3_disable_ecc(u32 base)
+{
+ ddr3_ecc_config(base, 0);
+}
+
+#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
+static void cic_init(u32 base)
+{
+ /* Disable CIC global interrupts */
+ __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
+
+ /* Set to normal mode, no nesting, no priority hold */
+ __raw_writel(0, base + KS2_CIC_CTRL);
+ __raw_writel(0, base + KS2_CIC_HOST_CTRL);
+
+ /* Enable CIC global interrupts */
+ __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
+}
+
+static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
+{
+ /* Map the system interrupt to a CIC channel */
+ __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
+
+ /* Enable CIC system interrupt */
+ __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
+
+ /* Enable CIC Host interrupt */
+ __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
+}
+
+static void ddr3_map_ecc_cic2_irq(u32 base)
+{
+ cic_init(base);
+ cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
+ KS2_CIC2_DDR3_ECC_IRQ_NUM);
+}
+#endif
+
+void ddr3_init_ecc(u32 base)
+{
+ u32 ddr3_size;
+
+ if (!ddr3_ecc_support_rmw(base)) {
+ ddr3_disable_ecc(base);
+ return;
+ }
+
+ ddr3_ecc_init_range(base);
+ ddr3_size = ddr3_get_size();
+ ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
+
+ /* mapping DDR3 ECC system interrupt from CIC2 to GIC */
+#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
+ ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
+#endif
+ ddr3_enable_ecc(base, 0);
+}
+
+void ddr3_check_ecc_int(u32 base)
+{
+ char *env;
+ int ecc_test = 0;
+ u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+
+ env = getenv("ecc_test");
+ if (env)
+ ecc_test = simple_strtol(env, NULL, 0);
+
+ if (value & KS2_DDR3_WR_ECC_ERR_SYS)
+ puts("DDR3 ECC write error interrupted\n");
+
+ if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
+ puts("DDR3 ECC 2-bit error interrupted\n");
+
+ if (!ecc_test) {
+ puts("Reseting the device ...\n");
+ reset_cpu(0);
+ }
+ }
+
+ value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+ if (value) {
+ printf("1-bit ECC err count: 0x%x\n", value);
+ value = __raw_readl(base +
+ KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
+ printf("1-bit ECC err address log: 0x%x\n", value);
+ }
+}
+
void ddr3_reset_ddrphy(void)
{
u32 tmp;
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index a8f8aee8ab..c2b947839d 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -13,6 +13,7 @@
#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/psc_defs.h>
void chip_configuration_unlock(void)
{
@@ -20,17 +21,67 @@ void chip_configuration_unlock(void)
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+ u32 i;
+ u32 j;
+ u32 val;
+ u32 base = KS2_OSR_CFG_BASE;
+ u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+ /* Enable the OSR clock domain */
+ psc_enable_module(KS2_LPSC_OSR);
+
+ /* Disable OSR ECC check for all the ram banks */
+ for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
+ val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+ (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+ writel(val , base + KS2_OSR_ECC_VEC);
+
+ /**
+ * wait till read is done.
+ * Print should be added after earlyprintk support is added.
+ */
+ for (j = 0; j < 10000; j++) {
+ val = readl(base + KS2_OSR_ECC_VEC);
+ if (val & KS2_OSR_ECC_VEC_RD_DONE)
+ break;
+ }
+
+ ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+ KS2_OSR_ECC_CTRL_CHK;
+
+ writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+ writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+ }
+
+ /* Reset OSR memory to all zeros */
+ for (i = 0; i < KS2_OSR_SIZE; i += 4)
+ writel(0, KS2_OSR_DATA_BASE + i);
+
+ /* Enable OSR ECC check for all the ram banks */
+ for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
+ writel(ecc_ctrl[i] |
+ KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
icache_enable();
- msmc_share_all_segments(8); /* TETRIS */
- msmc_share_all_segments(9); /* NETCP */
- msmc_share_all_segments(10); /* QM PDSP */
- msmc_share_all_segments(11); /* PCIE 0 */
-#ifdef CONFIG_SOC_K2E
- msmc_share_all_segments(13); /* PCIE 1 */
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+#endif
+#ifdef CONFIG_SOC_K2L
+ osr_init();
#endif
/*
diff --git a/arch/arm/cpu/armv7/keystone/keystone_nav.c b/arch/arm/cpu/armv7/keystone/keystone_nav.c
deleted file mode 100644
index 39d6f995f7..0000000000
--- a/arch/arm/cpu/armv7/keystone/keystone_nav.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * Multicore Navigator driver for TI Keystone 2 devices.
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/keystone_nav.h>
-
-static int soc_type =
-#ifdef CONFIG_SOC_K2HK
- k2hk;
-#endif
-
-struct qm_config k2hk_qm_memmap = {
- .stat_cfg = 0x02a40000,
- .queue = (struct qm_reg_queue *)0x02a80000,
- .mngr_vbusm = 0x23a80000,
- .i_lram = 0x00100000,
- .proxy = (struct qm_reg_queue *)0x02ac0000,
- .status_ram = 0x02a06000,
- .mngr_cfg = (struct qm_cfg_reg *)0x02a02000,
- .intd_cfg = 0x02a0c000,
- .desc_mem = (struct descr_mem_setup_reg *)0x02a03000,
- .region_num = 64,
- .pdsp_cmd = 0x02a20000,
- .pdsp_ctl = 0x02a0f000,
- .pdsp_iram = 0x02a10000,
- .qpool_num = 4000,
-};
-
-/*
- * We are going to use only one type of descriptors - host packet
- * descriptors. We staticaly allocate memory for them here
- */
-struct qm_host_desc desc_pool[HDESC_NUM] __aligned(sizeof(struct qm_host_desc));
-
-static struct qm_config *qm_cfg;
-
-inline int num_of_desc_to_reg(int num_descr)
-{
- int j, num;
-
- for (j = 0, num = 32; j < 15; j++, num *= 2) {
- if (num_descr <= num)
- return j;
- }
-
- return 15;
-}
-
-static int _qm_init(struct qm_config *cfg)
-{
- u32 j;
-
- if (cfg == NULL)
- return QM_ERR;
-
- qm_cfg = cfg;
-
- qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram;
- qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8;
- qm_cfg->mngr_cfg->link_ram_base1 = 0;
- qm_cfg->mngr_cfg->link_ram_size1 = 0;
- qm_cfg->mngr_cfg->link_ram_base2 = 0;
-
- qm_cfg->desc_mem[0].base_addr = (u32)desc_pool;
- qm_cfg->desc_mem[0].start_idx = 0;
- qm_cfg->desc_mem[0].desc_reg_size =
- (((sizeof(struct qm_host_desc) >> 4) - 1) << 16) |
- num_of_desc_to_reg(HDESC_NUM);
-
- memset(desc_pool, 0, sizeof(desc_pool));
- for (j = 0; j < HDESC_NUM; j++)
- qm_push(&desc_pool[j], qm_cfg->qpool_num);
-
- return QM_OK;
-}
-
-int qm_init(void)
-{
- switch (soc_type) {
- case k2hk:
- return _qm_init(&k2hk_qm_memmap);
- }
-
- return QM_ERR;
-}
-
-void qm_close(void)
-{
- u32 j;
-
- if (qm_cfg == NULL)
- return;
-
- queue_close(qm_cfg->qpool_num);
-
- qm_cfg->mngr_cfg->link_ram_base0 = 0;
- qm_cfg->mngr_cfg->link_ram_size0 = 0;
- qm_cfg->mngr_cfg->link_ram_base1 = 0;
- qm_cfg->mngr_cfg->link_ram_size1 = 0;
- qm_cfg->mngr_cfg->link_ram_base2 = 0;
-
- for (j = 0; j < qm_cfg->region_num; j++) {
- qm_cfg->desc_mem[j].base_addr = 0;
- qm_cfg->desc_mem[j].start_idx = 0;
- qm_cfg->desc_mem[j].desc_reg_size = 0;
- }
-
- qm_cfg = NULL;
-}
-
-void qm_push(struct qm_host_desc *hd, u32 qnum)
-{
- u32 regd;
-
- if (!qm_cfg)
- return;
-
- cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
- regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
- writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
-}
-
-void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
- void *buff_ptr, u32 buff_len)
-{
- hd->orig_buff_len = buff_len;
- hd->buff_len = buff_len;
- hd->orig_buff_ptr = (u32)buff_ptr;
- hd->buff_ptr = (u32)buff_ptr;
- qm_push(hd, qnum);
-}
-
-struct qm_host_desc *qm_pop(u32 qnum)
-{
- u32 uhd;
-
- if (!qm_cfg)
- return NULL;
-
- uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
- if (uhd)
- cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
-
- return (struct qm_host_desc *)uhd;
-}
-
-struct qm_host_desc *qm_pop_from_free_pool(void)
-{
- if (!qm_cfg)
- return NULL;
-
- return qm_pop(qm_cfg->qpool_num);
-}
-
-void queue_close(u32 qnum)
-{
- struct qm_host_desc *hd;
-
- while ((hd = qm_pop(qnum)))
- ;
-}
-
-/*
- * DMA API
- */
-
-struct pktdma_cfg k2hk_netcp_pktdma = {
- .global = (struct global_ctl_regs *)0x02004000,
- .tx_ch = (struct tx_chan_regs *)0x02004400,
- .tx_ch_num = 9,
- .rx_ch = (struct rx_chan_regs *)0x02004800,
- .rx_ch_num = 26,
- .tx_sched = (u32 *)0x02004c00,
- .rx_flows = (struct rx_flow_regs *)0x02005000,
- .rx_flow_num = 32,
- .rx_free_q = 4001,
- .rx_rcv_q = 4002,
- .tx_snd_q = 648,
-};
-
-struct pktdma_cfg *netcp;
-
-static int netcp_rx_disable(void)
-{
- u32 j, v, k;
-
- for (j = 0; j < netcp->rx_ch_num; j++) {
- v = readl(&netcp->rx_ch[j].cfg_a);
- if (!(v & CPDMA_CHAN_A_ENABLE))
- continue;
-
- writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a);
- for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
- udelay(100);
- v = readl(&netcp->rx_ch[j].cfg_a);
- if (!(v & CPDMA_CHAN_A_ENABLE))
- continue;
- }
- /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
- }
-
- /* Clear all of the flow registers */
- for (j = 0; j < netcp->rx_flow_num; j++) {
- writel(0, &netcp->rx_flows[j].control);
- writel(0, &netcp->rx_flows[j].tags);
- writel(0, &netcp->rx_flows[j].tag_sel);
- writel(0, &netcp->rx_flows[j].fdq_sel[0]);
- writel(0, &netcp->rx_flows[j].fdq_sel[1]);
- writel(0, &netcp->rx_flows[j].thresh[0]);
- writel(0, &netcp->rx_flows[j].thresh[1]);
- writel(0, &netcp->rx_flows[j].thresh[2]);
- }
-
- return QM_OK;
-}
-
-static int netcp_tx_disable(void)
-{
- u32 j, v, k;
-
- for (j = 0; j < netcp->tx_ch_num; j++) {
- v = readl(&netcp->tx_ch[j].cfg_a);
- if (!(v & CPDMA_CHAN_A_ENABLE))
- continue;
-
- writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a);
- for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
- udelay(100);
- v = readl(&netcp->tx_ch[j].cfg_a);
- if (!(v & CPDMA_CHAN_A_ENABLE))
- continue;
- }
- /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
- }
-
- return QM_OK;
-}
-
-static int _netcp_init(struct pktdma_cfg *netcp_cfg,
- struct rx_buff_desc *rx_buffers)
-{
- u32 j, v;
- struct qm_host_desc *hd;
- u8 *rx_ptr;
-
- if (netcp_cfg == NULL || rx_buffers == NULL ||
- rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
- return QM_ERR;
-
- netcp = netcp_cfg;
- netcp->rx_flow = rx_buffers->rx_flow;
-
- /* init rx queue */
- rx_ptr = rx_buffers->buff_ptr;
-
- for (j = 0; j < rx_buffers->num_buffs; j++) {
- hd = qm_pop(qm_cfg->qpool_num);
- if (hd == NULL)
- return QM_ERR;
-
- qm_buff_push(hd, netcp->rx_free_q,
- rx_ptr, rx_buffers->buff_len);
-
- rx_ptr += rx_buffers->buff_len;
- }
-
- netcp_rx_disable();
-
- /* configure rx channels */
- v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q);
- writel(v, &netcp->rx_flows[netcp->rx_flow].control);
- writel(0, &netcp->rx_flows[netcp->rx_flow].tags);
- writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel);
-
- v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0,
- netcp->rx_free_q);
-
- writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]);
- writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]);
- writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]);
- writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]);
- writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]);
-
- for (j = 0; j < netcp->rx_ch_num; j++)
- writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a);
-
- /* configure tx channels */
- /* Disable loopback in the tx direction */
- writel(0, &netcp->global->emulation_control);
-
-/* TODO: make it dependend on a soc type variable */
-#ifdef CONFIG_SOC_K2HK
- /* Set QM base address, only for K2x devices */
- writel(0x23a80000, &netcp->global->qm_base_addr[0]);
-#endif
-
- /* Enable all channels. The current state isn't important */
- for (j = 0; j < netcp->tx_ch_num; j++) {
- writel(0, &netcp->tx_ch[j].cfg_b);
- writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a);
- }
-
- return QM_OK;
-}
-
-int netcp_init(struct rx_buff_desc *rx_buffers)
-{
- switch (soc_type) {
- case k2hk:
- _netcp_init(&k2hk_netcp_pktdma, rx_buffers);
- return QM_OK;
- }
- return QM_ERR;
-}
-
-int netcp_close(void)
-{
- if (!netcp)
- return QM_ERR;
-
- netcp_tx_disable();
- netcp_rx_disable();
-
- queue_close(netcp->rx_free_q);
- queue_close(netcp->rx_rcv_q);
- queue_close(netcp->tx_snd_q);
-
- return QM_OK;
-}
-
-int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
-{
- struct qm_host_desc *hd;
-
- hd = qm_pop(qm_cfg->qpool_num);
- if (hd == NULL)
- return QM_ERR;
-
- hd->desc_info = num_bytes;
- hd->swinfo[2] = swinfo2;
- hd->packet_info = qm_cfg->qpool_num;
-
- qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes);
-
- return QM_OK;
-}
-
-void *netcp_recv(u32 **pkt, int *num_bytes)
-{
- struct qm_host_desc *hd;
-
- hd = qm_pop(netcp->rx_rcv_q);
- if (!hd)
- return NULL;
-
- *pkt = (u32 *)hd->buff_ptr;
- *num_bytes = hd->desc_info & 0x3fffff;
-
- return hd;
-}
-
-void netcp_release_rxhd(void *hd)
-{
- struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
-
- _hd->buff_len = _hd->orig_buff_len;
- _hd->buff_ptr = _hd->orig_buff_ptr;
-
- qm_push(_hd, netcp->rx_free_q);
-}
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index 7d8e5978df..7899141d54 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -66,3 +66,29 @@ void msmc_share_all_segments(int priv_id)
msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
}
}
+
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc->ses[priv_id][ses_pair].mpaxh = src_pfn << 12 |
+ (size & 0x1f) | 0x80;
+ msmc->ses[priv_id][ses_pair].mpaxl = dst_pfn << 8 | 0x3f;
+}
+
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ *mpax++ = msmc->ses[priv_id][ses_pair].mpaxl;
+ *mpax = msmc->ses[priv_id][ses_pair].mpaxh;
+}
+
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc->ses[priv_id][ses_pair].mpaxl = *mpax++;
+ msmc->ses[priv_id][ses_pair].mpaxh = *mpax;
+}
diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c
deleted file mode 100644
index d4b0e9b163..0000000000
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * common spl init code
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <spl.h>
-#include <spi_flash.h>
-
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_K2HK_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_799,
- TETRIS_PLL_500,
-};
-#endif
-
-#ifdef CONFIG_K2E_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_800,
-};
-#endif
-
-void spl_init_keystone_plls(void)
-{
- init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
-}
-
-void spl_board_init(void)
-{
- spl_init_keystone_plls();
- preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
-#if defined(CONFIG_SPL_SPI_LOAD)
- return BOOT_DEVICE_SPI;
-#else
- puts("Unknown boot device\n");
- hang();
-#endif
-}
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index d200531030..6c9c78c11a 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -312,6 +312,10 @@ static u32 get_ipg_per_clk(void)
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+ if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+ return MXC_HCLK; /* OSC 24Mhz */
+#endif
perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1);
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 6352422253..affbf7f702 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <asm/armv7.h>
+#include <asm/bootm.h>
#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
@@ -20,6 +21,7 @@
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
+#include <asm/bootm.h>
enum ldo_reg {
LDO_ARM,
@@ -238,6 +240,18 @@ static void clear_mmdc_ch_mask(void)
writel(0, &mxc_ccm->ccdr);
}
+#ifdef CONFIG_MX6SL
+static void set_preclk_from_osc(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
+ writel(reg, &mxc_ccm->cscmr1);
+}
+#endif
+
int arch_cpu_init(void)
{
init_aips();
@@ -253,6 +267,11 @@ int arch_cpu_init(void)
if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
set_ahb_rate(132000000);
+ /* Set perclk to source from OSC 24MHz */
+#if defined(CONFIG_MX6SL)
+ set_preclk_from_osc();
+#endif
+
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 3033564760..fb535eb9ec 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -81,8 +81,8 @@ u32 spl_boot_mode(void)
if (val == MMCSD_MODE_RAW)
return MMCSD_MODE_RAW;
- else if (val == MMCSD_MODE_FAT)
- return MMCSD_MODE_FAT;
+ else if (val == MMCSD_MODE_FS)
+ return MMCSD_MODE_FS;
else
#ifdef CONFIG_SUPPORT_EMMC_BOOT
return MMCSD_MODE_EMMCBOOT;
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 6fae1e5f36..a029379a4f 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -5,57 +5,74 @@ choice
config TARGET_AM3517_EVM
bool "AM3517 EVM"
+ select SUPPORT_SPL
config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
+ select SUPPORT_SPL
config TARGET_OMAP3_SDP3430
bool "TI OMAP3430 SDP"
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
+ select SUPPORT_SPL
config TARGET_CM_T35
- bool "CompuLab CM-T35"
+ bool "CompuLab CM-T3530 and CM-T3730 boards"
+ select SUPPORT_SPL
+
+config TARGET_CM_T3517
+ bool "CompuLab CM-T3517 boards"
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
+ select SUPPORT_SPL
config TARGET_OMAP3_EVM
bool "TI OMAP3 EVM"
+ select SUPPORT_SPL
config TARGET_OMAP3_EVM_QUICK_MMC
bool "TI OMAP3 EVM Quick MMC"
+ select SUPPORT_SPL
config TARGET_OMAP3_EVM_QUICK_NAND
bool "TI OMAP3 EVM Quick NAND"
+ select SUPPORT_SPL
config TARGET_OMAP3_IGEP00X0
bool "IGEP"
+ select SUPPORT_SPL
config TARGET_OMAP3_OVERO
bool "OMAP35xx Gumstix Overo"
+ select SUPPORT_SPL
config TARGET_OMAP3_ZOOM1
bool "TI Zoom1"
config TARGET_AM3517_CRANE
bool "am3517_crane"
+ select SUPPORT_SPL
config TARGET_OMAP3_PANDORA
bool "OMAP3 Pandora"
config TARGET_ECO5PK
bool "ECO5PK"
+ select SUPPORT_SPL
config TARGET_DIG297
bool "DIG297"
config TARGET_TRICORDER
bool "Tricorder"
+ select SUPPORT_SPL
config TARGET_MCX
bool "MCX"
+ select SUPPORT_SPL
config TARGET_OMAP3_LOGIC
bool "OMAP3 Logic"
@@ -68,15 +85,14 @@ config TARGET_NOKIA_RX51
config TARGET_TAO3530
bool "TAO3530"
+ select SUPPORT_SPL
config TARGET_TWISTER
bool "Twister"
+ select SUPPORT_SPL
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "omap3"
@@ -85,6 +101,7 @@ source "board/teejet/mt_ventoux/Kconfig"
source "board/ti/sdp3430/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
+source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 667e77ff05..53a9e5d77d 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -17,13 +17,15 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <mmc.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
#include <asm/omap_common.h>
#include <asm/arch/mmc_host_def.h>
#include <i2c.h>
@@ -38,6 +40,27 @@ static void omap3_setup_aux_cr(void);
static void omap3_invalidate_l2_cache_secure(void);
#endif
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata omap34xx_gpio[] = {
+ { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+ { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+ { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+ { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+ { "gpio_omap", &omap34xx_gpio[0] },
+ { "gpio_omap", &omap34xx_gpio[1] },
+ { "gpio_omap", &omap34xx_gpio[2] },
+ { "gpio_omap", &omap34xx_gpio[3] },
+ { "gpio_omap", &omap34xx_gpio[4] },
+ { "gpio_omap", &omap34xx_gpio[5] },
+};
+
+#else
+
static const struct gpio_bank gpio_bank_34xx[6] = {
{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
@@ -49,6 +72,8 @@ static const struct gpio_bank gpio_bank_34xx[6] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
+#endif
+
#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
@@ -65,7 +90,7 @@ u32 spl_boot_mode(void)
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_RAW;
case BOOT_DEVICE_MMC1:
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
break;
default:
puts("spl: ERROR: unknown device - can't select boot mode\n");
@@ -266,7 +291,7 @@ int __weak misc_init_r(void)
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
*****************************************************************************/
-void wait_for_command_complete(struct watchdog *wd_base)
+static void wait_for_command_complete(struct watchdog *wd_base)
{
int pending = 1;
do {
diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
index 6c7330a0ca..a2aadc9816 100644
--- a/arch/arm/cpu/armv7/omap3/emif4.c
+++ b/arch/arm/cpu/armv7/omap3/emif4.c
@@ -61,7 +61,7 @@ u32 get_sdr_cs_offset(u32 cs)
* - Init the emif4 module for DDR access
* - Early init routines, called from flash or SRAM.
*/
-void do_emif4_init(void)
+static void do_emif4_init(void)
{
unsigned int regval;
/* Set the DDR PHY parameters in PHY ctrl registers */
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index bef5f05eaa..bbb65bbe72 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -16,6 +16,8 @@
#include <asm/io.h>
#include <asm/arch/mem.h> /* get mem tables */
#include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
+
#include <i2c.h>
#include <linux/compiler.h>
@@ -202,7 +204,7 @@ u32 __weak get_board_rev(void)
/********************************************************
* get_base(); get upper addr of current execution
*******************************************************/
-u32 get_base(void)
+static u32 get_base(void)
{
u32 val;
diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig
index e270895135..eccf897258 100644
--- a/arch/arm/cpu/armv7/omap4/Kconfig
+++ b/arch/arm/cpu/armv7/omap4/Kconfig
@@ -14,9 +14,6 @@ config TARGET_OMAP4_SDP4430
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "omap4"
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
index 2ccf5b919d..129982caca 100644
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ b/arch/arm/cpu/armv7/omap5/Kconfig
@@ -14,9 +14,6 @@ config TARGET_DRA7XX_EVM
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "omap5"
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 6c2bb22a85..8444d4224a 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -20,12 +20,14 @@ config TARGET_ALT
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "rmobile"
+config RMOBILE_EXTRAM_BOOT
+ bool "Enable boot from RAM"
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
+ default n
+
source "board/atmark-techno/armadillo-800eva/Kconfig"
source "board/renesas/koelsch/Kconfig"
source "board/renesas/lager/Kconfig"
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index 879e0e097f..d47546a11d 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -60,17 +60,10 @@ do_lowlevel_init:
cmp r1, #3 /* has already been set up */
bicne r0, r0, #0xe7
orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
-
- ldr r2, =0xFF000044 /* PRR */
- ldr r1, [r2]
- and r1, r1, #0x7F00
- lsrs r1, r1, #8
- cmp r1, #0x45 /* 0x45 is ID of r8a7790 */
- bne L2CTLR_5_SKIP
+#if defined(CONFIG_R8A7790)
orrne r0, r0, #0x20 /* L2CTLR[5] */
-L2CTLR_5_SKIP:
+#endif
mcrne p15, 1, r0, c9, c0, 2
-
_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
index 2fbbc18203..628813423f 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig
+++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
@@ -13,9 +13,6 @@ config TARGET_SMDKC100
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "s5pc1xx"
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 0eab264668..8c3e5f7cd4 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -176,7 +176,7 @@ static void socfpga_nic301_slave_ns(void)
static uint32_t iswgrp_handoff[8];
-int misc_init_r(void)
+int arch_early_init_r(void)
{
int i;
for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
index db9bdad7d6..569fa418f4 100644
--- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -42,13 +42,4 @@ SECTIONS
. = ALIGN(4);
__bss_end = .;
} >.sdram
-
- . = ALIGN(8);
- __malloc_start = .;
- . = . + CONFIG_SPL_MALLOC_SIZE;
- __malloc_end = .;
-
- . = . + CONFIG_SPL_STACK_SIZE;
- . = ALIGN(8);
- __stack_start = .;
}
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index fedd7c8f7e..fdc05b942f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -81,12 +81,6 @@ ENTRY(c_runtime_cpu_setup)
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
#endif
-/*
- * Move vector table
- */
- /* Set vector address in CP15 VBAR register */
- ldr r0, =_start
- mcr p15, 0, r0, c12, c0, 0 @Set VBAR
bx lr
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index e9721b27b6..82dbf764e4 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,9 +11,13 @@ obj-y += timer.o
obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
-obj-$(CONFIG_SUN4I) += clock_sun4i.o
-obj-$(CONFIG_SUN5I) += clock_sun4i.o
-obj-$(CONFIG_SUN7I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN6I) += prcm.o
+obj-$(CONFIG_MACH_SUN8I) += prcm.o
+obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
ifndef CONFIG_SPL_BUILD
obj-y += cpu_info.o
@@ -23,9 +27,9 @@ endif
endif
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SUN4I) += dram.o
-obj-$(CONFIG_SUN5I) += dram.o
-obj-$(CONFIG_SUN7I) += dram.o
+obj-$(CONFIG_MACH_SUN4I) += dram.o
+obj-$(CONFIG_MACH_SUN5I) += dram.o
+obj-$(CONFIG_MACH_SUN7I) += dram.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index f2cedbb156..6c812fc6e9 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -50,18 +50,35 @@ u32 spl_boot_mode(void)
int gpio_init(void)
{
-#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
+#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
+#endif
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+ sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
- sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+ sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
- sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+ sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+ sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
- sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+ sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+ sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
@@ -71,6 +88,7 @@ int gpio_init(void)
void reset_cpu(ulong addr)
{
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
@@ -82,12 +100,22 @@ void reset_cpu(ulong addr)
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
+ static const struct sunxi_wdog *wdog =
+ ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+ /* Set the watchdog for its shortest interval (.5s) and wait */
+ writel(WDT_CFG_RESET, &wdog->cfg);
+ writel(WDT_MODE_EN, &wdog->mode);
+ writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+#endif
}
/* do some early init */
void s_init(void)
{
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
+ defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index ecbdb0162b..a0e49d179f 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -35,7 +35,7 @@ void clock_init_safe(void)
APB0_DIV_1 << APB0_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
#endif
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
@@ -180,6 +180,17 @@ void clock_set_pll1(unsigned int hz)
}
#endif
+unsigned int clock_get_pll5p(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll5_cfg);
+ int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
+ int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
+ int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
+ return (24000000 * n * k) >> p;
+}
+
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
new file mode 100644
index 0000000000..1eae9767d0
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -0,0 +1,76 @@
+/*
+ * sun6i specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void clock_init_uart(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#if CONFIG_CONS_INDEX < 5
+ /* uart clock source is apb2 */
+ writel(APB2_CLK_SRC_OSC24M|
+ APB2_CLK_RATE_N_1|
+ APB2_CLK_RATE_M(1),
+ &ccm->apb2_div);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+#else
+ /* enable R_PIO and R_UART clocks, and de-assert resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
+
+ /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (port > 3)
+ return -1;
+
+ /* set the apb clock gate for twi */
+ if (state)
+ setbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+ else
+ clrbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+
+ return 0;
+}
+
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll6_cfg);
+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
+ int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+ return 24000000 * n * k / 2;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 5cf35acc1e..41b9add297 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -13,9 +13,9 @@
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
puts("CPU: Allwinner A10 (SUN4I)\n");
-#elif defined CONFIG_SUN5I
+#elif defined CONFIG_MACH_SUN5I
u32 val = readl(SUNXI_SID_BASE + 0x08);
switch ((val >> 12) & 0xf) {
case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
@@ -23,8 +23,12 @@ int print_cpuinfo(void)
case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
default: puts("CPU: Allwinner A1X (SUN5I)\n");
}
-#elif defined CONFIG_SUN7I
+#elif defined CONFIG_MACH_SUN6I
+ puts("CPU: Allwinner A31 (SUN6I)\n");
+#elif defined CONFIG_MACH_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
+#elif defined CONFIG_MACH_SUN8I
+ puts("CPU: Allwinner A23 (SUN8I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 584f7420d7..dc9fdb930b 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -74,7 +74,7 @@ static void mctl_ddr3_reset(void)
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
struct sunxi_timer_reg *timer =
(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
u32 reg_val;
@@ -113,7 +113,7 @@ static void mctl_set_drive(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
#else
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
@@ -202,7 +202,7 @@ static void mctl_enable_dllx(u32 phase)
}
static u32 hpcr_value[32] = {
-#ifdef CONFIG_SUN5I
+#ifdef CONFIG_MACH_SUN5I
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@@ -212,7 +212,7 @@ static u32 hpcr_value[32] = {
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0
#endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0, 0,
0, 0, 0, 0,
@@ -222,7 +222,7 @@ static u32 hpcr_value[32] = {
0x1035, 0x1031, 0x0731, 0x1035,
0x1031, 0x0301, 0x0301, 0x0731
#endif
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0x0301,
0, 0, 0, 0,
@@ -252,15 +252,9 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
{
u32 reg_val;
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* PLL5P and PLL6 are the potential clock sources for MBUS */
- u32 pll6x_div, pll5p_div;
- u32 pll6x_clk = clock_get_pll6() / 1000000;
- u32 pll5p_clk = clk / 24 * 48;
+ u32 pll5p_clk, pll6x_clk;
+ u32 pll5p_div, pll6x_div;
u32 pll5p_rate, pll6x_rate;
-#ifdef CONFIG_SUN7I
- pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
-#endif
/* setup DRAM PLL */
reg_val = readl(&ccm->pll5_cfg);
@@ -268,33 +262,32 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */
reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
+#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
+ /* Old kernels are hardcoded to P=1 (divide by 2) */
+ reg_val |= CCM_PLL5_CTRL_P(1);
+#endif
if (clk >= 540 && clk < 552) {
- /* dram = 540MHz, pll5p = 1080MHz */
- pll5p_clk = 1080;
+ /* dram = 540MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
} else if (clk >= 512 && clk < 528) {
- /* dram = 512MHz, pll5p = 1536MHz */
- pll5p_clk = 1536;
+ /* dram = 512MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
} else if (clk >= 496 && clk < 504) {
- /* dram = 496MHz, pll5p = 1488MHz */
- pll5p_clk = 1488;
+ /* dram = 496MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
} else if (clk >= 468 && clk < 480) {
- /* dram = 468MHz, pll5p = 936MHz */
- pll5p_clk = 936;
+ /* dram = 468MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
} else if (clk >= 396 && clk < 408) {
- /* dram = 396MHz, pll5p = 792MHz */
- pll5p_clk = 792;
+ /* dram = 396MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
@@ -311,7 +304,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
/* reset GPS */
clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
@@ -322,6 +315,13 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
/* setup MBUS clock */
if (!mbus_clk)
mbus_clk = 300;
+
+ /* PLL5P and PLL6 are the potential clock sources for MBUS */
+ pll6x_clk = clock_get_pll6() / 1000000;
+#ifdef CONFIG_MACH_SUN7I
+ pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
+#endif
+ pll5p_clk = clock_get_pll5p() / 1000000;
pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
pll6x_rate = pll6x_clk / pll6x_div;
@@ -348,7 +348,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
* open DRAMC AHB & DLL register clock
* close it first
*/
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
@@ -356,7 +356,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
udelay(22);
/* then open it */
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
@@ -417,7 +417,7 @@ static int dramc_scan_readpipe(void)
static void dramc_clock_output_en(u32 on)
{
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
if (on)
@@ -425,7 +425,7 @@ static void dramc_clock_output_en(u32 on)
else
clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
#endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (on)
setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
@@ -527,7 +527,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en)
u32 reg_val;
u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
-#ifndef CONFIG_SUN7I
+#ifndef CONFIG_MACH_SUN7I
/* Appears that some kind of automatically initiated default
* ZQ calibration is already in progress at this point on sun4i/sun5i
* hardware, but not on sun7i. So it is reasonable to wait for its
@@ -539,7 +539,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en)
if (!odt_en)
return;
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
/* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
* unless bit 24 is set in SDR_ZQCR1. Not much is known about the
* SDR_ZQCR1 register, but there are hints indicating that it might
@@ -597,7 +597,7 @@ static unsigned long dramc_init_helper(struct dram_para *para)
/* dram clock off */
dramc_clock_output_en(0);
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
/* select dram controller 1 */
writel(DRAM_CSEL_MAGIC, &dram->csel);
#endif
@@ -654,7 +654,7 @@ static unsigned long dramc_init_helper(struct dram_para *para)
writel(para->tpr2, &dram->tpr2);
reg_val = DRAM_MR_BURST_LENGTH(0x0);
-#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
+#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I))
reg_val |= DRAM_MR_POWER_DOWN;
#endif
reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
@@ -668,7 +668,7 @@ static unsigned long dramc_init_helper(struct dram_para *para)
/* disable drift compensation and set passive DQS window mode */
clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
/* Command rate timing mode 2T & 1T */
if (para->tpr4 & 0x1)
setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
@@ -718,7 +718,7 @@ unsigned long dramc_init(struct dram_para *para)
/* try to autodetect the DRAM bus width and density */
para->io_width = 16;
para->bus_width = 32;
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I)
/* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
para->density = 4096;
#else
diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c
index 1f2843fcac..b026f78ca5 100644
--- a/arch/arm/cpu/armv7/sunxi/pinmux.c
+++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
@@ -10,32 +10,42 @@
#include <asm/io.h>
#include <asm/arch/gpio.h>
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
{
- u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_CFG_INDEX(pin);
- u32 offset = GPIO_CFG_OFFSET(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
-
- return 0;
}
-int sunxi_gpio_get_cfgpin(u32 pin)
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
{
- u32 cfg;
u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_CFG_INDEX(pin);
- u32 offset = GPIO_CFG_OFFSET(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+ sunxi_gpio_set_cfgbank(pio, pin, val);
+}
+
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+{
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
+ u32 cfg;
+
cfg = readl(&pio->cfg[0] + index);
cfg >>= offset;
return cfg & 0xf;
}
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+ u32 bank = GPIO_BANK(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ return sunxi_gpio_get_cfgbank(pio, pin);
+}
+
int sunxi_gpio_set_drv(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
new file mode 100644
index 0000000000..19b4938dc9
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -0,0 +1,35 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
+{
+ struct sunxi_prcm_reg *prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ /* open the clock for module */
+ setbits_le32(&prcm->apb0_gate, flags);
+
+ /* deassert reset for module */
+ setbits_le32(&prcm->apb0_reset, flags);
+}
diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c
index fd77f3f0ef..d98cec9018 100644
--- a/arch/arm/cpu/armv7/tegra20/display.c
+++ b/arch/arm/cpu/armv7/tegra20/display.c
@@ -194,7 +194,8 @@ static void rgb_enable(struct dc_com_reg *com)
writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
}
-int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
+static int setup_window(struct disp_ctl_win *win,
+ struct fdt_disp_config *config)
{
win->x = 0;
win->y = 0;
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 34f5496c8c..f013dc3cad 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -1,16 +1,10 @@
menu "Panasonic UniPhier platform"
depends on ARCH_UNIPHIER
-config SYS_CPU
- string
- default "armv7"
-
config SYS_SOC
- string
default "uniphier"
config SYS_CONFIG_NAME
- string
default "ph1_pro4" if MACH_PH1_PRO4
default "ph1_ld4" if MACH_PH1_LD4
default "ph1_sld8" if MACH_PH1_SLD8
@@ -29,4 +23,13 @@ config MACH_PH1_SLD8
endchoice
+config CMD_PINMON
+ bool "Enable boot mode pins monitor command"
+ depends on !SPL_BUILD
+ default y
+ help
+ The command "pinmon" shows the state of the boot mode pins.
+ The boot mode pins are latched when the system reset is deasserted
+ and determine which device the system should load a boot image from.
+
endmenu
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
index 7cedddaadc..dd57469d9c 100644
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/Makefile
@@ -12,7 +12,7 @@ obj-y += dram_init.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
-obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o
+obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
obj-y += board_common.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index b385e19544..781b511a97 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -3,6 +3,7 @@
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
new file mode 100644
index 0000000000..0047223181
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK 36864000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index 712afd1bee..e11f4f6d8b 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -3,6 +3,7 @@
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
sg_init.o pll_init.o clkrst_init.o pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
new file mode 100644
index 0000000000..6da921e920
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK 73728000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
index b385e19544..781b511a97 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -3,6 +3,7 @@
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
new file mode 100644
index 0000000000..59d054a310
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK 80000000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig
index d6655a972b..f418cd6d99 100644
--- a/arch/arm/cpu/armv7/zynq/Kconfig
+++ b/arch/arm/cpu/armv7/zynq/Kconfig
@@ -17,9 +17,6 @@ config TARGET_ZYNQ_ZC770
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "zynq"
diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c
index 1ea086d520..d74f8dbbc4 100644
--- a/arch/arm/cpu/armv7/zynq/ddrc.c
+++ b/arch/arm/cpu/armv7/zynq/ddrc.c
@@ -40,6 +40,7 @@ void zynq_ddrc_init(void)
* first stage bootloader. To get ECC to work all memory has
* been initialized by writing any value.
*/
+ /* cppcheck-suppress nullPointer */
memset((void *)0, 0, 1 * 1024 * 1024);
} else {
puts("ECC disabled ");
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
index 9ff2ef2ae3..31627f970e 100644
--- a/arch/arm/cpu/armv7/zynq/spl.c
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -63,7 +63,7 @@ u32 spl_boot_device(void)
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(void)
{
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
}
#endif
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
index cbb5a529da..674a47061e 100644
--- a/arch/arm/cpu/at91-common/spl.c
+++ b/arch/arm/cpu/at91-common/spl.c
@@ -102,7 +102,7 @@ u32 spl_boot_mode(void)
switch (spl_boot_device()) {
#ifdef CONFIG_SYS_USE_MMC
case BOOT_DEVICE_MMC1:
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
break;
#endif
case BOOT_DEVICE_NONE:
diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c
index de20325ecf..5933c35ddd 100644
--- a/arch/arm/cpu/tegra-common/sys_info.c
+++ b/arch/arm/cpu/tegra-common/sys_info.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <linux/ctype.h>
-void upstring(char *s)
+static void upstring(char *s)
{
while (*s) {
*s = toupper(*s);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c34606334d..52f8926894 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_MACH_SUN7I) += sun7i-a20-pcduino3.dtb
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index 2f66deda9f..e70b4d1f1f 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -10,6 +10,10 @@
model = "TI AM335x BeagleBone";
compatible = "ti,am335x-bone", "ti,am33xx";
+ chosen {
+ stdout-path = &uart0;
+ };
+
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
diff --git a/arch/arm/dts/dt-bindings/gpio/gpio.h b/arch/arm/dts/dt-bindings/gpio/gpio.h
deleted file mode 100644
index e6b1e0a808..0000000000
--- a/arch/arm/dts/dt-bindings/gpio/gpio.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This header provides constants for most GPIO bindings.
- *
- * Most GPIO bindings include a flags cell as part of the GPIO specifier.
- * In most cases, the format of the flags cell uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_GPIO_GPIO_H
-#define _DT_BINDINGS_GPIO_GPIO_H
-
-#define GPIO_ACTIVE_HIGH 0
-#define GPIO_ACTIVE_LOW 1
-
-#endif
diff --git a/arch/arm/dts/dt-bindings/pinctrl/am33xx.h b/arch/arm/dts/dt-bindings/pinctrl/am33xx.h
deleted file mode 100644
index 2fbc804e1a..0000000000
--- a/arch/arm/dts/dt-bindings/pinctrl/am33xx.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This header provides constants specific to AM33XX pinctrl bindings.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
-#define _DT_BINDINGS_PINCTRL_AM33XX_H
-
-#include <dt-bindings/pinctrl/omap.h>
-
-/* am33xx specific mux bit defines */
-#undef PULL_ENA
-#undef INPUT_EN
-
-#define PULL_DISABLE (1 << 3)
-#define INPUT_EN (1 << 5)
-#define SLEWCTRL_FAST (1 << 6)
-
-/* update macro depending on INPUT_EN and PULL_ENA */
-#undef PIN_OUTPUT
-#undef PIN_OUTPUT_PULLUP
-#undef PIN_OUTPUT_PULLDOWN
-#undef PIN_INPUT
-#undef PIN_INPUT_PULLUP
-#undef PIN_INPUT_PULLDOWN
-
-#define PIN_OUTPUT (PULL_DISABLE)
-#define PIN_OUTPUT_PULLUP (PULL_UP)
-#define PIN_OUTPUT_PULLDOWN 0
-#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (INPUT_EN)
-
-/* undef non-existing modes */
-#undef PIN_OFF_NONE
-#undef PIN_OFF_OUTPUT_HIGH
-#undef PIN_OFF_OUTPUT_LOW
-#undef PIN_OFF_INPUT_PULLUP
-#undef PIN_OFF_INPUT_PULLDOWN
-#undef PIN_OFF_WAKEUPENABLE
-
-#endif
-
diff --git a/arch/arm/dts/dt-bindings/pinctrl/omap.h b/arch/arm/dts/dt-bindings/pinctrl/omap.h
deleted file mode 100644
index edbd250809..0000000000
--- a/arch/arm/dts/dt-bindings/pinctrl/omap.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This header provides constants for OMAP pinctrl bindings.
- *
- * Copyright (C) 2009 Nokia
- * Copyright (C) 2009-2010 Texas Instruments
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
-#define _DT_BINDINGS_PINCTRL_OMAP_H
-
-/* 34xx mux mode options for each pin. See TRM for options */
-#define MUX_MODE0 0
-#define MUX_MODE1 1
-#define MUX_MODE2 2
-#define MUX_MODE3 3
-#define MUX_MODE4 4
-#define MUX_MODE5 5
-#define MUX_MODE6 6
-#define MUX_MODE7 7
-
-/* 24xx/34xx mux bit defines */
-#define PULL_ENA (1 << 3)
-#define PULL_UP (1 << 4)
-#define ALTELECTRICALSEL (1 << 5)
-
-/* 34xx specific mux bit defines */
-#define INPUT_EN (1 << 8)
-#define OFF_EN (1 << 9)
-#define OFFOUT_EN (1 << 10)
-#define OFFOUT_VAL (1 << 11)
-#define OFF_PULL_EN (1 << 12)
-#define OFF_PULL_UP (1 << 13)
-#define WAKEUP_EN (1 << 14)
-
-/* 44xx specific mux bit defines */
-#define WAKEUP_EVENT (1 << 15)
-
-/* Active pin states */
-#define PIN_OUTPUT 0
-#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
-#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
-#define PIN_INPUT INPUT_EN
-#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
-
-/* Off mode states */
-#define PIN_OFF_NONE 0
-#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
-#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN)
-#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
-#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
-#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
-
-#endif
-
diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
index ee071c162f..f9b61ba8e8 100644
--- a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
@@ -14,7 +14,7 @@
pinctrl_1: pinctrl@11000000 {
#address-cells = <1>;
#size-cells = <0>;
- gpy0: gpy0 {
+ gpx0: gpx0 {
reg = <0xc00>;
};
};
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
index 81188bca13..8c7a2c3a78 100644
--- a/arch/arm/dts/exynos4210-trats.dts
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -101,7 +101,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0xA2 0>;
+ pwr-gpios = <&gpio 146 0>;
};
sdhci@12520000 {
@@ -111,7 +111,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x39C 0>;
+ cd-gpios = <&gpio 284 0>;
};
sdhci@12540000 {
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index 9139810b1a..808c3f7cc3 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -24,7 +24,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0xA2 0>;
+ pwr-gpios = <&gpio 146 0>;
};
sdhci@12520000 {
@@ -34,7 +34,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x39C 0>;
+ cd-gpios = <&gpio 284 0>;
};
sdhci@12540000 {
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index 4c5e2b39be..2a1f1dda4e 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -8,7 +8,7 @@
*/
/dts-v1/;
-#include "exynos4.dtsi"
+#include "exynos4412.dtsi"
/ {
model = "Odroid based on Exynos4412";
@@ -51,7 +51,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0xC2 0>;
+ cd-gpios = <&gpio 122 0>;
};
sdhci@12540000 {
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts
index 3b1e4588b5..60e4515a7e 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -416,7 +416,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0xB2 0>;
+ pwr-gpios = <&gpio 0x6a 0>;
status = "disabled";
};
@@ -427,7 +427,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x3BC 0>;
+ cd-gpios = <&gpio 0x7a 0>;
};
sdhci@12540000 {
@@ -437,7 +437,7 @@
dwmmc@12550000 {
samsung,bus-width = <8>;
samsung,timing = <2 1 0>;
- pwr-gpios = <&gpio 0xB2 0>;
+ pwr-gpios = <&gpio 0x6a 0>;
fifoth_val = <0x203f0040>;
bus_hz = <400000000>;
div = <0x3>;
diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
index c02796d2b3..c41d07b65f 100644
--- a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
@@ -9,7 +9,7 @@
#address-cells = <1>;
#size-cells = <0>;
gpf0: gpf0 {
- reg = <0xc180>;
+ reg = <0x180>;
};
gpj0: gpj0 {
reg = <0x240>;
@@ -25,9 +25,6 @@
gpm0: gpm0 {
reg = <0x260>;
};
- gpy0: gpy0 {
- reg = <0x120>;
- };
gpx0: gpx0 {
reg = <0xc00>;
};
diff --git a/arch/arm/dts/exynos4x12-pinctrl.dtsi b/arch/arm/dts/exynos4x12-pinctrl.dtsi
index 93f39983b4..23061351ff 100644
--- a/arch/arm/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/dts/exynos4x12-pinctrl.dtsi
@@ -176,79 +176,79 @@
#interrupt-cells = <2>;
};
- gpm0: gpm0 {
+ gpy0: gpy0 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpm1: gpm1 {
+ gpy1: gpy1 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpm2: gpm2 {
+ gpy2: gpy2 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpm3: gpm3 {
+ gpy3: gpy3 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpm4: gpm4 {
+ gpy4: gpy4 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpy0: gpy0 {
+ gpy5: gpy5 {
gpio-controller;
#gpio-cells = <2>;
};
- gpy1: gpy1 {
+ gpy6: gpy6 {
gpio-controller;
#gpio-cells = <2>;
};
- gpy2: gpy2 {
+ gpm0: gpm0 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- gpy3: gpy3 {
+ gpm1: gpm1 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- gpy4: gpy4 {
+ gpm2: gpm2 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- gpy5: gpy5 {
+ gpm3: gpm3 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- gpy6: gpy6 {
+ gpm4: gpm4 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpx0: gpx0 {
diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
new file mode 100644
index 0000000000..f7cc8e7a09
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2014 Zoltan HERPAI
+ * Zoltan HERPAI <wigyori@uid0.hu>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "LinkSprite pcDuino3";
+ compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ soc@01c00000 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+ };
+
+ usbphy: phy@01c13400 {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ usb2_vbus-supply = <&reg_usb2_vbus>;
+ status = "okay";
+ };
+
+ ehci0: usb@01c14000 {
+ status = "okay";
+ };
+
+ ohci0: usb@01c14400 {
+ status = "okay";
+ };
+
+ ahci: sata@01c18000 {
+ target-supply = <&reg_ahci_5v>;
+ status = "okay";
+ };
+
+ ehci1: usb@01c1c000 {
+ status = "okay";
+ };
+
+ ohci1: usb@01c1c400 {
+ status = "okay";
+ };
+
+ pinctrl@01c20800 {
+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
+ allwinner,pins = "PH2";
+ };
+
+ led_pins_pcduino3: led_pins@0 {
+ allwinner,pins = "PH15", "PH16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ key_pins_pcduino3: key_pins@0 {
+ allwinner,pins = "PH17", "PH18", "PH19";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ ir0: ir@01c21800 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 8>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ gmac: ethernet@01c50000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_pcduino3>;
+
+ tx {
+ label = "pcduino3:green:tx";
+ gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
+ };
+
+ rx {
+ label = "pcduino3:green:rx";
+ gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_pins_pcduino3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ button@0 {
+ label = "Key Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
+ };
+ button@1 {
+ label = "Key Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
+ };
+ button@2 {
+ label = "Key Menu";
+ linux,code = <KEY_MENU>;
+ gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ status = "okay";
+ };
+
+ reg_usb2_vbus: usb2-vbus {
+ status = "okay";
+ };
+
+ reg_ahci_5v: ahci-5v {
+ gpio = <&pio 7 2 0>;
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
new file mode 100644
index 0000000000..4011628c73
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -0,0 +1,988 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ aliases {
+ ethernet0 = &gmac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ interrupts = <0 120 4>,
+ <0 121 4>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-osc-clk";
+ reg = <0x01c20050 0x4>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll4: clk@01c20018 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-pll4-clk";
+ reg = <0x01c20018 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll4";
+ };
+
+ pll5: clk@01c20020 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll5-clk";
+ reg = <0x01c20020 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll5_ddr", "pll5_other";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
+ };
+
+ pll8: clk@01c20040 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-pll4-clk";
+ reg = <0x01c20040 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll8";
+ };
+
+ cpu: cpu@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb: ahb@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&axi>;
+ clock-output-names = "ahb";
+ };
+
+ ahb_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-output-names = "ahb_usb0", "ahb_ehci0",
+ "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
+ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+ "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+ "ahb_nand", "ahb_sdram", "ahb_ace",
+ "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+ "ahb_spi2", "ahb_spi3", "ahb_sata",
+ "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
+ "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
+ "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
+ "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+ "ahb_de_fe1", "ahb_gmac", "ahb_mp",
+ "ahb_mali";
+ };
+
+ apb0: apb0@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_codec", "apb0_spdif",
+ "apb0_ac97", "apb0_iis0", "apb0_iis1",
+ "apb0_pio", "apb0_ir0", "apb0_ir1",
+ "apb0_iis2", "apb0_keypad";
+ };
+
+ apb1_mux: apb1_mux@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+ clock-output-names = "apb1_mux";
+ };
+
+ apb1: apb1@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&apb1_mux>;
+ clock-output-names = "apb1";
+ };
+
+ apb1_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_i2c3", "apb1_can",
+ "apb1_scr", "apb1_ps20", "apb1_ps21",
+ "apb1_i2c4", "apb1_uart0", "apb1_uart1",
+ "apb1_uart2", "apb1_uart3", "apb1_uart4",
+ "apb1_uart5", "apb1_uart6", "apb1_uart7";
+ };
+
+ nand_clk: clk@01c20080 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20080 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "nand";
+ };
+
+ ms_clk: clk@01c20084 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20084 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ms";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc0";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc1";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc2";
+ };
+
+ mmc3_clk: clk@01c20094 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20094 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc3";
+ };
+
+ ts_clk: clk@01c20098 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20098 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ts";
+ };
+
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ss";
+ };
+
+ spi0_clk: clk@01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk@01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk@01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi2";
+ };
+
+ pata_clk: clk@01c200ac {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200ac 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "pata";
+ };
+
+ ir0_clk: clk@01c200b0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir0";
+ };
+
+ ir1_clk: clk@01c200b4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun4i-a10-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+ };
+
+ spi3_clk: clk@01c200d4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200d4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi3";
+ };
+
+ mbus_clk: clk@01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
+ clock-output-names = "mbus";
+ };
+
+ /*
+ * The following two are dummy clocks, placeholders used in the gmac_tx
+ * clock. The gmac driver will choose one parent depending on the PHY
+ * interface mode, using clk_set_rate auto-reparenting.
+ * The actual TX clock rate is not controlled by the gmac_tx clock.
+ */
+ mii_phy_tx_clk: clk@2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "mii_phy_tx";
+ };
+
+ gmac_int_tx_clk: clk@3 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_int_tx";
+ };
+
+ gmac_tx_clk: clk@01c20164 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-gmac-clk";
+ reg = <0x01c20164 0x4>;
+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+ clock-output-names = "gmac_tx";
+ };
+
+ /*
+ * Dummy clock used by output clocks
+ */
+ osc24M_32k: clk@1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <750>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "osc24M_32k";
+ };
+
+ clk_out_a: clk@01c201f0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-out-clk";
+ reg = <0x01c201f0 0x4>;
+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+ clock-output-names = "clk_out_a";
+ };
+
+ clk_out_b: clk@01c201f4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-out-clk";
+ reg = <0x01c201f4 0x4>;
+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+ clock-output-names = "clk_out_b";
+ };
+ };
+
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ nmi_intc: interrupt-controller@01c00030 {
+ compatible = "allwinner,sun7i-a20-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01c00030 0x0c>;
+ interrupts = <0 0 4>;
+ };
+
+ spi0: spi@01c05000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <0 10 4>;
+ clocks = <&ahb_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@01c06000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <0 11 4>;
+ clocks = <&ahb_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emac: ethernet@01c0b000 {
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <0 55 4>;
+ clocks = <&ahb_gates 17>;
+ status = "disabled";
+ };
+
+ mdio@01c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 32 4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 33 4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 34 4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 35 4>;
+ status = "disabled";
+ };
+
+ usbphy: phy@01c13400 {
+ #phy-cells = <1>;
+ compatible = "allwinner,sun7i-a20-usb-phy";
+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+ reg-names = "phy_ctrl", "pmu1", "pmu2";
+ clocks = <&usb_clk 8>;
+ clock-names = "usb_phy";
+ resets = <&usb_clk 1>, <&usb_clk 2>;
+ reset-names = "usb1_reset", "usb2_reset";
+ status = "disabled";
+ };
+
+ ehci0: usb@01c14000 {
+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+ reg = <0x01c14000 0x100>;
+ interrupts = <0 39 4>;
+ clocks = <&ahb_gates 1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@01c14400 {
+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+ reg = <0x01c14400 0x100>;
+ interrupts = <0 64 4>;
+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi2: spi@01c17000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <0 12 4>;
+ clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ahci: sata@01c18000 {
+ compatible = "allwinner,sun4i-a10-ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = <0 56 4>;
+ clocks = <&pll6 0>, <&ahb_gates 25>;
+ status = "disabled";
+ };
+
+ ehci1: usb@01c1c000 {
+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <0 40 4>;
+ clocks = <&ahb_gates 3>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1c400 {
+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <0 65 4>;
+ clocks = <&usb_clk 7>, <&ahb_gates 4>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi3: spi@01c1f000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c1f000 0x1000>;
+ interrupts = <0 50 4>;
+ clocks = <&ahb_gates 23>, <&spi3_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun7i-a20-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <0 28 4>;
+ clocks = <&apb0_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ pwm0_pins_a: pwm0@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "pwm";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ pwm1_pins_a: pwm1@0 {
+ allwinner,pins = "PI3";
+ allwinner,function = "pwm";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB22", "PB23";
+ allwinner,function = "uart0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart2_pins_a: uart2@0 {
+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+ allwinner,function = "uart2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart6_pins_a: uart6@0 {
+ allwinner,pins = "PI12", "PI13";
+ allwinner,function = "uart6";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart7_pins_a: uart7@0 {
+ allwinner,pins = "PI20", "PI21";
+ allwinner,function = "uart7";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "i2c0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PB18", "PB19";
+ allwinner,function = "i2c1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PB20", "PB21";
+ allwinner,function = "i2c2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ emac_pins_a: emac0@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ allwinner,function = "emac";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ clk_out_a_pins_a: clk_out_a@0 {
+ allwinner,pins = "PI12";
+ allwinner,function = "clk_out_a";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ clk_out_b_pins_a: clk_out_b@0 {
+ allwinner,pins = "PI13";
+ allwinner,function = "clk_out_b";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_mii_a: gmac_mii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ allwinner,function = "gmac";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA10",
+ "PA11", "PA12", "PA13",
+ "PA15", "PA16";
+ allwinner,function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ spi1_pins_a: spi1@0 {
+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+ allwinner,function = "spi1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ spi2_pins_a: spi2@0 {
+ allwinner,pins = "PC19", "PC20", "PC21", "PC22";
+ allwinner,function = "spi2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
+
+ mmc3_pins_a: mmc3@0 {
+ allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
+ allwinner,function = "mmc3";
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ ir0_pins_a: ir0@0 {
+ allwinner,pins = "PB3","PB4";
+ allwinner,function = "ir0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ ir1_pins_a: ir1@0 {
+ allwinner,pins = "PB22","PB23";
+ allwinner,function = "ir1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <0 22 4>,
+ <0 23 4>,
+ <0 24 4>,
+ <0 25 4>,
+ <0 67 4>,
+ <0 68 4>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@01c20c90 {
+ compatible = "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20c90 0x10>;
+ };
+
+ rtc: rtc@01c20d00 {
+ compatible = "allwinner,sun7i-a20-rtc";
+ reg = <0x01c20d00 0x20>;
+ interrupts = <0 24 4>;
+ };
+
+ pwm: pwm@01c20e00 {
+ compatible = "allwinner,sun7i-a20-pwm";
+ reg = <0x01c20e00 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ir0: ir@01c21800 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&apb0_gates 6>, <&ir0_clk>;
+ clock-names = "apb", "ir";
+ interrupts = <0 5 4>;
+ reg = <0x01c21800 0x40>;
+ status = "disabled";
+ };
+
+ ir1: ir@01c21c00 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&apb0_gates 7>, <&ir1_clk>;
+ clock-names = "apb", "ir";
+ interrupts = <0 6 4>;
+ reg = <0x01c21c00 0x40>;
+ status = "disabled";
+ };
+
+ sid: eeprom@01c23800 {
+ compatible = "allwinner,sun7i-a20-sid";
+ reg = <0x01c23800 0x200>;
+ };
+
+ rtp: rtp@01c25000 {
+ compatible = "allwinner,sun4i-a10-ts";
+ reg = <0x01c25000 0x100>;
+ interrupts = <0 29 4>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <0 1 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 16>;
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <0 2 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 17>;
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <0 3 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 18>;
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <0 4 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 19>;
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <0 17 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 20>;
+ status = "disabled";
+ };
+
+ uart5: serial@01c29400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29400 0x400>;
+ interrupts = <0 18 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 21>;
+ status = "disabled";
+ };
+
+ uart6: serial@01c29800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29800 0x400>;
+ interrupts = <0 19 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 22>;
+ status = "disabled";
+ };
+
+ uart7: serial@01c29c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29c00 0x400>;
+ interrupts = <0 20 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 23>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <0 7 4>;
+ clocks = <&apb1_gates 0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <0 8 4>;
+ clocks = <&apb1_gates 1>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <0 9 4>;
+ clocks = <&apb1_gates 2>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@01c2b800 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b800 0x400>;
+ interrupts = <0 88 4>;
+ clocks = <&apb1_gates 3>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@01c2c000 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2c000 0x400>;
+ interrupts = <0 89 4>;
+ clocks = <&apb1_gates 15>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac: ethernet@01c50000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x01c50000 0x10000>;
+ interrupts = <0 85 4>;
+ interrupt-names = "macirq";
+ clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ hstimer@01c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 81 4>,
+ <0 82 4>,
+ <0 83 4>,
+ <0 84 4>;
+ clocks = <&ahb_gates 28>;
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 0xf04>;
+ };
+ };
+};
diff --git a/arch/arm/dts/sunxi-common-regulators.dtsi b/arch/arm/dts/sunxi-common-regulators.dtsi
new file mode 100644
index 0000000000..3d021efd1a
--- /dev/null
+++ b/arch/arm/dts/sunxi-common-regulators.dtsi
@@ -0,0 +1,89 @@
+/*
+ * sunxi boards common regulator (ahci target power supply, usb-vbus) code
+ *
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+ soc@01c00000 {
+ pio: pinctrl@01c20800 {
+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
+ allwinner,pins = "PB8";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
+ allwinner,pins = "PH6";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ usb2_vbus_pin_a: usb2_vbus_pin@0 {
+ allwinner,pins = "PH3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+ };
+
+ reg_ahci_5v: ahci-5v {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ahci_pwr_pin_a>;
+ regulator-name = "ahci-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 1 8 0>;
+ status = "disabled";
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_vbus_pin_a>;
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 7 6 0>;
+ status = "disabled";
+ };
+
+ reg_usb2_vbus: usb2-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_pin_a>;
+ regulator-name = "usb2-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 7 3 0>;
+ status = "disabled";
+ };
+
+ reg_vcc3v0: vcc3v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index ed826a0e19..09fc22760d 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -7,7 +7,9 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <bootm.h>
#include <common.h>
+#include <netdev.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 22cd11aa04..e88e6e2a98 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -77,3 +77,18 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
p += stride;
}
}
+
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value)
+{
+ int i = 0;
+ u32 reg;
+ reg = readl(base + group * 4);
+ while (num_bits) {
+ reg &= ~(1<<(start_bit + i));
+ i++;
+ num_bits--;
+ }
+ reg |= (value << start_bit);
+ writel(reg, base + group * 4);
+}
diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c
index dbecf4e434..12256a38eb 100644
--- a/arch/arm/imx-common/misc.c
+++ b/arch/arm/imx-common/misc.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <asm/arch/sys_proto.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/imx-common/regs-common.h>
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index 9a02a644bc..9d3c31ab08 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -68,7 +68,7 @@ u32 spl_boot_mode(void)
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index c63f78f682..65ef60bf2e 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -12,6 +12,7 @@
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
/* General purpose timers registers */
struct mxc_gpt {
@@ -26,23 +27,59 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
+#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
+#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
+#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
+#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
+#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
#define GPTCR_TEN 1 /* Timer enable */
+#define GPTPR_PRESCALER24M_SHIFT 12
+#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
+
DECLARE_GLOBAL_DATA_PTR;
+static inline int gpt_has_clk_source_osc(void)
+{
+#if defined(CONFIG_MX6)
+ if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
+ (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
+ return 1;
+
+ return 0;
+#else
+ return 0;
+#endif
+}
+
+static inline ulong gpt_get_clk(void)
+{
+#ifdef CONFIG_MXC_GPT_HCLK
+ if (gpt_has_clk_source_osc())
+ return MXC_HCLK >> 3;
+ else
+ return mxc_get_clock(MXC_IPG_PERCLK);
+#else
+ return MXC_CLK32;
+#endif
+}
static inline unsigned long long tick_to_time(unsigned long long tick)
{
+ ulong gpt_clk = gpt_get_clk();
+
tick *= CONFIG_SYS_HZ;
- do_div(tick, MXC_CLK32);
+ do_div(tick, gpt_clk);
return tick;
}
static inline unsigned long long us_to_tick(unsigned long long usec)
{
- usec = usec * MXC_CLK32 + 999999;
+ ulong gpt_clk = gpt_get_clk();
+
+ usec = usec * gpt_clk + 999999;
do_div(usec, 1000000);
return usec;
@@ -59,11 +96,31 @@ int timer_init(void)
for (i = 0; i < 100; i++)
__raw_writel(0, &cur_gpt->control);
- __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
-
- /* Freerun Mode, PERCLK1 input */
i = __raw_readl(&cur_gpt->control);
- __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
+ i &= ~GPTCR_CLKSOURCE_MASK;
+
+#ifdef CONFIG_MXC_GPT_HCLK
+ if (gpt_has_clk_source_osc()) {
+ i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
+
+ /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
+ if (is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO) ||
+ is_cpu_type(MXC_CPU_MX6SX)) {
+ i |= GPTCR_24MEN;
+
+ /* Produce 3Mhz clock */
+ __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
+ &cur_gpt->prescaler);
+ }
+ } else {
+ i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
+ }
+#else
+ __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
+ i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+#endif
+ __raw_writel(i, &cur_gpt->control);
gd->arch.tbl = __raw_readl(&cur_gpt->counter);
gd->arch.tbu = 0;
@@ -86,7 +143,7 @@ ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
- * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
@@ -117,5 +174,5 @@ void __udelay(unsigned long usec)
*/
ulong get_tbclk(void)
{
- return MXC_CLK32;
+ return gpt_get_clk();
}
diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c
index 0121cd78f2..8651b80ce0 100644
--- a/arch/arm/imx-common/video.c
+++ b/arch/arm/imx-common/video.c
@@ -6,9 +6,6 @@
#include <asm/errno.h>
#include <asm/imx-common/video.h>
-extern struct display_info_t const displays[];
-extern size_t display_count;
-
int board_video_skip(void)
{
int i;
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index 3249437263..d8bf87258b 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -36,7 +36,7 @@ struct module_pin_mux {
/* Pad control register offset */
#define PAD_CTRL_BASE 0x800
-#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *)\
(PAD_CTRL_BASE))->x)
/*
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 33a82fca98..7eacf27a93 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -14,8 +14,6 @@
#include <asm/ti-common/sys_proto.h>
#include <asm/arch/cpu.h>
-#define BOARD_REV_ID 0x0
-
u32 get_cpu_rev(void);
u32 get_sysboot_value(void);
diff --git a/arch/arm/include/asm/arch-at91/at91_shdwn.h b/arch/arm/include/asm/arch-at91/at91_shdwn.h
deleted file mode 100644
index 18d9ea690e..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_shdwn.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Shutdown Controller
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_SHDWN_H
-#define AT91_SHDWN_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_shdwn {
- u32 cr; /* Control Rer. WO */
- u32 mr; /* Mode Register RW 0x00000003 */
- u32 sr; /* Status Register RO 0x00000000 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_SHDW_CR_KEY 0xa5000000
-#define AT91_SHDW_CR_SHDW 0x00000001
-
-#define AT91_SHDW_MR_RTTWKEN 0x00010000
-#define AT91_SHDW_MR_CPTWK0 0x000000f0
-#define AT91_SHDW_MR_WKMODE0H2L 0x00000002
-#define AT91_SHDW_MR_WKMODE0L2H 0x00000001
-
-#define AT91_SHDW_SR_RTTWK 0x00010000
-#define AT91_SHDW_SR_WAKEUP0 0x00000001
-
-#endif
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index dded857c3a..61f427d914 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -119,6 +119,20 @@ struct bcm2835_mbox_tag_hdr {
* };
*/
+#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003
+
+struct bcm2835_mbox_tag_get_mac_address {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+ union {
+ struct {
+ } req;
+ struct {
+ u8 mac[6];
+ u8 pad[2];
+ } resp;
+ } body;
+};
+
#define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005
struct bcm2835_mbox_tag_get_arm_mem {
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index ba717146f5..78aceef17b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -29,6 +29,8 @@
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_ACE_SFR_BASE 0x10830000
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
#define EXYNOS4_FIMD_BASE 0x11C00000
#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
@@ -70,7 +72,14 @@
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4X12_GPIO_PART2_0 0x11000000
+#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */
#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
#define EXYNOS4X12_FIMD_BASE 0x11C00000
#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4X12_USBOTG_BASE 0x12480000
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index ad2ece64f4..02287decc2 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -284,7 +284,10 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_Y65,
EXYNOS4_GPIO_Y66,
EXYNOS4_GPIO_Y67,
- EXYNOS4_GPIO_X00, /* 256 0x100 */
+
+ /* GPIO_PART2_1 STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
+ EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
EXYNOS4_GPIO_X01,
EXYNOS4_GPIO_X02,
EXYNOS4_GPIO_X03,
@@ -318,8 +321,8 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */
- EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */
- EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+ EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */
+ EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
EXYNOS4_GPIO_Z1,
EXYNOS4_GPIO_Z2,
EXYNOS4_GPIO_Z3,
@@ -332,7 +335,7 @@ enum exynos4_gpio_pin {
};
enum exynos4X12_gpio_pin {
- /* GPIO_PART1_STARTS */
+ /* EXYNOS4X12_GPIO_PART1_0 starts here */
EXYNOS4X12_GPIO_A00, /* 0 */
EXYNOS4X12_GPIO_A01,
EXYNOS4X12_GPIO_A02,
@@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_D15,
EXYNOS4X12_GPIO_D16,
EXYNOS4X12_GPIO_D17,
- EXYNOS4X12_GPIO_F00, /* 56 0x38 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
+ /* EXYNOS4X12_GPIO_PART1_1 starts here */
+ EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
EXYNOS4X12_GPIO_F01,
EXYNOS4X12_GPIO_F02,
EXYNOS4X12_GPIO_F03,
@@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_F35,
EXYNOS4X12_GPIO_F36,
EXYNOS4X12_GPIO_F37,
- EXYNOS4X12_GPIO_J00, /* 88 0x58 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
+ /* EXYNOS4X12_GPIO_PART1_2 starts here */
+ EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
EXYNOS4X12_GPIO_J01,
EXYNOS4X12_GPIO_J02,
EXYNOS4X12_GPIO_J03,
@@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_J16,
EXYNOS4X12_GPIO_J17,
- /* GPIO_PART2_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */
- EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
+ /**
+ * EXYNOS4X12_GPIO_PART2_0 is not used
+ * EXYNOS4X12_GPIO_PART2_1 starts here
+ */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
+ EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
EXYNOS4X12_GPIO_K01,
EXYNOS4X12_GPIO_K02,
EXYNOS4X12_GPIO_K03,
@@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y65,
EXYNOS4X12_GPIO_Y66,
EXYNOS4X12_GPIO_Y67,
- EXYNOS4X12_GPIO_M00, /* 216 0xd8 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
+ /* EXYNOS4X12_GPIO_PART2_2 starts here */
+ EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
EXYNOS4X12_GPIO_M01,
EXYNOS4X12_GPIO_M02,
EXYNOS4X12_GPIO_M03,
@@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_M45,
EXYNOS4X12_GPIO_M46,
EXYNOS4X12_GPIO_M47,
- EXYNOS4X12_GPIO_X00, /* 256 0x100 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
+ /* EXYNOS4X12_GPIO_PART2_3 starts here */
+ EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
EXYNOS4X12_GPIO_X01,
EXYNOS4X12_GPIO_X02,
EXYNOS4X12_GPIO_X03,
@@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_X36,
EXYNOS4X12_GPIO_X37,
- /* GPIO_PART3_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */
- EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+ /* EXYNOS4X12_GPIO_PART3 starts here */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
+ EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
EXYNOS4X12_GPIO_Z1,
EXYNOS4X12_GPIO_Z2,
EXYNOS4X12_GPIO_Z3,
@@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Z6,
EXYNOS4X12_GPIO_Z7,
- /* GPIO_PART4_STARTS */
+ /* EXYNOS4X12_GPIO_PART4 starts here */
EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
EXYNOS4X12_GPIO_V01,
@@ -1339,17 +1353,22 @@ struct gpio_info {
unsigned int max_gpio; /* Maximum GPIO in this part */
};
-#define EXYNOS4_GPIO_NUM_PARTS 3
+#define EXYNOS4_GPIO_NUM_PARTS 4
static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
{ EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
+ { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
{ EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
};
-#define EXYNOS4X12_GPIO_NUM_PARTS 4
+#define EXYNOS4X12_GPIO_NUM_PARTS 8
static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
- { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },
+ { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },
+ { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },
+ { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },
+ { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },
+ { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },
{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
{ EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
};
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
index df33a78a10..d013b830ed 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
@@ -25,27 +25,28 @@ enum ext_clk_e {
extern unsigned int external_clk[ext_clk_count];
-enum clk_e {
- core_pll_clk,
- pass_pll_clk,
- ddr3_pll_clk,
- sys_clk0_clk,
- sys_clk0_1_clk,
- sys_clk0_2_clk,
- sys_clk0_3_clk,
- sys_clk0_4_clk,
- sys_clk0_6_clk,
- sys_clk0_8_clk,
- sys_clk0_12_clk,
- sys_clk0_24_clk,
- sys_clk1_clk,
- sys_clk1_3_clk,
- sys_clk1_4_clk,
- sys_clk1_6_clk,
- sys_clk1_12_clk,
- sys_clk2_clk,
- sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, ddr3_pll_clk)\
+ CLK(3, sys_clk0_clk)\
+ CLK(4, sys_clk0_1_clk)\
+ CLK(5, sys_clk0_2_clk)\
+ CLK(6, sys_clk0_3_clk)\
+ CLK(7, sys_clk0_4_clk)\
+ CLK(8, sys_clk0_6_clk)\
+ CLK(9, sys_clk0_8_clk)\
+ CLK(10, sys_clk0_12_clk)\
+ CLK(11, sys_clk0_24_clk)\
+ CLK(12, sys_clk1_clk)\
+ CLK(13, sys_clk1_3_clk)\
+ CLK(14, sys_clk1_4_clk)\
+ CLK(15, sys_clk1_6_clk)\
+ CLK(16, sys_clk1_12_clk)\
+ CLK(17, sys_clk2_clk)\
+ CLK(18, sys_clk3_clk)
+
+#define PLLSET_CMD_LIST "<pa|ddr3>"
#define KS2_CLK1_6 sys_clk0_6_clk
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
index bdb869bed4..f28d5f0c4e 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -28,29 +28,30 @@ enum ext_clk_e {
extern unsigned int external_clk[ext_clk_count];
-enum clk_e {
- core_pll_clk,
- pass_pll_clk,
- tetris_pll_clk,
- ddr3a_pll_clk,
- ddr3b_pll_clk,
- sys_clk0_clk,
- sys_clk0_1_clk,
- sys_clk0_2_clk,
- sys_clk0_3_clk,
- sys_clk0_4_clk,
- sys_clk0_6_clk,
- sys_clk0_8_clk,
- sys_clk0_12_clk,
- sys_clk0_24_clk,
- sys_clk1_clk,
- sys_clk1_3_clk,
- sys_clk1_4_clk,
- sys_clk1_6_clk,
- sys_clk1_12_clk,
- sys_clk2_clk,
- sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, tetris_pll_clk)\
+ CLK(3, ddr3a_pll_clk)\
+ CLK(4, ddr3b_pll_clk)\
+ CLK(5, sys_clk0_clk)\
+ CLK(6, sys_clk0_1_clk)\
+ CLK(7, sys_clk0_2_clk)\
+ CLK(8, sys_clk0_3_clk)\
+ CLK(9, sys_clk0_4_clk)\
+ CLK(10, sys_clk0_6_clk)\
+ CLK(11, sys_clk0_8_clk)\
+ CLK(12, sys_clk0_12_clk)\
+ CLK(13, sys_clk0_24_clk)\
+ CLK(14, sys_clk1_clk)\
+ CLK(15, sys_clk1_3_clk)\
+ CLK(16, sys_clk1_4_clk)\
+ CLK(17, sys_clk1_6_clk)\
+ CLK(18, sys_clk1_12_clk)\
+ CLK(19, sys_clk2_clk)\
+ CLK(20, sys_clk3_clk)
+
+#define PLLSET_CMD_LIST "<pa|arm|ddr3a|ddr3b>"
#define KS2_CLK1_6 sys_clk0_6_clk
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h
new file mode 100644
index 0000000000..bb9a5c4dcf
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h
@@ -0,0 +1,95 @@
+/*
+ * K2L: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2L_H
+#define __ASM_ARCH_CLOCK_K2L_H
+
+enum ext_clk_e {
+ sys_clk,
+ alt_core_clk,
+ pa_clk,
+ tetris_clk,
+ ddr3_clk,
+ pcie_clk,
+ sgmii_clk,
+ usb_clk,
+ rp1_clk,
+ ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, tetris_pll_clk)\
+ CLK(3, ddr3_pll_clk)\
+ CLK(4, sys_clk0_clk)\
+ CLK(5, sys_clk0_1_clk)\
+ CLK(6, sys_clk0_2_clk)\
+ CLK(7, sys_clk0_3_clk)\
+ CLK(8, sys_clk0_4_clk)\
+ CLK(9, sys_clk0_6_clk)\
+ CLK(10, sys_clk0_8_clk)\
+ CLK(11, sys_clk0_12_clk)\
+ CLK(12, sys_clk0_24_clk)\
+ CLK(13, sys_clk1_clk)\
+ CLK(14, sys_clk1_3_clk)\
+ CLK(15, sys_clk1_4_clk)\
+ CLK(16, sys_clk1_6_clk)\
+ CLK(17, sys_clk1_12_clk)\
+ CLK(18, sys_clk2_clk)\
+ CLK(19, sys_clk3_clk)\
+
+#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
+
+#define KS2_CLK1_6 sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+ CORE_PLL,
+ PASS_PLL,
+ TETRIS_PLL,
+ DDR3_PLL,
+};
+
+enum {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD_RSV
+};
+
+#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
+#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
+#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
+#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
+#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
+#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
+#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
+#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2}
+#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
+#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
+#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
+#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2}
+#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2}
+#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2}
+#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2}
+#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2}
+#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2}
+#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
+#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
+#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
+#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
index dae000e43a..9f6cfb265f 100644
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -20,10 +20,22 @@
#include <asm/arch/clock-k2e.h>
#endif
+#ifdef CONFIG_SOC_K2L
+#include <asm/arch/clock-k2l.h>
+#endif
+
#define MAIN_PLL CORE_PLL
#include <asm/types.h>
+#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
+#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
+#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)
+
+enum clk_e {
+ CLK_LIST(GENERATE_ENUM)
+};
+
struct keystone_pll_regs {
u32 reg0;
u32 reg1;
@@ -46,6 +58,7 @@ void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
+void pass_pll_pa_clk_enable(void);
int get_max_dev_speed(void);
int get_max_arm_speed(void);
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h
index 6bf35d3543..b044d6f18f 100644
--- a/arch/arm/include/asm/arch-keystone/ddr3.h
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -49,8 +49,14 @@ struct ddr3_emif_config {
};
void ddr3_init(void);
+int ddr3_get_size(void);
void ddr3_reset_ddrphy(void);
+void ddr3_init_ecc(u32 base);
+void ddr3_disable_ecc(u32 base);
+void ddr3_check_ecc_int(u32 base);
+int ddr3_ecc_support_rmw(u32 base);
void ddr3_err_reset_workaround(void);
+void ddr3_enable_ecc(u32 base, int test);
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
diff --git a/arch/arm/include/asm/arch-keystone/emac_defs.h b/arch/arm/include/asm/arch-keystone/emac_defs.h
deleted file mode 100644
index 9cd8925819..0000000000
--- a/arch/arm/include/asm/arch-keystone/emac_defs.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * emac definitions for keystone2 devices
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _EMAC_DEFS_H_
-#define _EMAC_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
-#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
-#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
-
-#define KEYSTONE2_EMAC_GIG_ENABLE
-
-#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
-
-#ifdef CONFIG_SOC_K2HK
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
-#endif
-
-/* MII Status Register */
-#define MII_STATUS_REG 1
-#define MII_STATUS_LINK_MASK (0x4)
-
-/* Marvell 88E1111 PHY ID */
-#define PHY_MARVELL_88E1111 (0x01410cc0)
-
-#define MDIO_CONTROL_IDLE (0x80000000)
-#define MDIO_CONTROL_ENABLE (0x40000000)
-#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
-#define MDIO_CONTROL_FAULT (0x80000)
-#define MDIO_USERACCESS0_GO (0x80000000)
-#define MDIO_USERACCESS0_WRITE_READ (0x0)
-#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
-#define MDIO_USERACCESS0_ACK (0x20000000)
-
-#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
-#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
-#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
-#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
-#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
-
-#define EMAC_MIN_ETHERNET_PKT_SIZE 60
-
-struct mac_sl_cfg {
- u_int32_t max_rx_len; /* Maximum receive packet length. */
- u_int32_t ctl; /* Control bitfield */
-};
-
-/*
- * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
- */
-#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
-#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
-#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
-#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
-#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
-#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
-#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
-#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
-#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
-#define GMACSL_ENABLE_GIG_MODE (1 << 7)
-#define GMACSL_TX_ENABLE_PACE (1 << 6)
-#define GMACSL_ENABLE (1 << 5)
-#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
-#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
-#define GMACSL_ENABLE_LOOPBACK (1 << 1)
-#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
-
-/*
- * DEFINTITION: function return values
- */
-#define GMACSL_RET_OK 0
-#define GMACSL_RET_INVALID_PORT -1
-#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
-#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
-#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
-
-/* Register offsets */
-#define CPGMACSL_REG_ID 0x00
-#define CPGMACSL_REG_CTL 0x04
-#define CPGMACSL_REG_STATUS 0x08
-#define CPGMACSL_REG_RESET 0x0c
-#define CPGMACSL_REG_MAXLEN 0x10
-#define CPGMACSL_REG_BOFF 0x14
-#define CPGMACSL_REG_RX_PAUSE 0x18
-#define CPGMACSL_REG_TX_PAURSE 0x1c
-#define CPGMACSL_REG_EM_CTL 0x20
-#define CPGMACSL_REG_PRI 0x24
-
-/* Soft reset register values */
-#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
-#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
-
-/* Maxlen register values */
-#define CPGMAC_REG_MAXLEN_LEN 0x3fff
-
-/* Control bitfields */
-#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
-#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
-#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
-#define CPSW_CTL_P0_ENABLE (1 << 2)
-#define CPSW_CTL_VLAN_AWARE (1 << 1)
-#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
-
-#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */
-#define DEVICE_CPSW_BASE (0x02090800)
-#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
-#define SWITCH_MAX_PKT_SIZE 9000
-
-/* Register offsets */
-#define CPSW_REG_CTL 0x004
-#define CPSW_REG_STAT_PORT_EN 0x00c
-#define CPSW_REG_MAXLEN 0x040
-#define CPSW_REG_ALE_CONTROL 0x608
-#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
-
-/* Register values */
-#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
-#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
-#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
-#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
-
-#define SGMII_REG_STATUS_LOCK BIT(4)
-#define SGMII_REG_STATUS_LINK BIT(0)
-#define SGMII_REG_STATUS_AUTONEG BIT(2)
-#define SGMII_REG_CONTROL_AUTONEG BIT(0)
-#define SGMII_REG_CONTROL_MASTER BIT(5)
-#define SGMII_REG_MR_ADV_ENABLE BIT(0)
-#define SGMII_REG_MR_ADV_LINK BIT(15)
-#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
-#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
-
-#define SGMII_LINK_MAC_MAC_AUTONEG 0
-#define SGMII_LINK_MAC_PHY 1
-#define SGMII_LINK_MAC_MAC_FORCED 2
-#define SGMII_LINK_MAC_FIBER 3
-#define SGMII_LINK_MAC_PHY_FORCED 4
-
-#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100
-#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \
- KS2_PASS_BASE + 0x00090200, \
- KS2_PASS_BASE + 0x00090400, \
- KS2_PASS_BASE + 0x00090500}
-
-#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
-
-/*
- * SGMII registers
- */
-#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
-#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
-#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
-#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
-#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
-#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
-#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
-#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
-#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
-
-#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
-#define DEVICE_N_GMACSL_PORTS 4
-#define DEVICE_EMACSL_RESET_POLL_COUNT 100
-
-#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
-
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606
-#endif
-
-#define hw_config_streaming_switch() \
- writel(DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI,\
- DEVICE_PSTREAM_CFG_REG_ADDR);
-
-/* EMAC MDIO Registers Structure */
-struct mdio_regs {
- dv_reg version;
- dv_reg control;
- dv_reg alive;
- dv_reg link;
- dv_reg linkintraw;
- dv_reg linkintmasked;
- u_int8_t rsvd0[8];
- dv_reg userintraw;
- dv_reg userintmasked;
- dv_reg userintmaskset;
- dv_reg userintmaskclear;
- u_int8_t rsvd1[80];
- dv_reg useraccess0;
- dv_reg userphysel0;
- dv_reg useraccess1;
- dv_reg userphysel1;
-};
-
-/* Ethernet MAC Registers Structure */
-struct emac_regs {
- dv_reg idver;
- dv_reg maccontrol;
- dv_reg macstatus;
- dv_reg soft_reset;
- dv_reg rx_maxlen;
- u32 rsvd0;
- dv_reg rx_pause;
- dv_reg tx_pause;
- dv_reg emcontrol;
- dv_reg pri_map;
- u32 rsvd1[6];
-};
-
-#define SGMII_ACCESS(port, reg) \
- *((volatile unsigned int *)(sgmiis[port] + reg))
-
-struct eth_priv_t {
- char int_name[32];
- int rx_flow;
- int phy_addr;
- int slave_port;
- int sgmii_link_type;
-};
-
-extern struct eth_priv_t eth_priv_cfg[];
-
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
-void sgmii_serdes_setup_156p25mhz(void);
-void sgmii_serdes_shutdown(void);
-
-#endif /* _EMAC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
index 62172a4b84..df499957e5 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
@@ -34,11 +34,32 @@
#define KS2_LPSC_PCIE_1 27
#define KS2_LPSC_XGE 50
+/* MSMC */
+#define KS2_MSMC_SEGMENT_PCIE1 13
+
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES2_BASE 0x02324000
+#define KS2_LANES_PER_SGMII_SERDES 4
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 1
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x24186000
+#define KS2_NETCP_PDMA_TX_BASE 0x24187000
+#define KS2_NETCP_PDMA_TX_CH_NUM 21
+#define KS2_NETCP_PDMA_RX_BASE 0x24188000
+#define KS2_NETCP_PDMA_RX_CH_NUM 91
+#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
+
+/* NETCP */
+#define KS2_NETCP_BASE 0x24000000
+
#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index eb132f73e6..195c0d3003 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -10,8 +10,6 @@
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
@@ -81,7 +79,28 @@
#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
#define KS2_DDR3B_DDRPHYC 0x02328000
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2
+ channel 29 */
+
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES 4
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 8
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x02004000
+#define KS2_NETCP_PDMA_TX_BASE 0x02004400
+#define KS2_NETCP_PDMA_TX_CH_NUM 9
+#define KS2_NETCP_PDMA_RX_BASE 0x02004800
+#define KS2_NETCP_PDMA_RX_CH_NUM 26
+#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00
+#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 32
+#define KS2_NETCP_PDMA_TX_SND_QUEUE 648
+
+/* NETCP */
+#define KS2_NETCP_BASE 0x02000000
+
#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
new file mode 100644
index 0000000000..4f1197ea92
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -0,0 +1,108 @@
+/*
+ * K2L: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2L_H
+#define __ASM_ARCH_HARDWARE_K2L_H
+
+#define KS2_ARM_PLL_EN BIT(13)
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x26000000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DFE_IQN_SYS 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI 3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PA KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO 9
+#define KS2_LPSC_PCIE0 10
+#define KS2_LPSC_PCIE1 11
+#define KS2_LPSC_JESD_MISC 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_EMIF4F_DDR3 23
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_DDUC4X_CFR2X_BB 27
+#define KS2_LPSC_FFTC_A 28
+#define KS2_LPSC_OSR 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 37
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_VCP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DPD4X 48
+#define KS2_LPSC_FFTC_B 49
+#define KS2_LPSC_IQN_AIL 50
+
+/* MSMC */
+#define KS2_MSMC_SEGMENT_PCIE1 14
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+
+/* OSR */
+#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */
+#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
+#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */
+#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */
+#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS 4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE 0x100000
+
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES2_BASE 0x02320000
+#define KS2_LANES_PER_SGMII_SERDES 2
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
+#define KS2_NETCP_PDMA_TX_BASE 0x26187000
+#define KS2_NETCP_PDMA_TX_CH_NUM 21
+#define KS2_NETCP_PDMA_RX_BASE 0x26188000
+#define KS2_NETCP_PDMA_RX_CH_NUM 91
+#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
+
+/* NETCP */
+#define KS2_NETCP_BASE 0x26000000
+
+#endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 76e6441e57..be22bdb1ca 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -87,6 +87,56 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
+/* DDR3 ECC */
+#define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC
+#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4
+#define KS2_DDR3_ECC_CTRL_OFFSET 0x110
+#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114
+#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130
+#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C
+
+/* DDR3 ECC Interrupt Status register */
+#define KS2_DDR3_1B_ECC_ERR_SYS BIT(5)
+#define KS2_DDR3_2B_ECC_ERR_SYS BIT(4)
+#define KS2_DDR3_WR_ECC_ERR_SYS BIT(3)
+
+/* DDR3 ECC Control register */
+#define KS2_DDR3_ECC_EN BIT(31)
+#define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30)
+#define KS2_DDR3_ECC_VERIFY_EN BIT(29)
+#define KS2_DDR3_ECC_RMW_EN BIT(28)
+#define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0)
+
+#define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \
+ KS2_DDR3_ECC_ADDR_RNG_PROT | \
+ KS2_DDR3_ECC_VERIFY_EN)
+
+/* EDMA */
+#define KS2_EDMA0_BASE 0x02700000
+
+/* EDMA3 register offsets */
+#define KS2_EDMA_QCHMAP0 0x0200
+#define KS2_EDMA_IPR 0x1068
+#define KS2_EDMA_ICR 0x1070
+#define KS2_EDMA_QEECR 0x1088
+#define KS2_EDMA_QEESR 0x108c
+#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_BASE 0x02608000
+
+/* Chip Interrupt Controller register offsets */
+#define KS2_CIC_CTRL 0x04
+#define KS2_CIC_HOST_CTRL 0x0C
+#define KS2_CIC_GLOBAL_ENABLE 0x10
+#define KS2_CIC_SYS_ENABLE_IDX_SET 0x28
+#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
+#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
+
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
@@ -140,19 +190,51 @@ typedef volatile unsigned int *dv_reg_p;
/* Flag from ks2_debug options to check if DSPs need to stay ON */
#define DBG_LEAVE_DSPS_ON 0x1
+/* MSMC control */
+#define KS2_MSMC_CTRL_BASE 0x0bc00000
+#define KS2_MSMC_DATA_BASE 0x0c000000
+#define KS2_MSMC_SEGMENT_TETRIS 8
+#define KS2_MSMC_SEGMENT_NETCP 9
+#define KS2_MSMC_SEGMENT_QM_PDSP 10
+#define KS2_MSMC_SEGMENT_PCIE0 11
+
+/* MSMC segment size shift bits */
+#define KS2_MSMC_SEG_SIZE_SHIFT 12
+#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
+#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \
+ KS2_MSMC_SEG_SIZE_SHIFT)
+
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
/* Queue manager */
-#define KS2_QM_MANAGER_BASE 0x02a02000
+#define KS2_QM_BASE_ADDRESS 0x23a80000
+#define KS2_QM_CONF_BASE 0x02a02000
#define KS2_QM_DESC_SETUP_BASE 0x02a03000
-#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
+#define KS2_QM_STATUS_RAM_BASE 0x02a06000
+#define KS2_QM_INTD_CONF_BASE 0x02a0c000
+#define KS2_QM_PDSP1_CMD_BASE 0x02a20000
+#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000
+#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000
+#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000
#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
+#define KS2_QM_LINK_RAM_BASE 0x00100000
+#define KS2_QM_REGION_NUM 64
+#define KS2_QM_QPOOL_NUM 4000
-/* MSMC control */
-#define KS2_MSMC_CTRL_BASE 0x0bc00000
+/* USB */
+#define KS2_USB_SS_BASE 0x02680000
+#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000)
+#define KS2_DEV_USB_PHY_BASE 0x02620738
+#define KS2_USB_PHY_CFG_BASE 0x02630000
+
+#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES_BASE 0x0232a000
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
@@ -162,6 +244,10 @@ typedef volatile unsigned int *dv_reg_p;
#include <asm/arch/hardware-k2e.h>
#endif
+#ifdef CONFIG_SOC_K2L
+#include <asm/arch/hardware-k2l.h>
+#endif
+
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
@@ -179,6 +265,14 @@ static inline int cpu_is_k2e(void)
return (part_no == 0xb9a6) ? 1 : 0;
}
+static inline int cpu_is_k2l(void)
+{
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
+ unsigned int part_no = (jtag_id >> 12) & 0xffff;
+
+ return (part_no == 0xb9a7) ? 1 : 0;
+}
+
static inline int cpu_revision(void)
{
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h
index c320db5b65..083f5ba052 100644
--- a/arch/arm/include/asm/arch-keystone/msmc.h
+++ b/arch/arm/include/asm/arch-keystone/msmc.h
@@ -12,6 +12,34 @@
#include <asm/arch/hardware.h>
+enum mpax_seg_size {
+ MPAX_SEG_4K = 0x0b,
+ MPAX_SEG_8K,
+ MPAX_SEG_16K,
+ MPAX_SEG_32K,
+ MPAX_SEG_64K,
+ MPAX_SEG_128K,
+ MPAX_SEG_256K,
+ MPAX_SEG_512K,
+ MPAX_SEG_1M,
+ MPAX_SEG_2M,
+ MPAX_SEG_4M,
+ MPAX_SEG_8M,
+ MPAX_SEG_16M,
+ MPAX_SEG_32M,
+ MPAX_SEG_64M,
+ MPAX_SEG_128M,
+ MPAX_SEG_256M,
+ MPAX_SEG_512M,
+ MPAX_SEG_1G,
+ MPAX_SEG_2G,
+ MPAX_SEG_4G
+};
+
void msmc_share_all_segments(int priv_id);
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size);
#endif
diff --git a/arch/arm/include/asm/arch-keystone/spl.h b/arch/arm/include/asm/arch-keystone/spl.h
deleted file mode 100644
index a7102d5640..0000000000
--- a/arch/arm/include/asm/arch-keystone/spl.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012-2014
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_SPI 2
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/xhci-keystone.h b/arch/arm/include/asm/arch-keystone/xhci-keystone.h
new file mode 100644
index 0000000000..3aab4e045f
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/xhci-keystone.h
@@ -0,0 +1,21 @@
+/*
+ * USB 3.0 DRD Controller
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define USB3_PHY_REF_SSP_EN BIT(29)
+#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16)
+
+/* KEYSTONE2 XHCI PHY register structure */
+struct keystone_xhci_phy {
+ unsigned int phy_utmi; /* ctl0 */
+ unsigned int phy_pipe; /* ctl1 */
+ unsigned int phy_param_ctrl_1; /* ctl2 */
+ unsigned int phy_param_ctrl_2; /* ctl3 */
+ unsigned int phy_clock; /* ctl4 */
+ unsigned int phy_pll; /* ctl5 */
+};
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index e67b5b9e7d..39f3c0707b 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -89,7 +89,7 @@ struct mxc_ccm_reg {
u32 analog_pll_video_tog;
u32 analog_pll_video_num; /* 0x40b0 */
u32 analog_reserved6[3];
- u32 analog_pll_vedio_denon; /* 0x40c0 */
+ u32 analog_pll_video_denom; /* 0x40c0 */
u32 analog_reserved7[7];
u32 analog_pll_enet; /* 0x40e0 */
u32 analog_pll_enet_set;
@@ -228,6 +228,8 @@ struct mxc_ccm_reg {
#ifdef CONFIG_MX6SX
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
+#endif
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
#endif
@@ -931,10 +933,10 @@ struct mxc_ccm_reg {
#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
+ (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4512..d9db58c9a3 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -14,12 +14,31 @@ enum {
MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0),
MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 09dfc90a9b..062f3de1d0 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -10,6 +10,8 @@
#ifndef __SYS_PROTO_H__
#define __SYS_PROTO_H__
+#include <asm/imx-common/regs-common.h>
+
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg,
uint32_t mask,
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index 2f8320629b..eba4a5c7f0 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -281,7 +281,7 @@
#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
-#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C
+#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C
#define CONTROL_PADCONF_JTAG_TCK 0x0A1E
#define CONTROL_PADCONF_JTAG_TMS 0x0A20
#define CONTROL_PADCONF_JTAG_TDI 0x0A22
@@ -443,7 +443,7 @@
#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C)
#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6)
-#define MUX_VAL(OFFSET,VALUE)\
+#define MUX_VAL(OFFSET, VALUE)\
writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
#define CP(x) (CONTROL_PADCONF_##x)
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 5866bf23e8..34bd8c509a 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -64,6 +64,7 @@ void try_unlock_memory(void);
u32 get_boot_type(void);
void invalidate_dcache(u32);
u32 wait_on_value(u32, u32, void *, u32);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
void omap_nand_switch_ecc(uint32_t, uint32_t);
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index 027e9b1b14..9c1439b764 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -385,6 +385,8 @@
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F000000
#define PLL0_STC_BIT 24
+#define PLLECR 0xE61500D0
+#define PLL0ST 0x100
#ifndef __ASSEMBLY__
#include <asm/types.h>
diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
deleted file mode 100644
index 7e310d5a0c..0000000000
--- a/arch/arm/include/asm/arch-socfpga/spl.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2012 Pavel Machek <pavel@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SOCFPGA_SPL_H_
-#define _SOCFPGA_SPL_H_
-
-/* Symbols from linker script */
-extern char __malloc_start, __malloc_end, __stack_start;
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 5669f392fa..42382a8ae2 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -15,12 +15,17 @@
#define CLK_GATE_CLOSE 0x0
/* clock control module regs definition */
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#include <asm/arch/clock_sun6i.h>
+#else
#include <asm/arch/clock_sun4i.h>
+#endif
#ifndef __ASSEMBLY__
int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(unsigned int hz);
+unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
void clock_init_safe(void);
void clock_init_uart(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 1ba997adf9..90af8e2506 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -199,13 +199,16 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
+#define CCM_PLL5_CTRL_K_SHIFT 4
#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
#define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
#define CCM_PLL5_CTRL_LDO (0x1 << 7)
#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_N_SHIFT 8
#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
#define CCM_PLL5_CTRL_N_X(n) (n)
#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
+#define CCM_PLL5_CTRL_P_SHIFT 16
#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
#define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
#define CCM_PLL5_CTRL_BW (0x1 << 18)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
new file mode 100644
index 0000000000..1397b35889
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -0,0 +1,205 @@
+/*
+ * sun6i clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN6I_H
+#define _SUNXI_CLOCK_SUN6I_H
+
+struct sunxi_ccm_reg {
+ u32 pll1_cfg; /* 0x00 pll1 control */
+ u32 reserved0;
+ u32 pll2_cfg; /* 0x08 pll2 control */
+ u32 reserved1;
+ u32 pll3_cfg; /* 0x10 pll3 control */
+ u32 reserved2;
+ u32 pll4_cfg; /* 0x18 pll4 control */
+ u32 reserved3;
+ u32 pll5_cfg; /* 0x20 pll5 control */
+ u32 reserved4;
+ u32 pll6_cfg; /* 0x28 pll6 control */
+ u32 reserved5;
+ u32 pll7_cfg; /* 0x30 pll7 control */
+ u32 reserved6;
+ u32 pll8_cfg; /* 0x38 pll8 control */
+ u32 reserved7;
+ u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
+ u32 pll9_cfg; /* 0x44 pll9 control */
+ u32 pll10_cfg; /* 0x48 pll10 control */
+ u32 reserved8;
+ u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
+ u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
+ u32 apb2_div; /* 0x58 APB2 divide ratio */
+ u32 axi_gate; /* 0x5c axi module clock gating */
+ u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
+ u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
+ u32 apb1_gate; /* 0x68 apb1 module clock gating */
+ u32 apb2_gate; /* 0x6c apb2 module clock gating */
+ u32 reserved9[4];
+ u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
+ u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
+ u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
+ u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
+ u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
+ u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
+ u32 ts_clk_cfg; /* 0x98 transport stream clock control */
+ u32 ss_clk_cfg; /* 0x9c security system clock control */
+ u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */
+ u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */
+ u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */
+ u32 spi3_clk_cfg; /* 0xac spi3 clock control */
+ u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/
+ u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
+ u32 reserved10[2];
+ u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
+ u32 reserved11[2];
+ u32 usb_clk_cfg; /* 0xcc USB clock control */
+ u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
+ u32 reserved12[7];
+ u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
+ u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
+ u32 reserved13[2];
+ u32 dram_clk_gate; /* 0x100 DRAM module gating */
+ u32 be0_clk_cfg; /* 0x104 BE0 module clock */
+ u32 be1_clk_cfg; /* 0x108 BE1 module clock */
+ u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
+ u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
+ u32 mp_clk_cfg; /* 0x114 MP module clock */
+ u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
+ u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
+ u32 reserved14[3];
+ u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
+ u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
+ u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */
+ u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */
+ u32 ve_clk_cfg; /* 0x13c VE module clock */
+ u32 adda_clk_cfg; /* 0x140 ADDA module clock */
+ u32 avs_clk_cfg; /* 0x144 AVS module clock */
+ u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
+ u32 reserved15;
+ u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
+ u32 ps_clk_cfg; /* 0x154 PS module clock */
+ u32 mtc_clk_cfg; /* 0x158 MTC module clock */
+ u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
+ u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
+ u32 reserved16;
+ u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
+ u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
+ u32 reserved17[4];
+ u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */
+ u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */
+ u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */
+ u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */
+ u32 reserved18[4];
+ u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */
+ u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */
+ u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */
+ u32 reserved19[21];
+ u32 pll_lock; /* 0x200 PLL Lock Time */
+ u32 pll1_lock; /* 0x204 PLL1 Lock Time */
+ u32 reserved20[6];
+ u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */
+ u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */
+ u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */
+ u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
+ u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
+ u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
+ u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
+ u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */
+ u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
+ u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
+ u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
+ u32 reserved21[13];
+ u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
+ u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
+ u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
+ u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */
+ u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
+ u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
+ u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
+ u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */
+ u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
+ u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
+ u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
+ u32 reserved22[5];
+ u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
+ u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
+ u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
+ u32 reserved23;
+ u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
+ u32 reserved24;
+ u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
+};
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_LOSC (0x0 << 24)
+#define APB2_CLK_SRC_OSC24M (0x1 << 24)
+#define APB2_CLK_SRC_PLL6 (0x2 << 24)
+#define APB2_CLK_SRC_MASK (0x3 << 24)
+#define APB2_CLK_RATE_N_1 (0x0 << 16)
+#define APB2_CLK_RATE_N_2 (0x1 << 16)
+#define APB2_CLK_RATE_N_4 (0x2 << 16)
+#define APB2_CLK_RATE_N_8 (0x3 << 16)
+#define APB2_CLK_RATE_N_MASK (3 << 16)
+#define APB2_CLK_RATE_M(m) (((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK (0x1f << 0)
+
+/* apb2 gate field */
+#define APB2_GATE_UART_SHIFT (16)
+#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT)
+#define APB2_GATE_TWI_SHIFT (0)
+#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
+
+/* cpu_axi_cfg bits */
+#define AXI_DIV_SHIFT 0
+#define ATB_DIV_SHIFT 8
+#define CPU_CLK_SRC_SHIFT 16
+
+#define AXI_DIV_1 0
+#define AXI_DIV_2 1
+#define AXI_DIV_3 2
+#define AXI_DIV_4 3
+#define ATB_DIV_1 0
+#define ATB_DIV_2 1
+#define ATB_DIV_4 2
+#define CPU_CLK_SRC_OSC24M 1
+#define CPU_CLK_SRC_PLL1 2
+
+#define PLL1_CFG_DEFAULT 0x90011b21
+
+#define PLL6_CFG_DEFAULT 0x90041811
+
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT 4
+#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+
+#define AHB_GATE_OFFSET_MMC3 11
+#define AHB_GATE_OFFSET_MMC2 10
+#define AHB_GATE_OFFSET_MMC1 9
+#define AHB_GATE_OFFSET_MMC0 8
+#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
+
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+
+#define AHB_RESET_OFFSET_MMC3 11
+#define AHB_RESET_OFFSET_MMC2 10
+#define AHB_RESET_OFFSET_MMC1 9
+#define AHB_RESET_OFFSET_MMC0 8
+#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
+
+/* apb2 reset */
+#define APB2_RESET_UART_SHIFT (16)
+#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
+#define APB2_RESET_TWI_SHIFT (0)
+#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
+
+#endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index a987e51d57..0de79a0d50 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -95,6 +95,11 @@
#define SUNXI_MALI400_BASE 0x01c40000
#define SUNXI_GMAC_BASE 0x01c50000
+#define SUNXI_DRAM_COM_BASE 0x01c62000
+#define SUNXI_DRAM_CTL_BASE 0x01c63000
+#define SUNXI_DRAM_PHY_CH1_BASE 0x01c65000
+#define SUNXI_DRAM_PHY_CH2_BASE 0x01c66000
+
/* module sram */
#define SUNXI_SRAM_C_BASE 0x01d00000
@@ -105,6 +110,11 @@
#define SUNXI_MP_BASE 0x01e80000
#define SUNXI_AVG_BASE 0x01ea0000
+#define SUNXI_PRCM_BASE 0x01f01400
+#define SUNXI_R_UART_BASE 0x01f02800
+#define SUNXI_R_PIO_BASE 0x01f02c00
+#define SUNXI_P2WI_BASE 0x01f03400
+
/* CoreSight Debug Module */
#define SUNXI_CSDM_BASE 0x3f500000
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f7f3d8c41a..437dd35b68 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -10,6 +10,7 @@
#define _SUNXI_GPIO_H
#include <linux/types.h>
+#include <asm/arch/cpu.h>
/*
* sunxi has 9 banks of gpio, they are:
@@ -27,8 +28,27 @@
#define SUNXI_GPIO_G 6
#define SUNXI_GPIO_H 7
#define SUNXI_GPIO_I 8
+
+/*
+ * This defines the number of GPIO banks for the _main_ GPIO controller.
+ * You should fix up the padding in struct sunxi_gpio_reg below if you
+ * change this.
+ */
#define SUNXI_GPIO_BANKS 9
+/*
+ * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
+ * at a different register offset.
+ *
+ * sun6i has 2 banks:
+ * PL0 - PL8 | PM0 - PM7
+ *
+ * sun8i has 1 bank:
+ * PL0 - PL11
+ */
+#define SUNXI_GPIO_L 11
+#define SUNXI_GPIO_M 12
+
struct sunxi_gpio {
u32 cfg[4];
u32 dat;
@@ -50,8 +70,9 @@ struct sunxi_gpio_reg {
struct sunxi_gpio_int gpio_int;
};
-#define BANK_TO_GPIO(bank) \
- &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]
+#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
+ &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
+ &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
#define GPIO_BANK(pin) ((pin) >> 5)
#define GPIO_NUM(pin) ((pin) & 0x1f)
@@ -75,6 +96,8 @@ struct sunxi_gpio_reg {
#define SUNXI_GPIO_G_NR 32
#define SUNXI_GPIO_H_NR 32
#define SUNXI_GPIO_I_NR 32
+#define SUNXI_GPIO_L_NR 32
+#define SUNXI_GPIO_M_NR 32
#define SUNXI_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + 0)
@@ -89,6 +112,8 @@ enum sunxi_gpio_number {
SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
+ SUNXI_GPIO_L_START = 352,
+ SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
};
/* SUNXI GPIO number definitions */
@@ -101,6 +126,8 @@ enum sunxi_gpio_number {
#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
+#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
+#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
/* GPIO pin function config */
#define SUNXI_GPIO_INPUT 0
@@ -117,6 +144,8 @@ enum sunxi_gpio_number {
#define SUN5I_GPB19_UART0_TX 2
#define SUN5I_GPB20_UART0_RX 2
+#define SUN5I_GPG3_SDC1 2
+
#define SUN5I_GPG3_UART1_TX 4
#define SUN5I_GPG4_UART1_RX 4
@@ -125,21 +154,35 @@ enum sunxi_gpio_number {
#define SUNXI_GPF0_SDC0 2
#define SUNXI_GPF2_SDC0 2
+
+#ifdef CONFIG_MACH_SUN8I
+#define SUNXI_GPF2_UART0_TX 3
+#define SUNXI_GPF4_UART0_RX 3
+#else
#define SUNXI_GPF2_UART0_TX 4
#define SUNXI_GPF4_UART0_RX 4
+#endif
#define SUN4I_GPG0_SDC1 4
#define SUN4I_GPH22_SDC1 5
+#define SUN6I_GPH20_UART0_TX 2
+#define SUN6I_GPH21_UART0_RX 2
+
#define SUN4I_GPI4_SDC3 2
+#define SUN8I_GPL2_R_UART_TX 2
+#define SUN8I_GPL3_R_UART_RX 2
+
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE 0
#define SUNXI_GPIO_PULL_UP 1
#define SUNXI_GPIO_PULL_DOWN 2
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 53196e3b02..537f145564 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,7 +43,10 @@ struct sunxi_mmc {
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res1[26];
- u32 fifo; /* 0x100 FIFO access address */
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+ u32 res2[64];
+#endif
+ u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */
};
#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
@@ -120,5 +123,5 @@ struct sunxi_mmc {
#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
-int sunxi_mmc_init(int sdc_no);
+struct mmc *sunxi_mmc_init(int sdc_no);
#endif /* _SUNXI_MMC_H */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
new file mode 100644
index 0000000000..3d3bfa6cd1
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -0,0 +1,238 @@
+/*
+ * Sunxi A31 Power Management Unit register definition.
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_PRCM_H
+#define _SUNXI_PRCM_H
+
+#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
+#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
+#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
+#define PRCM_CPUS_CFG_PRE_DIV(n) \
+ __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
+#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
+#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
+#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
+#define PRCM_CPUS_CFG_POST_DIV(n) \
+ __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
+#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
+#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
+#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
+#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
+#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
+#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
+#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
+#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
+
+#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)
+#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
+#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
+#define PRCM_APB0_RATIO_DIV(n) \
+ __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
+
+#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
+#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
+
+#define PRCM_APB0_GATE_PIO (0x1 << 0)
+#define PRCM_APB0_GATE_IR (0x1 << 1)
+#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
+#define PRCM_APB0_GATE_P2WI (0x1 << 3)
+#define PRCM_APB0_GATE_UART (0x1 << 4)
+#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
+#define PRCM_APB0_GATE_I2C (0x1 << 6)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
+#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
+#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
+#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
+#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
+#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
+#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
+#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
+#define PRCM_PLL_CTRL_USB_CLK_0 \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
+#define PRCM_PLL_CTRL_USB_CLK_1 \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
+#define PRCM_PLL_CTRL_USB_CLK_2 \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
+#define PRCM_PLL_CTRL_USB_CLK_3 \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)
+#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \
+ __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \
+ __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)
+#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)
+#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)
+#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0
+#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1
+#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2
+#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3
+#define PRCM_PLL_CTRL_HOSC_CLK_0 \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)
+#define PRCM_PLL_CTRL_HOSC_CLK_1 \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)
+#define PRCM_PLL_CTRL_HOSC_CLK_2 \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)
+#define PRCM_PLL_CTRL_HOSC_CLK_3 \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)
+#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)
+#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)
+#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)
+#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)
+#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)
+#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */
+#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)
+#define PRCM_PLL_CTRL_LDO_OUT_MASK \
+ __PRCM_PLL_CTRL_LDO_OUT(0x7)
+/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
+#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
+#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+
+#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
+
+#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)
+#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)
+#define __PRCM_CLK_MOD0_M_X(n) (n - 1)
+#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))
+#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)
+#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)
+#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)
+#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))
+#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)
+#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)
+#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)
+#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)
+#define __PRCM_CLK_OUTD_M_X() ((n) - 1)
+#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))
+#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)
+#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)
+#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)
+#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)
+#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0
+#define __PRCM_CLK_OUTD_SRC_LOSC 0x1
+#define __PRCM_CLK_OUTD_SRC_HOSC 0x2
+#define __PRCM_CLK_OUTD_SRC_ERR 0x3
+#define PRCM_CLK_OUTD_SRC_LOSC2 \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)
+#define PRCM_CLK_OUTD_SRC_LOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)
+#define PRCM_CLK_OUTD_SRC_HOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)
+#define PRCM_CLK_OUTD_SRC_ERR \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)
+#define PRCM_CLK_OUTD_EN (0x1 << 31)
+
+#define PRCM_CPU0_PWROFF (0x1 << 0)
+#define PRCM_CPU1_PWROFF (0x1 << 1)
+#define PRCM_CPU2_PWROFF (0x1 << 2)
+#define PRCM_CPU3_PWROFF (0x1 << 3)
+#define PRCM_CPU_ALL_PWROFF (0xf << 0)
+
+#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)
+#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)
+#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)
+#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)
+
+#define PRCM_VDD_GPU_PWROFF (0x1 << 0)
+
+#define PRCM_VDD_SYS_RESET (0x1 << 0)
+
+#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)
+
+#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)
+
+#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
+
+#ifndef __ASSEMBLY__
+struct sunxi_prcm_reg {
+ u32 cpus_cfg; /* 0x000 */
+ u8 res0[0x8]; /* 0x004 */
+ u32 apb0_ratio; /* 0x00c */
+ u32 cpu0_cfg; /* 0x010 */
+ u32 cpu1_cfg; /* 0x014 */
+ u32 cpu2_cfg; /* 0x018 */
+ u32 cpu3_cfg; /* 0x01c */
+ u8 res1[0x8]; /* 0x020 */
+ u32 apb0_gate; /* 0x028 */
+ u8 res2[0x14]; /* 0x02c */
+ u32 pll_ctrl0; /* 0x040 */
+ u32 pll_ctrl1; /* 0x044 */
+ u8 res3[0x8]; /* 0x048 */
+ u32 clk_1wire; /* 0x050 */
+ u32 clk_ir; /* 0x054 */
+ u8 res4[0x58]; /* 0x058 */
+ u32 apb0_reset; /* 0x0b0 */
+ u8 res5[0x3c]; /* 0x0b4 */
+ u32 clk_outd; /* 0x0f0 */
+ u8 res6[0xc]; /* 0x0f4 */
+ u32 cpu_pwroff; /* 0x100 */
+ u8 res7[0xc]; /* 0x104 */
+ u32 vdd_sys_pwroff; /* 0x110 */
+ u8 res8[0x4]; /* 0x114 */
+ u32 gpu_pwroff; /* 0x118 */
+ u8 res9[0x4]; /* 0x11c */
+ u32 vdd_pwr_reset; /* 0x120 */
+ u8 res10[0x20]; /* 0x124 */
+ u32 cpu1_pwr_clamp; /* 0x144 */
+ u32 cpu2_pwr_clamp; /* 0x148 */
+ u32 cpu3_pwr_clamp; /* 0x14c */
+ u8 res11[0x30]; /* 0x150 */
+ u32 dram_pwr; /* 0x180 */
+ u8 res12[0xc]; /* 0x184 */
+ u32 dram_tst; /* 0x190 */
+};
+
+void prcm_apb0_enable(u32 flags);
+#endif /* __ASSEMBLY__ */
+#endif /* _PRCM_H */
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index 58e14fd0f7..9a5e488a38 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -11,14 +11,10 @@
#ifndef _SUNXI_TIMER_H_
#define _SUNXI_TIMER_H_
-#define WDT_CTRL_RESTART (0x1 << 0)
-#define WDT_CTRL_KEY (0x0a57 << 1)
-#define WDT_MODE_EN (0x1 << 0)
-#define WDT_MODE_RESET_EN (0x1 << 1)
-
#ifndef __ASSEMBLY__
#include <linux/types.h>
+#include <asm/arch/watchdog.h>
/* General purpose timer */
struct sunxi_timer {
@@ -43,12 +39,6 @@ struct sunxi_64cnt {
u32 hi; /* 0xa8 */
};
-/* Watchdog */
-struct sunxi_wdog {
- u32 ctl; /* 0x90 */
- u32 mode; /* 0x94 */
-};
-
/* Rtc */
struct sunxi_rtc {
u32 ctl; /* 0x100 */
@@ -77,15 +67,20 @@ struct sunxi_timer_reg {
struct sunxi_timer timer[6]; /* We have 6 timers */
u8 res2[16];
struct sunxi_avs avs;
- struct sunxi_wdog wdog;
- u8 res3[8];
- struct sunxi_64cnt cnt64;
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+ struct sunxi_wdog wdog; /* 0x90 */
+ /* XXX the following is not accurate for sun5i/sun7i */
+ struct sunxi_64cnt cnt64; /* 0xa0 */
u8 res4[0x58];
struct sunxi_rtc rtc;
struct sunxi_alarm alarm;
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */
+ u8 res3[16];
+ struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
+#endif
};
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h
new file mode 100644
index 0000000000..8108be97ba
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/watchdog.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2014
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * Watchdog register definitions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_WATCHDOG_H_
+#define _SUNXI_WATCHDOG_H_
+
+#define WDT_CTRL_RESTART (0x1 << 0)
+#define WDT_CTRL_KEY (0x0a57 << 1)
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+
+#define WDT_MODE_EN (0x1 << 0)
+#define WDT_MODE_RESET_EN (0x1 << 1)
+
+struct sunxi_wdog {
+ u32 ctl; /* 0x00 */
+ u32 mode; /* 0x04 */
+ u32 res[2];
+};
+
+#else
+
+#define WDT_CFG_RESET (0x1)
+#define WDT_MODE_EN (0x1)
+
+struct sunxi_wdog {
+ u32 irq_en; /* 0x00 */
+ u32 irq_sta; /* 0x04 */
+ u32 res1[2];
+ u32 ctl; /* 0x10 */
+ u32 cfg; /* 0x14 */
+ u32 mode; /* 0x18 */
+ u32 res2;
+};
+
+#endif
+
+#endif /* _SUNXI_WATCHDOG_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
index ff773646cb..783bb3c0fa 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -24,10 +24,11 @@ void gpio_early_init(void); /* overrideable GPIO config */
* an empty stub function will be called.
*/
-void pinmux_init(void); /* overrideable general pinmux setup */
-void pin_mux_usb(void); /* overrideable USB pinmux setup */
-void pin_mux_spi(void); /* overrideable SPI pinmux setup */
-void pin_mux_nand(void); /* overrideable NAND pinmux setup */
-void pin_mux_display(void); /* overrideable DISPLAY pinmux setup */
+void pinmux_init(void); /* overridable general pinmux setup */
+void pin_mux_usb(void); /* overridable USB pinmux setup */
+void pin_mux_spi(void); /* overridable SPI pinmux setup */
+void pin_mux_nand(void); /* overridable NAND pinmux setup */
+void pin_mux_mmc(void); /* overridable mmc pinmux setup */
+void pin_mux_display(void); /* overridable DISPLAY pinmux setup */
#endif
diff --git a/arch/arm/include/asm/arch-uniphier/platdevice.h b/arch/arm/include/asm/arch-uniphier/platdevice.h
new file mode 100644
index 0000000000..cdf7d132d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/platdevice.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_PLATDEVICE_H
+#define ARCH_PLATDEVICE_H
+
+#include <dm/platdata.h>
+#include <dm/platform_data/serial-uniphier.h>
+
+#define SERIAL_DEVICE(n, ba, clk) \
+static struct uniphier_serial_platform_data serial_device##n = { \
+ .base = ba, \
+ .uartclk = clk \
+}; \
+U_BOOT_DEVICE(serial##n) = { \
+ .name = DRIVER_NAME, \
+ .platdata = &serial_device##n \
+};
+
+#endif /* ARCH_PLATDEVICE_H */
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index a8ca49c343..e0a49be4ff 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -182,6 +182,11 @@ typedef u64 iomux_v3_cfg_t;
void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/*
+* Set bits for general purpose registers
+*/
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value);
/* macros for declaring and using pinmux array */
#if defined(CONFIG_MX6QDL)
diff --git a/arch/arm/include/asm/imx-common/spi.h b/arch/arm/include/asm/imx-common/spi.h
new file mode 100644
index 0000000000..1d4473a04a
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/spi.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MXC_SPI_H_
+#define __MXC_SPI_H_
+
+/*
+ * Board-level chip-select callback
+ * Should return GPIO # to be used for chip-select
+ */
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs);
+
+#endif
diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h
index 2d948508d5..1a907d44e4 100644
--- a/arch/arm/include/asm/imx-common/video.h
+++ b/arch/arm/include/asm/imx-common/video.h
@@ -21,4 +21,9 @@ struct display_info_t {
extern int detect_hdmi(struct display_info_t const *dev);
#endif
+#ifdef CONFIG_IMX_VIDEO_SKIP
+extern struct display_info_t const displays[];
+extern size_t display_count;
+#endif
+
#endif
diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h
index 5d25d04c3b..839af54d48 100644
--- a/arch/arm/include/asm/omap_gpio.h
+++ b/arch/arm/include/asm/omap_gpio.h
@@ -23,6 +23,21 @@
#include <asm/arch/cpu.h>
+enum gpio_method {
+ METHOD_GPIO_24XX = 4,
+};
+
+#ifdef CONFIG_DM_GPIO
+
+/* Information about a GPIO bank */
+struct omap_gpio_platdata {
+ int bank_index;
+ ulong base; /* address of registers in physical memory */
+ enum gpio_method method;
+};
+
+#else
+
struct gpio_bank {
void *base;
int method;
@@ -30,8 +45,6 @@ struct gpio_bank {
extern const struct gpio_bank *const omap_gpio_bank;
-#define METHOD_GPIO_24XX 4
-
/**
* Check if gpio is valid.
*
@@ -39,4 +52,6 @@ extern const struct gpio_bank *const omap_gpio_bank;
* @return 1 if ok, 0 on error
*/
int gpio_is_valid(int gpio);
+#endif
+
#endif /* _GPIO_H_ */
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index e5daf89127..8acd7cd1bd 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -7,7 +7,7 @@
#ifndef _ASM_SPL_H_
#define _ASM_SPL_H_
-#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) \
+#if defined(CONFIG_OMAP) \
|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
|| defined(CONFIG_EXYNOS4210)
/* Platform-specific defines */
diff --git a/arch/arm/include/asm/arch-keystone/keystone_nav.h b/arch/arm/include/asm/ti-common/keystone_nav.h
index ab81eaf1fd..696d8c6fc0 100644
--- a/arch/arm/include/asm/arch-keystone/keystone_nav.h
+++ b/arch/arm/include/asm/ti-common/keystone_nav.h
@@ -13,10 +13,6 @@
#include <asm/arch/hardware.h>
#include <asm/io.h>
-enum soc_type_t {
- k2hk
-};
-
#define QM_OK 0
#define QM_ERR -1
#define QM_DESC_TYPE_HOST 0
@@ -173,6 +169,8 @@ struct pktdma_cfg {
u32 rx_flow; /* flow that is used for RX */
};
+extern struct pktdma_cfg netcp_pktdma;
+
/*
* packet dma user allocates memory for rx buffers
* and describe it in the following structure
@@ -184,10 +182,10 @@ struct rx_buff_desc {
u32 rx_flow;
};
-int netcp_close(void);
-int netcp_init(struct rx_buff_desc *rx_buffers);
-int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
-void *netcp_recv(u32 **pkt, int *num_bytes);
-void netcp_release_rxhd(void *hd);
+int ksnav_close(struct pktdma_cfg *pktdma);
+int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2);
+void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
+void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
#endif /* _KEYSTONE_NAV_H_ */
diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h
new file mode 100644
index 0000000000..011c03cf88
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -0,0 +1,249 @@
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _KEYSTONE_NET_H_
+#define _KEYSTONE_NET_H_
+
+#include <asm/io.h>
+
+/* EMAC */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000)
+#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900)
+#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300)
+#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100)
+#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL 0x04
+#define CPGMACSL_REG_STATUS 0x08
+#define CPGMACSL_REG_RESET 0x0c
+#define CPGMACSL_REG_MAXLEN 0x10
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000)
+#define CPGMACSL_REG_RX_PRI_MAP 0x020
+#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000)
+#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00)
+#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100)
+#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL 0x330
+#define CPGMACSL_REG_STATUS 0x334
+#define CPGMACSL_REG_RESET 0x338
+#define CPGMACSL_REG_MAXLEN 0x024
+
+#endif
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE
+
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
+
+/* MII Status Register */
+#define MII_STATUS_REG 1
+#define MII_STATUS_LINK_MASK 0x4
+
+#define MDIO_CONTROL_IDLE 0x80000000
+#define MDIO_CONTROL_ENABLE 0x40000000
+#define MDIO_CONTROL_FAULT_ENABLE 0x40000
+#define MDIO_CONTROL_FAULT 0x80000
+#define MDIO_USERACCESS0_GO 0x80000000
+#define MDIO_USERACCESS0_WRITE_READ 0x0
+#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000
+#define MDIO_USERACCESS0_ACK 0x20000000
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1
+#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7)
+#define EMAC_MACCONTROL_GIGFORCE BIT(17)
+#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE 60
+
+struct mac_sl_cfg {
+ u_int32_t max_rx_len; /* Maximum receive packet length. */
+ u_int32_t ctl; /* Control bitfield */
+};
+
+/**
+ * Definition: Control bitfields used in the ctl field of mac_sl_cfg
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22)
+#define GMACSL_RX_ENABLE_EXT_CTL BIT(18)
+#define GMACSL_RX_ENABLE_GIG_FORCE BIT(17)
+#define GMACSL_RX_ENABLE_IFCTL_B BIT(16)
+#define GMACSL_RX_ENABLE_IFCTL_A BIT(15)
+#define GMACSL_RX_ENABLE_CMD_IDLE BIT(11)
+#define GMACSL_TX_ENABLE_SHORT_GAP BIT(10)
+#define GMACSL_ENABLE_GIG_MODE BIT(7)
+#define GMACSL_TX_ENABLE_PACE BIT(6)
+#define GMACSL_ENABLE BIT(5)
+#define GMACSL_TX_ENABLE_FLOW_CTL BIT(4)
+#define GMACSL_RX_ENABLE_FLOW_CTL BIT(3)
+#define GMACSL_ENABLE_LOOPBACK BIT(1)
+#define GMACSL_ENABLE_FULL_DUPLEX BIT(0)
+
+/* EMAC SL function return values */
+#define GMACSL_RET_OK 0
+#define GMACSL_RET_INVALID_PORT -1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
+
+/* EMAC SL register definitions */
+#define DEVICE_EMACSL_RESET_POLL_COUNT 100
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0)
+#define CPGMAC_REG_RESET_VAL_RESET BIT(0)
+#define CPGMAC_REG_MAXLEN_LEN 0x3fff
+
+/* CPSW */
+/* Control bitfields */
+#define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5)
+#define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4)
+#define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3)
+#define CPSW_CTL_P0_ENABLE BIT(2)
+#define CPSW_CTL_VLAN_AWARE BIT(1)
+#define CPSW_CTL_FIFO_LOOPBACK BIT(0)
+
+#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS
+#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1)
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_CPSW_BASE (GBETH_BASE + 0x800)
+#define CPSW_REG_CTL 0x004
+#define CPSW_REG_STAT_PORT_EN 0x00c
+#define CPSW_REG_MAXLEN 0x040
+#define CPSW_REG_ALE_CONTROL 0x608
+#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000)
+#define CPSW_REG_CTL 0x00004
+#define CPSW_REG_STAT_PORT_EN 0x00014
+#define CPSW_REG_MAXLEN 0x01024
+#define CPSW_REG_ALE_CONTROL 0x1e008
+#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff
+
+#endif
+
+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
+#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
+
+#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE
+#define SWITCH_MAX_PKT_SIZE 9000
+
+/* SGMII */
+#define SGMII_REG_STATUS_LOCK BIT(4)
+#define SGMII_REG_STATUS_LINK BIT(0)
+#define SGMII_REG_STATUS_AUTONEG BIT(2)
+#define SGMII_REG_CONTROL_AUTONEG BIT(0)
+#define SGMII_REG_CONTROL_MASTER BIT(5)
+#define SGMII_REG_MR_ADV_ENABLE BIT(0)
+#define SGMII_REG_MR_ADV_LINK BIT(15)
+#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
+#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
+
+#define SGMII_LINK_MAC_MAC_AUTONEG 0
+#define SGMII_LINK_MAC_PHY 1
+#define SGMII_LINK_MAC_MAC_FORCED 2
+#define SGMII_LINK_MAC_FIBER 3
+#define SGMII_LINK_MAC_PHY_FORCED 4
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
+#elif defined CONFIG_KSNET_NETCP_V1_5
+#define SGMII_OFFSET(x) ((x) * 0x100)
+#endif
+
+#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
+
+/* PSS */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606
+#define hw_config_streaming_switch()\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0
+
+#define hw_config_streaming_switch()\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR);\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR+4);\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR+8);\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR+12);
+
+#endif
+
+/* EMAC MDIO Registers Structure */
+struct mdio_regs {
+ u32 version;
+ u32 control;
+ u32 alive;
+ u32 link;
+ u32 linkintraw;
+ u32 linkintmasked;
+ u32 rsvd0[2];
+ u32 userintraw;
+ u32 userintmasked;
+ u32 userintmaskset;
+ u32 userintmaskclear;
+ u32 rsvd1[20];
+ u32 useraccess0;
+ u32 userphysel0;
+ u32 useraccess1;
+ u32 userphysel1;
+};
+
+struct eth_priv_t {
+ char int_name[32];
+ int rx_flow;
+ int phy_addr;
+ int slave_port;
+ int sgmii_link_type;
+ struct phy_device *phy_dev;
+};
+
+int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
+void sgmii_serdes_setup_156p25mhz(void);
+void sgmii_serdes_shutdown(void);
+
+#endif /* _KEYSTONE_NET_H_ */
diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h b/arch/arm/include/asm/ti-common/keystone_serdes.h
new file mode 100644
index 0000000000..2e92411404
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_serdes.h
@@ -0,0 +1,55 @@
+/*
+ * Texas Instruments Keystone SerDes driver
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TI_KEYSTONE_SERDES_H__
+#define __TI_KEYSTONE_SERDES_H__
+
+/* SERDES Reference clock */
+enum ks2_serdes_clock {
+ SERDES_CLOCK_100M, /* 100 MHz */
+ SERDES_CLOCK_122P88M, /* 122.88 MHz */
+ SERDES_CLOCK_125M, /* 125 MHz */
+ SERDES_CLOCK_156P25M, /* 156.25 MHz */
+ SERDES_CLOCK_312P5M, /* 312.5 MHz */
+};
+
+/* SERDES Lane Baud Rate */
+enum ks2_serdes_rate {
+ SERDES_RATE_4P9152G, /* 4.9152 GBaud */
+ SERDES_RATE_5G, /* 5 GBaud */
+ SERDES_RATE_6P144G, /* 6.144 GBaud */
+ SERDES_RATE_6P25G, /* 6.25 GBaud */
+ SERDES_RATE_10p3125g, /* 10.3215 GBaud */
+ SERDES_RATE_12p5g, /* 12.5 GBaud */
+};
+
+/* SERDES Lane Rate Mode */
+enum ks2_serdes_rate_mode {
+ SERDES_FULL_RATE,
+ SERDES_HALF_RATE,
+ SERDES_QUARTER_RATE,
+};
+
+/* SERDES PHY TYPE */
+enum ks2_serdes_interface {
+ SERDES_PHY_SGMII,
+ SERDES_PHY_PCSR, /* XGE SERDES */
+};
+
+struct ks2_serdes {
+ enum ks2_serdes_clock clk;
+ enum ks2_serdes_rate rate;
+ enum ks2_serdes_rate_mode rate_mode;
+ enum ks2_serdes_interface intf;
+ u32 loopback;
+};
+
+int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
+
+#endif /* __TI_KEYSTONE_SERDES_H__ */
diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h
new file mode 100644
index 0000000000..5adc1dac0e
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/ti-edma3.h
@@ -0,0 +1,121 @@
+/*
+ * Enhanced Direct Memory Access (EDMA3) Controller
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EDMA3_H_
+#define _EDMA3_H_
+
+#include <linux/stddef.h>
+
+#define EDMA3_PARSET_NULL_LINK 0xffff
+
+/*
+ * All parameter RAM set options
+ * opt field in edma3_param_set_config structure
+ */
+#define EDMA3_SLOPT_PRIV_LEVEL BIT(31)
+#define EDMA3_SLOPT_PRIV_ID(id) ((0xf & (id)) << 24)
+#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB BIT(23)
+#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB BIT(22)
+#define EDMA3_SLOPT_INTERM_COMP_INT_ENB BIT(21)
+#define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20)
+#define EDMA3_SLOPT_COMP_CODE(code) ((0x3f & (code)) << 12)
+#define EDMA3_SLOPT_FIFO_WIDTH_8 0
+#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_32 (2 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_64 (3 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_128 (4 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_256 (5 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_SET(w) ((w & 0x7) << 8)
+#define EDMA3_SLOPT_STATIC BIT(3)
+#define EDMA3_SLOPT_AB_SYNC BIT(2)
+#define EDMA3_SLOPT_DST_ADDR_CONST_MODE BIT(1)
+#define EDMA3_SLOPT_SRC_ADDR_CONST_MODE BIT(0)
+
+enum edma3_address_mode {
+ INCR = 0,
+ FIFO = 1
+};
+
+enum edma3_fifo_width {
+ W8BIT = 0,
+ W16BIT = 1,
+ W32BIT = 2,
+ W64BIT = 3,
+ W128BIT = 4,
+ W256BIT = 5
+};
+
+enum edma3_sync_dimension {
+ ASYNC = 0,
+ ABSYNC = 1
+};
+
+/* PaRAM slots are laid out like this */
+struct edma3_slot_layout {
+ u32 opt;
+ u32 src;
+ u32 a_b_cnt;
+ u32 dst;
+ u32 src_dst_bidx;
+ u32 link_bcntrld;
+ u32 src_dst_cidx;
+ u32 ccnt;
+} __packed;
+
+/*
+ * Use this to assign trigger word number of edma3_slot_layout struct.
+ * trigger_word_name - is the exact name from edma3_slot_layout.
+ */
+#define EDMA3_TWORD(trigger_word_name)\
+ (offsetof(struct edma3_slot_layout, trigger_word_name) / 4)
+
+struct edma3_slot_config {
+ u32 opt;
+ u32 src;
+ u32 dst;
+ int bcnt;
+ int acnt;
+ int ccnt;
+ int src_bidx;
+ int dst_bidx;
+ int src_cidx;
+ int dst_cidx;
+ int bcntrld;
+ int link;
+};
+
+struct edma3_channel_config {
+ int slot;
+ int chnum;
+ int complete_code; /* indicate pending complete interrupt */
+ int trigger_slot_word; /* only used for qedma */
+};
+
+void qedma3_start(u32 base, struct edma3_channel_config *cfg);
+void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
+void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
+int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
+void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
+void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
+
+void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
+ enum edma3_fifo_width width);
+void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_dest_addr(u32 base, int slot, u32 dst);
+
+void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
+ enum edma3_fifo_width width);
+void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_src_addr(u32 base, int slot, u32 src);
+
+void edma3_set_transfer_params(u32 base, int slot, int acnt,
+ int bcnt, int ccnt, u16 bcnt_rld,
+ enum edma3_sync_dimension sync_mode);
+
+#endif
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index b16694c72f..f97f3dd149 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -45,4 +45,19 @@ void reset_timer_masked (void);
ulong get_timer_masked (void);
void udelay_masked (unsigned long usec);
+/* calls to c from vectors.S */
+void bad_mode(void);
+void do_undefined_instruction(struct pt_regs *pt_regs);
+void do_software_interrupt(struct pt_regs *pt_regs);
+void do_prefetch_abort(struct pt_regs *pt_regs);
+void do_data_abort(struct pt_regs *pt_regs);
+void do_not_used(struct pt_regs *pt_regs);
+#ifdef CONFIG_ARM64
+void do_fiq(struct pt_regs *pt_regs, unsigned int esr);
+void do_irq(struct pt_regs *pt_regs, unsigned int esr);
+#else
+void do_fiq(struct pt_regs *pt_regs);
+void do_irq(struct pt_regs *pt_regswq);
+#endif
+
#endif /* _U_BOOT_ARM_H_ */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 76adaf3aa4..f6062557e6 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -34,6 +34,7 @@
#include <onenand_uboot.h>
#include <mmc.h>
#include <scsi.h>
+#include <status_led.h>
#include <libfdt.h>
#include <fdtdec.h>
#include <post.h>
@@ -63,25 +64,15 @@ extern void dataflash_print_info(void);
************************************************************************
* May be supplied by boards if desired
*/
-inline void __coloured_LED_init(void) {}
-void coloured_LED_init(void)
- __attribute__((weak, alias("__coloured_LED_init")));
-inline void __red_led_on(void) {}
-void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
-inline void __red_led_off(void) {}
-void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
-inline void __green_led_on(void) {}
-void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
-inline void __green_led_off(void) {}
-void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
-inline void __yellow_led_on(void) {}
-void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
-inline void __yellow_led_off(void) {}
-void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
-inline void __blue_led_on(void) {}
-void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
-inline void __blue_led_off(void) {}
-void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
+__weak void coloured_LED_init(void) {}
+__weak void red_led_on(void) {}
+__weak void red_led_off(void) {}
+__weak void green_led_on(void) {}
+__weak void green_led_off(void) {}
+__weak void yellow_led_on(void) {}
+__weak void yellow_led_off(void) {}
+__weak void blue_led_on(void) {}
+__weak void blue_led_off(void) {}
/*
************************************************************************
@@ -198,27 +189,21 @@ static int arm_pci_init(void)
*/
typedef int (init_fnc_t) (void);
-void __dram_init_banksize(void)
+__weak void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
}
-void dram_init_banksize(void)
- __attribute__((weak, alias("__dram_init_banksize")));
-int __arch_cpu_init(void)
+__weak int arch_cpu_init(void)
{
return 0;
}
-int arch_cpu_init(void)
- __attribute__((weak, alias("__arch_cpu_init")));
-int __power_init_board(void)
+__weak int power_init_board(void)
{
return 0;
}
-int power_init_board(void)
- __attribute__((weak, alias("__power_init_board")));
/* Record the board_init_f() bootstage (after arch_cpu_init()) */
static int mark_bootstage(void)
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 39fe7a17fc..cdb1975105 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -15,6 +15,7 @@
#include <common.h>
#include <command.h>
#include <image.h>
+#include <vxworks.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
#include <libfdt.h>
@@ -22,6 +23,8 @@
#include <asm/bootm.h>
#include <asm/secure.h>
#include <linux/compiler.h>
+#include <bootm.h>
+#include <vxworks.h>
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
#include <asm/armv7.h>
@@ -299,7 +302,8 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
* DIFFERENCE: Instead of calling prep and go at the end
* they are called if subcommand is equal 0.
*/
-int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+int do_bootm_linux(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
{
/* No need for those on ARM */
if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index f6b7c03578..4dacfd941f 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -21,12 +21,15 @@
#include <common.h>
#include <asm/proc-armv/ptrace.h>
+#include <asm/u-boot-arm.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USE_IRQ
int interrupt_init (void)
{
+ unsigned long cpsr;
+
/*
* setup up stacks if necessary
*/
@@ -34,6 +37,31 @@ int interrupt_init (void)
IRQ_STACK_START_IN = gd->irq_sp + 8;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ : "=r" (cpsr)
+ :
+ : "memory");
+
+ __asm__ __volatile__("msr cpsr_c, %0\n"
+ "mov sp, %1\n"
+ :
+ : "r" (IRQ_MODE | I_BIT | F_BIT | (cpsr & ~FIQ_MODE)),
+ "r" (IRQ_STACK_START)
+ : "memory");
+
+ __asm__ __volatile__("msr cpsr_c, %0\n"
+ "mov sp, %1\n"
+ :
+ : "r" (FIQ_MODE | I_BIT | F_BIT | (cpsr & ~IRQ_MODE)),
+ "r" (FIQ_STACK_START)
+ : "memory");
+
+ __asm__ __volatile__("msr cpsr_c, %0"
+ :
+ : "r" (cpsr)
+ : "memory");
+
return arch_interrupt_init();
}
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 8035251563..b4a258ce5c 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -6,6 +6,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <asm-offsets.h>
+#include <config.h>
#include <linux/linkage.h>
/*
@@ -52,6 +54,34 @@ fixnext:
cmp r2, r3
blo fixloop
+ /*
+ * Relocate the exception vectors
+ */
+#ifdef CONFIG_HAS_VBAR
+ /*
+ * If the ARM processor has the security extensions,
+ * use VBAR to relocate the exception vectors.
+ */
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
+#else
+ /*
+ * Copy the relocated exception vectors to the
+ * correct address
+ * CP15 c1 V bit gives us the location of the vectors:
+ * 0x00000000 or 0xFFFF0000.
+ */
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+ mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
+ ands r2, r2, #(1 << 13)
+ ldreq r1, =0x00000000 /* If V=0 */
+ ldrne r1, =0xFFFF0000 /* If V=1 */
+ ldmia r0!, {r2-r8,r10}
+ stmia r1!, {r2-r8,r10}
+ ldmia r0!, {r2-r8,r10}
+ stmia r1!, {r2-r8,r10}
+#endif
+
relocate_done:
#ifdef __XSCALE__
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 0cb87cee7f..49238ed21e 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -33,7 +33,7 @@
*************************************************************************
*/
- .section ".vectors", "x"
+ .section ".vectors", "ax"
/*
*************************************************************************
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index 2e640afc45..fde54eaa3e 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -955,6 +955,7 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
uint32_t *hibernate_magic = 0;
SSYNC();
+ /* cppcheck-suppress nullPointer */
if (hibernate_magic[0] == 0xDEADBEEF) {
serial_putc('c');
bfin_write_EVT15(hibernate_magic[1]);
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 33bfd9f2f4..6f419f050d 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -9,6 +9,7 @@ choice
config TARGET_MICROBLAZE_GENERIC
bool "Support microblaze-generic"
+ select SUPPORT_SPL
endchoice
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9b72bab56b..4991da2226 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,6 +4,10 @@ menu "MIPS architecture"
config SYS_ARCH
default "mips"
+config SYS_CPU
+ default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
+ default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
+
config USE_PRIVATE_LIBGCC
default y
@@ -12,21 +16,39 @@ choice
config TARGET_QEMU_MIPS
bool "Support qemu-mips"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_CPU_MIPS64_R1
+ select SUPPORTS_CPU_MIPS64_R2
config TARGET_MALTA
bool "Support malta"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
config TARGET_VCT
bool "Support vct"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
config TARGET_DBAU1X00
bool "Support dbau1x00"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
config TARGET_PB1X00
bool "Support pb1x00"
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
-config TARGET_QEMU_MIPS64
- bool "Support qemu-mips64"
endchoice
@@ -36,4 +58,88 @@ source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
+if MIPS
+
+choice
+ prompt "Endianness selection"
+ help
+ Some MIPS boards can be configured for either little or big endian
+ byte order. These modes require different U-Boot images. In general there
+ is one preferred byteorder for a particular system but some systems are
+ just as commonly used in the one or the other endianness.
+
+config SYS_BIG_ENDIAN
+ bool "Big endian"
+ depends on SUPPORTS_BIG_ENDIAN
+
+config SYS_LITTLE_ENDIAN
+ bool "Little endian"
+ depends on SUPPORTS_LITTLE_ENDIAN
+
+endchoice
+
+choice
+ prompt "CPU selection"
+ default CPU_MIPS32_R2
+
+config CPU_MIPS32_R1
+ bool "MIPS32 Release 1"
+ depends on SUPPORTS_CPU_MIPS32_R1
+ select 32BIT
+ help
+ Choose this option to build an U-Boot for release 1 or later of the
+ MIPS32 architecture.
+
+config CPU_MIPS32_R2
+ bool "MIPS32 Release 2"
+ depends on SUPPORTS_CPU_MIPS32_R2
+ select 32BIT
+ help
+ Choose this option to build an U-Boot for release 2 or later of the
+ MIPS32 architecture.
+
+config CPU_MIPS64_R1
+ bool "MIPS64 Release 1"
+ depends on SUPPORTS_CPU_MIPS64_R1
+ select 64BIT
+ help
+ Choose this option to build a kernel for release 1 or later of the
+ MIPS64 architecture.
+
+config CPU_MIPS64_R2
+ bool "MIPS64 Release 2"
+ depends on SUPPORTS_CPU_MIPS64_R2
+ select 64BIT
+ help
+ Choose this option to build a kernel for release 2 or later of the
+ MIPS64 architecture.
+
+endchoice
+
+config SUPPORTS_BIG_ENDIAN
+ bool
+
+config SUPPORTS_LITTLE_ENDIAN
+ bool
+
+config SUPPORTS_CPU_MIPS32_R1
+ bool
+
+config SUPPORTS_CPU_MIPS32_R2
+ bool
+
+config SUPPORTS_CPU_MIPS64_R1
+ bool
+
+config SUPPORTS_CPU_MIPS64_R2
+ bool
+
+config 32BIT
+ bool
+
+config 64BIT
+ bool
+
+endif
+
endmenu
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index a2d07aff1b..4dc88f4d51 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -5,25 +5,41 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := mips_4KC-
+ifdef CONFIG_SYS_BIG_ENDIAN
+32bit-emul := elf32btsmip
+64bit-emul := elf64btsmip
+32bit-bfd := elf32-tradbigmips
+64bit-bfd := elf64-tradbigmips
+PLATFORM_CPPFLAGS += -EB
+PLATFORM_LDFLAGS += -EB
endif
-# Handle special prefix in ELDK 4.0 toolchain
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS := -EL
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+32bit-emul := elf32ltsmip
+64bit-emul := elf64ltsmip
+32bit-bfd := elf32-tradlittlemips
+64bit-bfd := elf64-tradlittlemips
+PLATFORM_CPPFLAGS += -EL
+PLATFORM_LDFLAGS += -EL
endif
-ifdef CONFIG_SYS_LITTLE_ENDIAN
-ENDIANNESS := -EL
+ifdef CONFIG_32BIT
+PLATFORM_CPPFLAGS += -mabi=32
+PLATFORM_LDFLAGS += -m $(32bit-emul)
+OBJCOPYFLAGS += -O $(32bit-bfd)
endif
-ifdef CONFIG_SYS_BIG_ENDIAN
-ENDIANNESS := -EB
+ifdef CONFIG_64BIT
+PLATFORM_CPPFLAGS += -mabi=64
+PLATFORM_LDFLAGS += -m$(64bit-emul)
+OBJCOPYFLAGS += -O $(64bit-bfd)
endif
-# Default to EB if no endianess is configured
-ENDIANNESS ?= -EB
+cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
+cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
+cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
+cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+PLATFORM_CPPFLAGS += $(cpuflags-y)
PLATFORM_CPPFLAGS += -D__MIPS__
@@ -49,10 +65,10 @@ __HAVE_ARCH_GENERIC_BOARD := y
# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
# to RAM. $28 is always used as gp.
#
-PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS)
+PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
PLATFORM_CPPFLAGS += -msoft-float
-PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
+PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections -pie
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got
-OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn
+OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding
diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk
index 332cd62c74..4257c56d59 100644
--- a/arch/mips/cpu/mips32/config.mk
+++ b/arch/mips/cpu/mips32/config.mk
@@ -5,19 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-#
-# Default optimization level for MIPS32
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2
-PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS += -m elf32btsmip
-else
-PLATFORM_LDFLAGS += -m elf32ltsmip
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
-T $(srctree)/examples/standalone/mips.lds
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk
index c55eb7f2ee..96eb82948d 100644
--- a/arch/mips/cpu/mips64/config.mk
+++ b/arch/mips/cpu/mips64/config.mk
@@ -5,19 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-#
-# Default optimization level for MIPS64
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64
-PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS += -m elf64btsmip
-else
-PLATFORM_LDFLAGS += -m elf64ltsmip
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \
-T $(srctree)/examples/standalone/mips64.lds
diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds
index e504ea7544..7d71c11ae4 100644
--- a/arch/mips/cpu/u-boot.lds
+++ b/arch/mips/cpu/u-boot.lds
@@ -61,6 +61,24 @@ SECTIONS
__rel_dyn_end = .;
}
+ .padding : {
+ /*
+ * Workaround for a binutils feature (or bug?).
+ *
+ * The GNU ld from binutils puts the dynamic relocation
+ * entries into the .rel.dyn section. Sometimes it
+ * allocates more dynamic relocation entries than it needs
+ * and the unused slots are set to R_MIPS_NONE entries.
+ *
+ * However the size of the .rel.dyn section in the ELF
+ * section header does not cover the unused entries, so
+ * objcopy removes those during stripping.
+ *
+ * Create a small section here to avoid that.
+ */
+ LONG(0xFFFFFFFF)
+ }
+
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
diff --git a/arch/powerpc/cpu/74xx_7xx/Kconfig b/arch/powerpc/cpu/74xx_7xx/Kconfig
index 3378c91645..b2f1a598e3 100644
--- a/arch/powerpc/cpu/74xx_7xx/Kconfig
+++ b/arch/powerpc/cpu/74xx_7xx/Kconfig
@@ -19,30 +19,14 @@ config TARGET_PPMC7XX
config TARGET_ELPPC
bool "Support ELPPC"
-config TARGET_CPCI750
- bool "Support CPCI750"
-
config TARGET_MPC7448HPC2
bool "Support mpc7448hpc2"
-config TARGET_DB64360
- bool "Support DB64360"
-
-config TARGET_DB64460
- bool "Support DB64460"
-
-config TARGET_P3MX
- bool "Support p3mx"
-
endchoice
-source "board/Marvell/db64360/Kconfig"
-source "board/Marvell/db64460/Kconfig"
source "board/eltec/elppc/Kconfig"
-source "board/esd/cpci750/Kconfig"
source "board/evb64260/Kconfig"
source "board/freescale/mpc7448hpc2/Kconfig"
source "board/ppmc7xx/Kconfig"
-source "board/prodrive/p3mx/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S
index b0e102c668..83937812bd 100644
--- a/arch/powerpc/cpu/74xx_7xx/start.S
+++ b/arch/powerpc/cpu/74xx_7xx/start.S
@@ -28,13 +28,6 @@
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#if !defined(CONFIG_DB64360) && \
- !defined(CONFIG_DB64460) && \
- !defined(CONFIG_CPCI750) && \
- !defined(CONFIG_P3Mx)
-#include <galileo/gt64260R.h>
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
@@ -712,11 +705,7 @@ in_ram:
bne 5b
6:
mr r3, r10 /* Destination Address */
-#if defined(CONFIG_DB64360) || \
- defined(CONFIG_DB64460) || \
- defined(CONFIG_CPCI750) || \
- defined(CONFIG_PPMC7XX) || \
- defined(CONFIG_P3Mx)
+#if defined(CONFIG_PPMC7XX)
mr r4, r9 /* Use RAM copy of the global data */
#endif
bl after_reloc
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index 8a477e7e0c..c1fb92af4b 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -9,6 +9,7 @@ choice
config TARGET_A3M071
bool "Support a3m071"
+ select SUPPORT_SPL
config TARGET_A4M072
bool "Support a4m072"
@@ -55,9 +56,6 @@ config TARGET_TOTAL5200
config TARGET_V38B
bool "Support v38b"
-config TARGET_TOP5200
- bool "Support TOP5200"
-
config TARGET_CPCI5200
bool "Support cpci5200"
@@ -119,7 +117,6 @@ source "board/a4m072/Kconfig"
source "board/bc3450/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
-source "board/emk/top5200/Kconfig"
source "board/esd/cpci5200/Kconfig"
source "board/esd/mecp5200/Kconfig"
source "board/esd/pf5200/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 41e4e5f1ec..2541400e72 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -28,9 +28,6 @@ config TARGET_EP82XXM
config TARGET_GW8260
bool "Support gw8260"
-config TARGET_HYMOD
- bool "Support hymod"
-
config TARGET_IPHASE4539
bool "Support IPHASE4539"
@@ -55,18 +52,9 @@ config TARGET_MPC8266ADS
config TARGET_VOVPN_GW
bool "Support VoVPN-GW"
-config TARGET_IDS8247
- bool "Support IDS8247"
-
config TARGET_KM82XX
bool "Support km82xx"
-config TARGET_TQM8260
- bool "Support TQM8260"
-
-config TARGET_TQM8272
- bool "Support TQM8272"
-
endchoice
source "board/atc/Kconfig"
@@ -78,8 +66,6 @@ source "board/ep82xxm/Kconfig"
source "board/freescale/mpc8266ads/Kconfig"
source "board/funkwerk/vovpn-gw/Kconfig"
source "board/gw8260/Kconfig"
-source "board/hymod/Kconfig"
-source "board/ids/ids8247/Kconfig"
source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
source "board/muas3001/Kconfig"
@@ -87,7 +73,5 @@ source "board/pm826/Kconfig"
source "board/pm828/Kconfig"
source "board/ppmc8260/Kconfig"
source "board/sacsng/Kconfig"
-source "board/tqc/tqm8260/Kconfig"
-source "board/tqc/tqm8272/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index d93a99109f..f9f15b59e5 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -645,32 +645,7 @@ eth_loopback_test (void)
/* 28.9 - (1-2): ioports have been set up already */
-#if defined(CONFIG_HYMOD)
- /*
- * Attention: this is board-specific
- * 0, FCC1
- * 1, FCC2
- * 2, FCC3
- */
-# define FCC_START_LOOP 0
-# define FCC_END_LOOP 2
-
- /*
- * Attention: this is board-specific
- * - FCC1 Rx-CLK is CLK10
- * - FCC1 Tx-CLK is CLK11
- * - FCC2 Rx-CLK is CLK13
- * - FCC2 Tx-CLK is CLK14
- * - FCC3 Rx-CLK is CLK15
- * - FCC3 Tx-CLK is CLK16
- */
-
- /* 28.9 - (3): connect FCC's tx and rx clocks */
- immr->im_cpmux.cmx_uar = 0;
- immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
- CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
- CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
-#elif defined(CONFIG_SACSng)
+#if defined(CONFIG_SACSng)
/*
* Attention: this is board-specific
* 1, FCC2
diff --git a/arch/powerpc/cpu/mpc8260/interrupts.c b/arch/powerpc/cpu/mpc8260/interrupts.c
index 30125a7a73..41d2c04c85 100644
--- a/arch/powerpc/cpu/mpc8260/interrupts.c
+++ b/arch/powerpc/cpu/mpc8260/interrupts.c
@@ -142,15 +142,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
immr->im_intctl.ic_sipnrh = 0xffffffff;
immr->im_intctl.ic_sipnrl = 0xffffffff;
-#ifdef CONFIG_HYMOD
- /*
- * ensure all external interrupt sources default to trigger on
- * high-to-low transition (i.e. edge triggered active low)
- */
- immr->im_intctl.ic_siexr = -1;
-#endif
-
- return (0);
+ return 0;
}
/****************************************************************************/
diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c
index 0a47fdc1d3..f7bb05d204 100644
--- a/arch/powerpc/cpu/mpc8260/pci.c
+++ b/arch/powerpc/cpu/mpc8260/pci.c
@@ -262,8 +262,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
| SIUMCR_CS10PC00
| SIUMCR_BCTLC00
| SIUMCR_MMR11;
-#elif defined(CONFIG_TQM8272)
-/* nothing to do for this Board here */
#else
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S
index d7eaf13e0b..5f1e174ec8 100644
--- a/arch/powerpc/cpu/mpc8260/start.S
+++ b/arch/powerpc/cpu/mpc8260/start.S
@@ -48,9 +48,6 @@
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
-#if defined(CONFIG_HYMOD)
- GOT_ENTRY(environment)
-#endif
END_GOT
/*
@@ -878,18 +875,7 @@ clear_bss:
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
-#if defined(CONFIG_HYMOD)
- /*
- * For HYMOD - the environment is the very last item in flash.
- * The real .bss stops just before environment starts, so only
- * clear up to that point.
- *
- * taken from mods for FADS board
- */
- lwz r4,GOT(environment)
-#else
lwz r4,GOT(__bss_end)
-#endif
cmplw 0, r3, r4
beq 6f
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 42e0e29668..2a1abe03a9 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -24,6 +24,7 @@ config TARGET_MPC8308RDB
config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
+ select SUPPORT_SPL
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 36724e5aa5..af75c63eb3 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -958,18 +958,7 @@ clear_bss:
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
-#if defined(CONFIG_HYMOD)
- /*
- * For HYMOD - the environment is the very last item in flash.
- * The real .bss stops just before environment starts, so only
- * clear up to that point.
- *
- * taken from mods for FADS board
- */
- lwz r4,GOT(environment)
-#else
lwz r4,GOT(__bss_end)
-#endif
cmplw 0, r3, r4
beq 6f
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8c1c01c342..7b42d06952 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -13,20 +13,22 @@ config TARGET_SBC8548
config TARGET_SOCRATES
bool "Support socrates"
-config TARGET_HWW1U1A
- bool "Support HWW1U1A"
-
config TARGET_B4860QDS
bool "Support B4860QDS"
+ select SUPPORT_SPL
config TARGET_BSC9131RDB
bool "Support BSC9131RDB"
+ select SUPPORT_SPL
config TARGET_BSC9132QDS
bool "Support BSC9132QDS"
+ select SUPPORT_SPL
config TARGET_C29XPCIE
bool "Support C29XPCIE"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P3041DS
bool "Support P3041DS"
@@ -72,18 +74,26 @@ config TARGET_MPC8572DS
config TARGET_P1010RDB
bool "Support P1010RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P1022DS
bool "Support P1022DS"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P1023RDB
bool "Support P1023RDB"
config TARGET_P1_P2_RDB
bool "Support P1_P2_RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P1_P2_RDB_PC
bool "Support p1_p2_rdb_pc"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P1_TWR
bool "Support p1_twr"
@@ -105,18 +115,22 @@ config TARGET_T1040QDS
config TARGET_T104XRDB
bool "Support T104xRDB"
+ select SUPPORT_SPL
config TARGET_T208XQDS
bool "Support T208xQDS"
+ select SUPPORT_SPL
config TARGET_T208XRDB
bool "Support T208xRDB"
+ select SUPPORT_SPL
config TARGET_T4240EMU
bool "Support T4240EMU"
config TARGET_T4240QDS
bool "Support T4240QDS"
+ select SUPPORT_SPL
config TARGET_T4240RDB
bool "Support T4240RDB"
@@ -144,7 +158,6 @@ config TARGET_XPEDITE550X
endchoice
-source "board/exmeritus/hww1u1a/Kconfig"
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 47b712d56b..072387a87e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -161,9 +161,12 @@ void cpu_init_early_f(void *fdt)
setup_ifc_sram = (void *)SRAM_BASE_ADDR;
dst = (u32 *) SRAM_BASE_ADDR;
src = (u32 *) setup_ifc;
- for (i = 0; i < 1024; i++)
+ for (i = 0; i < 1024; i++) {
+ /* cppcheck-suppress nullPointer */
*dst++ = *src++;
+ }
+ /* cppcheck-suppress nullPointer */
setup_ifc_sram();
/* CLEANUP */
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index f1dca90eba..e447748e12 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -16,9 +16,6 @@ config TARGET_ESTEEM192E
config TARGET_HERMES
bool "Support hermes"
-config TARGET_ICU862
- bool "Support ICU862"
-
config TARGET_IP860
bool "Support IP860"
@@ -43,12 +40,6 @@ config TARGET_RRVISION
config TARGET_SPD823TS
bool "Support SPD823TS"
-config TARGET_MHPC
- bool "Support MHPC"
-
-config TARGET_TOP860
- bool "Support TOP860"
-
config TARGET_KUP4K
bool "Support KUP4K"
@@ -120,11 +111,8 @@ endchoice
source "board/LEOX/elpt860/Kconfig"
source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
-source "board/eltec/mhpc/Kconfig"
-source "board/emk/top860/Kconfig"
source "board/esteem192e/Kconfig"
source "board/hermes/Kconfig"
-source "board/icu862/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
source "board/kup/kup4k/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 90c7e61d83..60c401e311 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -126,12 +126,10 @@ void cpu_init_f (volatile immap_t * immr)
*/
#if defined(CONFIG_HERMES) || \
- defined(CONFIG_ICU862) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
- defined(CONFIG_MHPC) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
defined(CONFIG_SPD823TS)
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index d12b3df4a1..22b8ec752b 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -205,11 +205,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
j = 0;
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
-#if defined(CONFIG_ICU862)
- udelay(10);
-#else
udelay(1);
-#endif
j++;
}
if (j>=TOUT_LOOP) {
@@ -424,7 +420,7 @@ static void fec_pin_init(int fecidx)
#endif /* !CONFIG_RMII */
-#elif !defined(CONFIG_ICU862)
+#else
/*
* Configure all of port D for MII.
*/
@@ -437,42 +433,8 @@ static void fec_pin_init(int fecidx)
immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
else
immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
-#else
- /*
- * Configure port A for MII.
- */
-
-#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
-
- /*
- * On the ICU862 board the MII-MDC pin is routed to PD8 pin
- * * of CPU, so for this board we need to configure Utopia and
- * * enable PD8 to MII-MDC function
- */
- immr->im_ioport.iop_pdpar |= 0x4080;
#endif
- /*
- * Has Utopia been configured?
- */
- if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
- /*
- * YES - Use MUXED mode for UTOPIA bus.
- * This frees Port A for use by MII (see 862UM table 41-6).
- */
- immr->im_ioport.utmode &= ~0x80;
- } else {
- /*
- * NO - set SPLIT mode for UTOPIA bus.
- *
- * This doesn't really effect UTOPIA (which isn't
- * enabled anyway) but just tells the 862
- * to use port A for MII (see 862UM table 41-6).
- */
- immr->im_ioport.utmode |= 0x80;
- }
-#endif /* !defined(CONFIG_ICU862) */
-
#endif /* CONFIG_ETHER_ON_FEC1 */
} else if (fecidx == 1) {
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 56abe8dc56..8f8860163c 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -24,6 +24,7 @@ config TARGET_KORAT
config TARGET_LWMON5
bool "Support lwmon5"
+ select SUPPORT_SPL
config TARGET_PCS440EP
bool "Support pcs440ep"
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 22561231cb..e5a0e21e36 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -451,6 +451,9 @@ cpu_init_f (void)
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset((void *)gd, 0, sizeof(gd_t));
}
/*
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index 6086a73ba9..bed80aa933 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -59,6 +59,7 @@ typedef struct sysconf512x {
u8 res2[0x28];
law512x_t ddrlaw; /* DDR Local Access Window */
u8 res3[0x18];
+ u32 mbxbar; /* MBX Base Address */
u32 srambar; /* SRAM Base Address */
u32 nfcbar; /* NFC Base Address */
u8 res4[0x34];
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index e1b566fa56..a61e998df6 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -77,9 +77,6 @@ typedef struct bd_info {
unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
#endif
-#if defined(CONFIG_HYMOD)
- hymod_conf_t bi_hymod_conf; /* hymod configuration information */
-#endif
#ifdef CONFIG_HAS_ETH1
unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index b3d70515dc..53a99ae71b 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <os.h>
+#include <cli.h>
#include <asm/getopt.h>
#include <asm/io.h>
#include <asm/sections.h>
@@ -76,6 +77,8 @@ int sandbox_main_loop_init(void)
/* Execute command if required */
if (state->cmd) {
+ cli_init();
+
run_command_list(state->cmd, -1, 0);
if (!state->interactive)
os_exit(state->exit_type);
diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h
index 6d3eb1f3de..42c09e2fff 100644
--- a/arch/sandbox/include/asm/types.h
+++ b/arch/sandbox/include/asm/types.h
@@ -42,8 +42,13 @@ typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
+#if !defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__)
typedef signed long long s64;
typedef unsigned long long u64;
+#else
+typedef __INT64_TYPE__ s64;
+typedef __UINT64_TYPE__ u64;
+#endif
#define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG
diff --git a/arch/sh/lib/zimageboot.c b/arch/sh/lib/zimageboot.c
index 86d39983c8..3fea5f5b53 100644
--- a/arch/sh/lib/zimageboot.c
+++ b/arch/sh/lib/zimageboot.c
@@ -45,6 +45,7 @@ int do_sh_zimageboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
bootargs = getenv("bootargs");
/* Clear zero page */
+ /* cppcheck-suppress nullPointer */
memset(param, 0, 0x1000);
/* Set commandline */
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 733334f931..2df09b2e50 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -1,29 +1,56 @@
menu "SPARC architecture"
depends on SPARC
-config SYS_ARCH
- default "sparc"
+config LEON
+ bool
+
+config LEON2
+ bool
+ select LEON
+
+config LEON3
+ bool
+ select LEON
choice
- prompt "Target select"
+ prompt "Board select"
config TARGET_GRSIM_LEON2
- bool "Support grsim_leon2"
+ bool "GRSIM simulating a LEON2 board"
+ select LEON2
config TARGET_GR_CPCI_AX2000
- bool "Support gr_cpci_ax2000"
+ bool "Gaisler GR-CPCI-AX2000 board"
+ select LEON3
config TARGET_GR_EP2S60
- bool "Support gr_ep2s60"
+ bool "Gaisler Template design for Altera NIOS board with Stratix EP2S60"
+ select LEON3
+ help
+ Gaisler Research AB's Template design (GPL Open Source SPARC/LEON3
+ 96MHz) for Altera NIOS Development board Stratix II edition,
+ with the FPGA device EP2S60.
config TARGET_GR_XC3S_1500
- bool "Support gr_xc3s_1500"
+ bool "Gaisler GR-XC3S-1500 spartan board"
+ select LEON3
config TARGET_GRSIM
- bool "Support grsim"
+ bool "GRSIM simulating a LEON3 GR-XC3S-1500 board"
+ select LEON3
endchoice
+config SYS_ARCH
+ default "sparc"
+
+config SYS_CPU
+ default "leon2" if LEON2
+ default "leon3" if LEON3
+
+config SYS_VENDOR
+ default "gaisler"
+
source "board/gaisler/gr_cpci_ax2000/Kconfig"
source "board/gaisler/gr_ep2s60/Kconfig"
source "board/gaisler/gr_xc3s_1500/Kconfig"
diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk
index 196d28af84..d615f294fe 100644
--- a/arch/sparc/config.mk
+++ b/arch/sparc/config.mk
@@ -15,3 +15,5 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \
-T $(srctree)/examples/standalone/sparc.lds
PLATFORM_CPPFLAGS += -D__sparc__
+
+PLATFORM_RELFLAGS += -fPIC
diff --git a/arch/sparc/cpu/leon2/config.mk b/arch/sparc/cpu/leon2/config.mk
deleted file mode 100644
index c44b0930ec..0000000000
--- a/arch/sparc/cpu/leon2/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fPIC
-
-PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON2
diff --git a/arch/sparc/cpu/leon3/config.mk b/arch/sparc/cpu/leon3/config.mk
deleted file mode 100644
index ca6c9b13ec..0000000000
--- a/arch/sparc/cpu/leon3/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fPIC
-
-PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON3
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index e7bb3e33d5..9d38ef73a7 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -10,4 +10,4 @@
extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y += interrupts.o cpu.o
+obj-y += interrupts.o cpu.o call64.o
diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/call64.S
new file mode 100644
index 0000000000..74dd5a89dc
--- /dev/null
+++ b/arch/x86/cpu/call64.S
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ * Copyright (C) 1991, 1992, 1993 Linus Torvalds
+ *
+ * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/global_data.h>
+#include <asm/msr-index.h>
+#include <asm/processor-flags.h>
+
+.code32
+.globl cpu_call64
+cpu_call64:
+ /*
+ * cpu_call64(ulong pgtable, ulong setup_base, ulong target)
+ *
+ * eax - pgtable
+ * edx - setup_base
+ * ecx - target
+ */
+ cli
+ push %ecx /* arg2 = target */
+ push %edx /* arg1 = setup_base */
+ mov %eax, %ebx
+
+ /* Load new GDT with the 64bit segments using 32bit descriptor */
+ leal gdt, %eax
+ movl %eax, gdt+2
+ lgdt gdt
+
+ /* Enable PAE mode */
+ movl $(X86_CR4_PAE), %eax
+ movl %eax, %cr4
+
+ /* Enable the boot page tables */
+ leal (%ebx), %eax
+ movl %eax, %cr3
+
+ /* Enable Long mode in EFER (Extended Feature Enable Register) */
+ movl $MSR_EFER, %ecx
+ rdmsr
+ btsl $_EFER_LME, %eax
+ wrmsr
+
+ /* After gdt is loaded */
+ xorl %eax, %eax
+ lldt %ax
+ movl $0x20, %eax
+ ltr %ax
+
+ /*
+ * Setup for the jump to 64bit mode
+ *
+ * When the jump is performed we will be in long mode but
+ * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
+ * (and in turn EFER.LMA = 1). To jump into 64bit mode we use
+ * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
+ * We place all of the values on our mini stack so lret can
+ * used to perform that far jump. See the gdt below.
+ */
+ pop %esi /* setup_base */
+
+ pushl $0x10
+ leal lret_target, %eax
+ pushl %eax
+
+ /* Enter paged protected Mode, activating Long Mode */
+ movl $(X86_CR0_PG | X86_CR0_PE), %eax
+ movl %eax, %cr0
+
+ /* Jump from 32bit compatibility mode into 64bit mode. */
+ lret
+
+code64:
+lret_target:
+ pop %eax /* target */
+ mov %eax, %eax /* Clear bits 63:32 */
+ jmp *%eax /* Jump to the 64-bit target */
+
+ .data
+gdt:
+ .word gdt_end - gdt
+ .long gdt
+ .word 0
+ .quad 0x0000000000000000 /* NULL descriptor */
+ .quad 0x00af9a000000ffff /* __KERNEL_CS */
+ .quad 0x00cf92000000ffff /* __KERNEL_DS */
+ .quad 0x0080890000000000 /* TS descriptor */
+ .quad 0x0000000000000000 /* TS continued */
+gdt_end:
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 623e3af61f..2e252532d6 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -18,7 +18,10 @@
#include <common.h>
#include <command.h>
+#include <errno.h>
+#include <malloc.h>
#include <asm/control_regs.h>
+#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/interrupt.h>
@@ -240,3 +243,144 @@ int icache_status(void)
{
return 1;
}
+
+void cpu_enable_paging_pae(ulong cr3)
+{
+ __asm__ __volatile__(
+ /* Load the page table address */
+ "movl %0, %%cr3\n"
+ /* Enable pae */
+ "movl %%cr4, %%eax\n"
+ "orl $0x00000020, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ /* Enable paging */
+ "movl %%cr0, %%eax\n"
+ "orl $0x80000000, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ :
+ : "r" (cr3)
+ : "eax");
+}
+
+void cpu_disable_paging_pae(void)
+{
+ /* Turn off paging */
+ __asm__ __volatile__ (
+ /* Disable paging */
+ "movl %%cr0, %%eax\n"
+ "andl $0x7fffffff, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ /* Disable pae */
+ "movl %%cr4, %%eax\n"
+ "andl $0xffffffdf, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ :
+ :
+ : "eax");
+}
+
+static bool has_cpuid(void)
+{
+ unsigned long flag;
+
+ asm volatile("pushf\n" \
+ "pop %%eax\n"
+ "mov %%eax, %%ecx\n" /* ecx = flags */
+ "xor %1, %%eax\n"
+ "push %%eax\n"
+ "popf\n" /* flags ^= $2 */
+ "pushf\n"
+ "pop %%eax\n" /* eax = flags */
+ "push %%ecx\n"
+ "popf\n" /* flags = ecx */
+ "xor %%ecx, %%eax\n"
+ "mov %%eax, %0"
+ : "=r" (flag)
+ : "i" (1 << 21)
+ : "eax", "ecx", "memory");
+
+ return flag != 0;
+}
+
+static bool can_detect_long_mode(void)
+{
+ unsigned long flag;
+
+ asm volatile("mov $0x80000000, %%eax\n"
+ "cpuid\n"
+ "mov %%eax, %0"
+ : "=r" (flag)
+ :
+ : "eax", "ebx", "ecx", "edx", "memory");
+
+ return flag > 0x80000000UL;
+}
+
+static bool has_long_mode(void)
+{
+ unsigned long flag;
+
+ asm volatile("mov $0x80000001, %%eax\n"
+ "cpuid\n"
+ "mov %%edx, %0"
+ : "=r" (flag)
+ :
+ : "eax", "ebx", "ecx", "edx", "memory");
+
+ return flag & (1 << 29) ? true : false;
+}
+
+int cpu_has_64bit(void)
+{
+ return has_cpuid() && can_detect_long_mode() &&
+ has_long_mode();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86");
+
+ return 0;
+}
+
+#define PAGETABLE_SIZE (6 * 4096)
+
+/**
+ * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
+ *
+ * @pgtable: Pointer to a 24iKB block of memory
+ */
+static void build_pagetable(uint32_t *pgtable)
+{
+ uint i;
+
+ memset(pgtable, '\0', PAGETABLE_SIZE);
+
+ /* Level 4 needs a single entry */
+ pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+
+ /* Level 3 has one 64-bit entry for each GiB of memory */
+ for (i = 0; i < 4; i++) {
+ pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
+ 0x1000 * i + 7;
+ }
+
+ /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
+ for (i = 0; i < 2048; i++)
+ pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+}
+
+int cpu_jump_to_64bit(ulong setup_base, ulong target)
+{
+ uint32_t *pgtable;
+
+ pgtable = memalign(4096, PAGETABLE_SIZE);
+ if (!pgtable)
+ return -ENOMEM;
+
+ build_pagetable(pgtable);
+ cpu_call64((ulong)pgtable, setup_base, target);
+ free(pgtable);
+
+ return -EFAULT;
+}
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 329bb3ab35..338bab19e4 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -85,12 +85,25 @@ car_init_ret:
/* Align global data to 16-byte boundary */
andl $0xfffffff0, %esp
+ /* Zero the global data since it won't happen later */
+ xorl %eax, %eax
+ movl $GENERATED_GBL_DATA_SIZE, %ecx
+ movl %esp, %edi
+ rep stosb
+
/* Setup first parameter to setup_gdt */
movl %esp, %eax
/* Reserve space for global descriptor table */
subl $X86_GDT_SIZE, %esp
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+ subl $CONFIG_SYS_MALLOC_F_LEN, %esp
+ movl %eax, %edx
+ addl $GD_MALLOC_BASE, %edx
+ movl %esp, (%edx)
+#endif
+
/* Align temporary global descriptor table to 16-byte boundary */
andl $0xfffffff0, %esp
diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi
index 4862a59704..c8dc4cec3c 100644
--- a/arch/x86/dts/coreboot.dtsi
+++ b/arch/x86/dts/coreboot.dtsi
@@ -1,13 +1,14 @@
/include/ "skeleton.dtsi"
/ {
- aliases {
- console = "/serial";
+ chosen {
+ stdout-path = "/serial";
};
serial {
- compatible = "ns16550";
- reg-shift = <1>;
+ compatible = "coreboot-uart";
+ reg = <0x3f8 0x10>;
+ reg-shift = <0>;
io-mapped = <1>;
multiplier = <1>;
baudrate = <115200>;
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 67ce52a102..f2fcb3927c 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -12,7 +12,23 @@
silent_console = <0>;
};
- gpio: gpio {};
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ reg = <0 0x10>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ reg = <0x30 0x10>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ reg = <0x40 0x10>;
+ bank-name = "C";
+ };
serial {
reg = <0x3f8 8>;
diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h
new file mode 100644
index 0000000000..3ec1816833
--- /dev/null
+++ b/arch/x86/include/asm/arch-coreboot/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2014, Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+struct ich6_bank_platdata {
+ uint32_t base_addr;
+ const char *bank_name;
+};
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/bootm.h b/arch/x86/include/asm/bootm.h
index 033ab79516..f6a64ce2c9 100644
--- a/arch/x86/include/asm/bootm.h
+++ b/arch/x86/include/asm/bootm.h
@@ -9,4 +9,20 @@
void bootm_announce_and_cleanup(void);
+/**
+ * boot_linux_kernel() - boot a linux kernel
+ *
+ * This boots a kernel image, either 32-bit or 64-bit. It will also work with
+ * a self-extracting kernel, if you set @image_64bit to false.
+ *
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @load_address: Pointer to the start of the kernel image
+ * @image_64bit: true if the image is a raw 64-bit kernel, false if it
+ * is raw 32-bit or any type of self-extracting kernel
+ * such as a bzImage.
+ * @return -ve error code. This function does not return if the kernel was
+ * booted successfully.
+ */
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit);
+
#endif
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
new file mode 100644
index 0000000000..6c6774af76
--- /dev/null
+++ b/arch/x86/include/asm/cpu.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __X86_CPU_H
+#define __X86_CPU_H
+
+ /**
+ * cpu_enable_paging_pae() - Enable PAE-paging
+ *
+ * @pdpt: Value to set in cr3 (PDPT or PML4T)
+ */
+void cpu_enable_paging_pae(ulong cr3);
+
+/**
+ * cpu_disable_paging_pae() - Disable paging and PAE
+ */
+void cpu_disable_paging_pae(void);
+
+/**
+ * cpu_has_64bit() - Check if the CPU has 64-bit support
+ *
+ * @return 1 if this CPU supports long mode (64-bit), 0 if not
+ */
+int cpu_has_64bit(void);
+
+/**
+ * cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * This function is used internally - see cpu_jump_to_64bit() for a more
+ * useful function.
+ *
+ * @pgtable: Address of 24KB area containing the page table
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @target: Pointer to the start of the kernel image
+ */
+void cpu_call64(ulong pgtable, ulong setup_base, ulong target);
+
+/**
+ * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @target: Pointer to the start of the kernel image
+ */
+int cpu_jump_to_64bit(ulong setup_base, ulong target);
+
+#endif
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index fe09f31515..8bda414dbd 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -6,6 +6,7 @@
#ifndef _X86_GPIO_H_
#define _X86_GPIO_H_
+#include <asm/arch/gpio.h>
#include <asm-generic/gpio.h>
#endif /* _X86_GPIO_H_ */
diff --git a/arch/x86/include/asm/ibmpc.h b/arch/x86/include/asm/ibmpc.h
index 0f9665f549..e6d183b479 100644
--- a/arch/x86/include/asm/ibmpc.h
+++ b/arch/x86/include/asm/ibmpc.h
@@ -18,14 +18,4 @@
#define SYSCTLA 0x92
#define SLAVE_PIC 0xa0
-#if 1
-#define UART0_BASE 0x3f8
-#define UART1_BASE 0x2f8
-#else
-/* FixMe: uarts swapped */
-#define UART0_BASE 0x2f8
-#define UART1_BASE 0x3f8
-#endif
-
-
#endif
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 0a36e178f5..6027d593ff 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -44,12 +44,16 @@
#define MSR_IA32_PERFCTR0 0x000000c1
#define MSR_IA32_PERFCTR1 0x000000c2
#define MSR_FSB_FREQ 0x000000cd
+#define MSR_NHM_PLATFORM_INFO 0x000000ce
#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
#define NHM_C1_AUTO_DEMOTE (1UL << 26)
#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
+#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
+#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
+#define MSR_PLATFORM_INFO 0x000000ce
#define MSR_MTRRcap 0x000000fe
#define MSR_IA32_BBL_CR_CTL 0x00000119
#define MSR_IA32_BBL_CR_CTL3 0x0000011e
@@ -64,10 +68,20 @@
#define MSR_OFFCORE_RSP_0 0x000001a6
#define MSR_OFFCORE_RSP_1 0x000001a7
+#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
+#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
+
+#define MSR_LBR_SELECT 0x000001c8
+#define MSR_LBR_TOS 0x000001c9
+#define MSR_LBR_NHM_FROM 0x00000680
+#define MSR_LBR_NHM_TO 0x000006c0
+#define MSR_LBR_CORE_FROM 0x00000040
+#define MSR_LBR_CORE_TO 0x00000060
#define MSR_IA32_PEBS_ENABLE 0x000003f1
#define MSR_IA32_DS_AREA 0x00000600
#define MSR_IA32_PERF_CAPABILITIES 0x00000345
+#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
#define MSR_MTRRfix64K_00000 0x00000250
#define MSR_MTRRfix16K_80000 0x00000258
@@ -91,7 +105,8 @@
#define MSR_IA32_LASTINTTOIP 0x000001de
/* DEBUGCTLMSR bits (others vary by model): */
-#define DEBUGCTLMSR_LBR (1UL << 0)
+#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
+/* single-step on branches */
#define DEBUGCTLMSR_BTF (1UL << 1)
#define DEBUGCTLMSR_TR (1UL << 6)
#define DEBUGCTLMSR_BTS (1UL << 7)
@@ -100,11 +115,50 @@
#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
+#define MSR_IA32_POWER_CTL 0x000001fc
+
#define MSR_IA32_MC0_CTL 0x00000400
#define MSR_IA32_MC0_STATUS 0x00000401
#define MSR_IA32_MC0_ADDR 0x00000402
#define MSR_IA32_MC0_MISC 0x00000403
+/* C-state Residency Counters */
+#define MSR_PKG_C3_RESIDENCY 0x000003f8
+#define MSR_PKG_C6_RESIDENCY 0x000003f9
+#define MSR_PKG_C7_RESIDENCY 0x000003fa
+#define MSR_CORE_C3_RESIDENCY 0x000003fc
+#define MSR_CORE_C6_RESIDENCY 0x000003fd
+#define MSR_CORE_C7_RESIDENCY 0x000003fe
+#define MSR_PKG_C2_RESIDENCY 0x0000060d
+#define MSR_PKG_C8_RESIDENCY 0x00000630
+#define MSR_PKG_C9_RESIDENCY 0x00000631
+#define MSR_PKG_C10_RESIDENCY 0x00000632
+
+/* Run Time Average Power Limiting (RAPL) Interface */
+
+#define MSR_RAPL_POWER_UNIT 0x00000606
+
+#define MSR_PKG_POWER_LIMIT 0x00000610
+#define MSR_PKG_ENERGY_STATUS 0x00000611
+#define MSR_PKG_PERF_STATUS 0x00000613
+#define MSR_PKG_POWER_INFO 0x00000614
+
+#define MSR_DRAM_POWER_LIMIT 0x00000618
+#define MSR_DRAM_ENERGY_STATUS 0x00000619
+#define MSR_DRAM_PERF_STATUS 0x0000061b
+#define MSR_DRAM_POWER_INFO 0x0000061c
+
+#define MSR_PP0_POWER_LIMIT 0x00000638
+#define MSR_PP0_ENERGY_STATUS 0x00000639
+#define MSR_PP0_POLICY 0x0000063a
+#define MSR_PP0_PERF_STATUS 0x0000063b
+
+#define MSR_PP1_POWER_LIMIT 0x00000640
+#define MSR_PP1_ENERGY_STATUS 0x00000641
+#define MSR_PP1_POLICY 0x00000642
+
+#define MSR_CORE_C1_RES 0x00000660
+
#define MSR_AMD64_MC0_MASK 0xc0010044
#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
@@ -123,18 +177,31 @@
#define MSR_P6_EVNTSEL0 0x00000186
#define MSR_P6_EVNTSEL1 0x00000187
+#define MSR_KNC_PERFCTR0 0x00000020
+#define MSR_KNC_PERFCTR1 0x00000021
+#define MSR_KNC_EVNTSEL0 0x00000028
+#define MSR_KNC_EVNTSEL1 0x00000029
+
+/* Alternative perfctr range with full access. */
+#define MSR_IA32_PMC0 0x000004c1
+
/* AMD64 MSRs. Not complete. See the architecture manual for a more
complete list. */
#define MSR_AMD64_PATCH_LEVEL 0x0000008b
+#define MSR_AMD64_TSC_RATIO 0xc0000104
#define MSR_AMD64_NB_CFG 0xc001001f
#define MSR_AMD64_PATCH_LOADER 0xc0010020
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
+#define MSR_AMD64_LS_CFG 0xc0011020
#define MSR_AMD64_DC_CFG 0xc0011022
+#define MSR_AMD64_BU_CFG2 0xc001102a
#define MSR_AMD64_IBSFETCHCTL 0xc0011030
#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
+#define MSR_AMD64_IBSFETCH_REG_COUNT 3
+#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
#define MSR_AMD64_IBSOPCTL 0xc0011033
#define MSR_AMD64_IBSOPRIP 0xc0011034
#define MSR_AMD64_IBSOPDATA 0xc0011035
@@ -142,12 +209,21 @@
#define MSR_AMD64_IBSOPDATA3 0xc0011037
#define MSR_AMD64_IBSDCLINAD 0xc0011038
#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
+#define MSR_AMD64_IBSOP_REG_COUNT 7
+#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
#define MSR_AMD64_IBSCTL 0xc001103a
#define MSR_AMD64_IBSBRTARGET 0xc001103b
+#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
+
+/* Fam 16h MSRs */
+#define MSR_F16H_L2I_PERF_CTL 0xc0010230
+#define MSR_F16H_L2I_PERF_CTR 0xc0010231
/* Fam 15h MSRs */
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTR 0xc0010201
+#define MSR_F15H_NB_PERF_CTL 0xc0010240
+#define MSR_F15H_NB_PERF_CTR 0xc0010241
/* Fam 10h MSRs */
#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
@@ -226,7 +302,9 @@
#define MSR_IA32_PLATFORM_ID 0x00000017
#define MSR_IA32_EBL_CR_POWERON 0x0000002a
#define MSR_EBC_FREQUENCY_ID 0x0000002c
+#define MSR_SMI_COUNT 0x00000034
#define MSR_IA32_FEATURE_CONTROL 0x0000003a
+#define MSR_IA32_TSC_ADJUST 0x0000003b
#define FEATURE_CONTROL_LOCKED (1<<0)
#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
@@ -237,11 +315,16 @@
#define MSR_IA32_APICBASE_ENABLE (1<<11)
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
+#define MSR_IA32_TSCDEADLINE 0x000006e0
+
#define MSR_IA32_UCODE_WRITE 0x00000079
#define MSR_IA32_UCODE_REV 0x0000008b
#define MSR_IA32_PERF_STATUS 0x00000198
#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
+#define MSR_AMD_PERF_STATUS 0xc0010063
+#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
@@ -267,6 +350,9 @@
#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
+#define ENERGY_PERF_BIAS_PERFORMANCE 0
+#define ENERGY_PERF_BIAS_NORMAL 6
+#define ENERGY_PERF_BIAS_POWERSAVE 15
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
@@ -320,6 +406,8 @@
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
+#define MSR_IA32_TSC_DEADLINE 0x000006E0
+
/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX 0x00000180
#define MSR_IA32_MCG_EBX 0x00000181
@@ -446,7 +534,23 @@
#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
-
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
+#define MSR_IA32_VMX_VMFUNC 0x00000491
+
+/* VMX_BASIC bits and bitmasks */
+#define VMX_BASIC_VMCS_SIZE_SHIFT 32
+#define VMX_BASIC_64 0x0001000000000000LLU
+#define VMX_BASIC_MEM_TYPE_SHIFT 50
+#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
+#define VMX_BASIC_MEM_TYPE_WB 6LLU
+#define VMX_BASIC_INOUT 0x0040000000000000LLU
+
+/* MSR_IA32_VMX_MISC bits */
+#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
+#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
/* AMD-V MSRs */
#define MSR_VM_CR 0xc0010114
diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h
index e9fde88f7d..e272c90eb7 100644
--- a/arch/x86/include/asm/types.h
+++ b/arch/x86/include/asm/types.h
@@ -36,8 +36,13 @@ typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
+#if !defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__)
typedef signed long long s64;
typedef unsigned long long u64;
+#else
+typedef __INT64_TYPE__ s64;
+typedef __UINT64_TYPE__ u64;
+#endif
#define BITS_PER_LONG 32
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 0f36662688..8e7dd424ca 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -35,10 +35,8 @@
unsigned install_e820_map(unsigned max_entries, struct e820entry *);
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
- void **load_address);
+ ulong *load_addressp);
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
unsigned long initrd_addr, unsigned long initrd_size);
-void boot_zimage(void *setup_base, void *load_address);
-
#endif
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 4c5c7f5aa7..86030cf52a 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -10,10 +10,12 @@
#include <common.h>
#include <command.h>
+#include <errno.h>
#include <fdt_support.h>
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/bootparam.h>
+#include <asm/cpu.h>
#include <asm/byteorder.h>
#include <asm/zimage.h>
#ifdef CONFIG_SYS_COREBOOT
@@ -109,17 +111,17 @@ static int boot_prep_linux(bootm_headers_t *images)
}
if (is_zimage) {
- void *load_address;
+ ulong load_address;
char *base_ptr;
base_ptr = (char *)load_zimage(data, len, &load_address);
- images->os.load = (ulong)load_address;
+ images->os.load = load_address;
cmd_line_dest = base_ptr + COMMAND_LINE_OFFSET;
images->ep = (ulong)base_ptr;
} else if (images->ep) {
cmd_line_dest = (void *)images->ep + COMMAND_LINE_OFFSET;
} else {
- printf("## Kernel loading failed (no setup) ...\n");
+ printf("## Kernel loading failed (missing x86 kernel setup) ...\n");
goto error;
}
@@ -139,16 +141,50 @@ error:
return 1;
}
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit)
+{
+ bootm_announce_and_cleanup();
+
+#ifdef CONFIG_SYS_COREBOOT
+ timestamp_add_now(TS_U_BOOT_START_KERNEL);
+#endif
+ if (image_64bit) {
+ if (!cpu_has_64bit()) {
+ puts("Cannot boot 64-bit kernel on 32-bit machine\n");
+ return -EFAULT;
+ }
+ return cpu_jump_to_64bit(setup_base, load_address);
+ } else {
+ /*
+ * Set %ebx, %ebp, and %edi to 0, %esi to point to the
+ * boot_params structure, and then jump to the kernel. We
+ * assume that %cs is 0x10, 4GB flat, and read/execute, and
+ * the data segments are 0x18, 4GB flat, and read/write.
+ * U-boot is setting them up that way for itself in
+ * arch/i386/cpu/cpu.c.
+ */
+ __asm__ __volatile__ (
+ "movl $0, %%ebp\n"
+ "cli\n"
+ "jmp *%[kernel_entry]\n"
+ :: [kernel_entry]"a"(load_address),
+ [boot_params] "S"(setup_base),
+ "b"(0), "D"(0)
+ );
+ }
+
+ /* We can't get to here */
+ return -EFAULT;
+}
+
/* Subcommand: GO */
static int boot_jump_linux(bootm_headers_t *images)
{
debug("## Transferring control to Linux (at address %08lx, kernel %08lx) ...\n",
images->ep, images->os.load);
- boot_zimage((struct boot_params *)images->ep, (void *)images->os.load);
- /* does not return */
-
- return 1;
+ return boot_linux_kernel(images->ep, images->os.load,
+ images->os.arch == IH_ARCH_X86_64);
}
int do_bootm_linux(int flag, int argc, char * const argv[],
@@ -161,10 +197,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
if (flag & BOOTM_STATE_OS_PREP)
return boot_prep_linux(images);
- if (flag & BOOTM_STATE_OS_GO) {
- boot_jump_linux(images);
- return 0;
- }
+ if (flag & BOOTM_STATE_OS_GO)
+ return boot_jump_linux(images);
return boot_jump_linux(images);
}
diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c
index b57b2c30fe..c3c709ec07 100644
--- a/arch/x86/lib/physmem.c
+++ b/arch/x86/lib/physmem.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <physmem.h>
+#include <asm/cpu.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -112,41 +113,13 @@ static void x86_phys_enter_paging(void)
x86_phys_map_page(page_addr, page_addr, 0);
}
- /* Turn on paging */
- __asm__ __volatile__(
- /* Load the page table address */
- "movl %0, %%cr3\n\t"
- /* Enable pae */
- "movl %%cr4, %%eax\n\t"
- "orl $0x00000020, %%eax\n\t"
- "movl %%eax, %%cr4\n\t"
- /* Enable paging */
- "movl %%cr0, %%eax\n\t"
- "orl $0x80000000, %%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- :
- : "r" (pdpt)
- : "eax"
- );
+ cpu_enable_paging_pae((ulong)pdpt);
}
/* Disable paging and PAE mode. */
static void x86_phys_exit_paging(void)
{
- /* Turn off paging */
- __asm__ __volatile__ (
- /* Disable paging */
- "movl %%cr0, %%eax\n\t"
- "andl $0x7fffffff, %%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- /* Disable pae */
- "movl %%cr4, %%eax\n\t"
- "andl $0xffffffdf, %%eax\n\t"
- "movl %%eax, %%cr4\n\t"
- :
- :
- : "eax"
- );
+ cpu_disable_paging_pae();
}
/*
diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index 526daaf93a..faca38fff4 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -16,6 +16,7 @@
*/
#include <common.h>
+#include <inttypes.h>
#include <libfdt.h>
#include <malloc.h>
#include <asm/u-boot-x86.h>
@@ -94,7 +95,7 @@ int do_elf_reloc_fixups(void)
*offset_ptr_ram += gd->reloc_off;
} else {
debug(" %p: rom reloc %x, ram %p, value %x,"
- " limit %lx\n", re_src,
+ " limit %" PRIXPTR "\n", re_src,
re_src->r_offset, offset_ptr_ram,
*offset_ptr_ram,
CONFIG_SYS_TEXT_BASE + size);
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 2f0e92f123..566b048c88 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -103,7 +103,7 @@ static int get_boot_protocol(struct setup_header *hdr)
}
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
- void **load_address)
+ ulong *load_addressp)
{
struct boot_params *setup_base;
int setup_size;
@@ -155,9 +155,9 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
/* Determine load address */
if (big_image)
- *load_address = (void *)BZIMAGE_LOAD_ADDR;
+ *load_addressp = BZIMAGE_LOAD_ADDR;
else
- *load_address = (void *)ZIMAGE_LOAD_ADDR;
+ *load_addressp = ZIMAGE_LOAD_ADDR;
printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base);
memset(setup_base, 0, sizeof(*setup_base));
@@ -204,10 +204,10 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
return 0;
}
- printf("Loading %s at address %p (%ld bytes)\n",
- big_image ? "bzImage" : "zImage", *load_address, kernel_size);
+ printf("Loading %s at address %lx (%ld bytes)\n",
+ big_image ? "bzImage" : "zImage", *load_addressp, kernel_size);
- memmove(*load_address, image + setup_size, kernel_size);
+ memmove((void *)*load_addressp, image + setup_size, kernel_size);
return setup_base;
}
@@ -261,31 +261,6 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
return 0;
}
-void boot_zimage(void *setup_base, void *load_address)
-{
- bootm_announce_and_cleanup();
-
-#ifdef CONFIG_SYS_COREBOOT
- timestamp_add_now(TS_U_BOOT_START_KERNEL);
-#endif
- /*
- * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params
- * structure, and then jump to the kernel. We assume that %cs is
- * 0x10, 4GB flat, and read/execute, and the data segments are 0x18,
- * 4GB flat, and read/write. U-boot is setting them up that way for
- * itself in arch/i386/cpu/cpu.c.
- */
- __asm__ __volatile__ (
- "movl $0, %%ebp\n"
- "cli\n"
- "jmp *%[kernel_entry]\n"
- :: [kernel_entry]"a"(load_address),
- [boot_params] "S"(setup_base),
- "b"(0), "D"(0)
- : "%ebp"
- );
-}
-
void setup_pcat_compatibility(void)
__attribute__((weak, alias("__setup_pcat_compatibility")));
@@ -297,7 +272,7 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
struct boot_params *base_ptr;
void *bzImage_addr = NULL;
- void *load_address;
+ ulong load_address;
char *s;
ulong bzImage_size = 0;
ulong initrd_addr = 0;
@@ -332,20 +307,17 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address);
if (!base_ptr) {
- printf("## Kernel loading failed ...\n");
+ puts("## Kernel loading failed ...\n");
return -1;
}
if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
0, initrd_addr, initrd_size)) {
- printf("Setting up boot parameters failed ...\n");
+ puts("Setting up boot parameters failed ...\n");
return -1;
}
/* we assume that the kernel is in place */
- boot_zimage(base_ptr, load_address);
- /* does not return */
-
- return -1;
+ return boot_linux_kernel((ulong)base_ptr, load_address, false);
}
U_BOOT_CMD(
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