diff options
Diffstat (limited to 'arch')
240 files changed, 16537 insertions, 5946 deletions
diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index b42dac3fbe..2ebee2e960 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -27,7 +27,6 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> -#ifdef CONFIG_SYS_MX31_UART1 void mx31_uart1_hw_init(void) { /* setup pins for UART1 */ @@ -36,9 +35,7 @@ void mx31_uart1_hw_init(void) mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); } -#endif -#ifdef CONFIG_SYS_MX31_UART2 void mx31_uart2_hw_init(void) { /* setup pins for UART2 */ @@ -47,7 +44,6 @@ void mx31_uart2_hw_init(void) mx31_gpio_mux(MUX_RTS2__UART2_RTS_B); mx31_gpio_mux(MUX_CTS2__UART2_CTS_B); } -#endif #ifdef CONFIG_MXC_SPI /* diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 4f27e250bd..f45828141e 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -27,8 +27,6 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> -#define IOMUXGPR (IOMUXC_BASE + 0x008) - static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = GET_PLL_MFI(reg); @@ -89,7 +87,7 @@ static u32 mx31_get_hsp_clk(void) void mx31_dump_clocks(void) { u32 cpufreq = mx31_get_mcu_main_clk(); - printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); + printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000); printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); printf("hsp clock : %dHz\n", mx31_get_hsp_clk()); } @@ -146,14 +144,15 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) void mx31_set_gpr(enum iomux_gp_func gp, char en) { u32 l; + struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE; - l = readl(IOMUXGPR); + l = readl(&iomuxc->gpr); if (en) l |= gp; else l &= ~gp; - writel(l, IOMUXGPR); + writel(l, &iomuxc->gpr); } void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) @@ -216,7 +215,7 @@ static char *get_reset_cause(void) } #if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo (void) +int print_cpuinfo(void) { u32 srev = get_cpu_rev(); diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c index 443d31d221..4bfcef2379 100644 --- a/arch/arm/cpu/arm920t/a320/timer.c +++ b/arch/arm/cpu/arm920t/a320/timer.c @@ -18,20 +18,35 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <faraday/ftpmu010.h> #include <faraday/fttmr010.h> -static ulong timestamp; -static ulong lastdec; - -static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; +DECLARE_GLOBAL_DATA_PTR; #define TIMER_CLOCK 32768 #define TIMER_LOAD_VAL 0xffffffff +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, gd->timer_rate_hz); + + return tick; +} + +static inline unsigned long long usec_to_tick(unsigned long long usec) +{ + usec *= gd->timer_rate_hz; + do_div(usec, 1000000); + + return usec; +} + int timer_init(void) { + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; unsigned int cr; debug("%s()\n", __func__); @@ -59,106 +74,57 @@ int timer_init(void) cr |= FTTMR010_TM3_ENABLE; writel(cr, &tmr->cr); - /* init the timestamp and lastdec value */ - reset_timer_masked(); + gd->timer_rate_hz = TIMER_CLOCK; + gd->tbu = gd->tbl = 0; return 0; } /* - * timer without interrupts - */ - -/* - * reset time - */ -void reset_timer_masked(void) -{ - /* capure current decrementer value time */ - lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); - timestamp = 0; /* start "advancing" time stamp from 0 */ - - debug("%s(): lastdec = %lx\n", __func__, lastdec); -} - -/* - * return timer ticks - */ -ulong get_timer_masked(void) -{ - /* current tick value */ - ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); - - debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); - - if (lastdec >= now) { - /* - * normal mode (non roll) - * move stamp fordward with absoulte diff ticks - */ - timestamp += lastdec - now; - } else { - /* - * we have overflow of the count down timer - * - * nts = ts + ld + (TLV - now) - * ts=old stamp, ld=time that passed before passing through -1 - * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll and - * cause problems. - */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - - lastdec = now; - - debug("%s() returns %lx\n", __func__, timestamp); - - return timestamp; -} - -/* - * return difference between timer ticks and base + * Get the current 64 bit timer tick count */ -ulong get_timer(ulong base) +unsigned long long get_ticks(void) { - debug("%s(%lx)\n", __func__, base); - return get_timer_masked() - base; + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; + ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter); + + /* increment tbu if tbl has rolled over */ + if (now < gd->tbl) + gd->tbu++; + gd->tbl = now; + return (((unsigned long long)gd->tbu) << 32) | gd->tbl; } -/* delay x useconds AND preserve advance timestamp value */ void __udelay(unsigned long usec) { - long tmo = usec * (TIMER_CLOCK / 1000) / 1000; - unsigned long now, last = readl(&tmr->timer3_counter); - - debug("%s(%lu)\n", __func__, usec); - while (tmo > 0) { - now = readl(&tmr->timer3_counter); - if (now > last) /* count down timer overflow */ - tmo -= TIMER_LOAD_VAL + last - now; - else - tmo -= last - now; - last = now; - } + unsigned long long start; + ulong tmo; + + start = get_ticks(); /* get current timestamp */ + tmo = usec_to_tick(usec); /* convert usecs to ticks */ + while ((get_ticks() - start) < tmo) + ; /* loop till time has passed */ } /* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. + * get_timer(base) can be used to check for timeouts or + * to measure elasped time relative to an event: + * + * ulong start_time = get_timer(0) sets start_time to the current + * time value. + * get_timer(start_time) returns the time elapsed since then. + * + * The time is used in CONFIG_SYS_HZ units! */ -unsigned long long get_ticks(void) +ulong get_timer(ulong base) { - debug("%s()\n", __func__); - return get_timer(0); + return tick_to_time(get_ticks()) - base; } /* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. + * Return the number of timer ticks per second. */ ulong get_tbclk(void) { - debug("%s()\n", __func__); - return CONFIG_SYS_HZ; + return gd->timer_rate_hz; } diff --git a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c b/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c index 412f502c36..4caa1579db 100644 --- a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c +++ b/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c @@ -5,7 +5,7 @@ * Andreas Bießmann <andreas.devel@googlemail.com> * * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 930e0d1bfc..5923e6548f 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -26,7 +26,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o START = start.o -COBJS = cpu.o +COBJS = cpu.o cache.o + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE +START := +endif +endif SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c index 2d878fdde6..db2ecb8c81 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * (C) Copyright 2009 diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index 65b8d516fd..a4e9f09f0c 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c index edc797214c..ae8cd56c5a 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c index 6eb0f305b7..7191db26ad 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * (C) Copyright 2009-2011 diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 5ff32e3749..f31c364374 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c index b0a16874d6..ca44cf5a33 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c index 6e59c86675..a1bb28d72f 100644 --- a/arch/arm/cpu/arm926ejs/at91/led.c +++ b/arch/arm/cpu/arm926ejs/at91/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c index 023719a683..f6a7cb7a86 100644 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ b/arch/arm/cpu/arm926ejs/at91/reset.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index a0876879d3..f70ce83f08 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c new file mode 100644 index 0000000000..441564203b --- /dev/null +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2011 + * Ilya Yanok, EmCraft Systems + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include <linux/types.h> +#include <common.h> + +#ifndef CONFIG_SYS_DCACHE_OFF +static inline void dcache_noop(void) +{ + if (dcache_status()) { + puts("WARNING: cache operations are not implemented!\n" + "WARNING: disabling D-Cache now, you can re-enable it" + "later with 'dcache on' command\n"); + dcache_disable(); + } +} + +void invalidate_dcache_all(void) +{ + dcache_noop(); +} + +void flush_dcache_all(void) +{ + dcache_noop(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + dcache_noop(); +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + dcache_noop(); +} +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +void invalidate_dcache_all(void) +{ +} + +void flush_dcache_all(void) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_cache(unsigned long start, unsigned long size) +{ +} +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index 98c7e55c40..5ae89df5db 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -27,12 +27,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS-y += cpu.o timer.o psc.o -COBJS-$(CONFIG_AM18018_LOWLEVEL) += am1808_lowlevel.o +COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o +COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_SOC_DM646X) += dm646x.o +COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c deleted file mode 100644 index 1ea4a9ffce..0000000000 --- a/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * SoC-specific lowlevel code for AM1808 and similar chips - * - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include <common.h> -#include <nand.h> -#include <ns16550.h> -#include <post.h> -#include <asm/arch/am1808_lowlevel.h> -#include <asm/arch/hardware.h> -#include <asm/arch/ddr2_defs.h> -#include <asm/arch/emif_defs.h> - -void am1808_waitloop(unsigned long loopcnt) -{ - unsigned long i; - - for (i = 0; i < loopcnt; i++) - asm(" NOP"); -} - -int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) -{ - if (reg == davinci_pllc0_regs) - /* Unlock PLL registers. */ - clrbits_le32(&davinci_syscfg_regs->cfgchip0, 0x00000010); - - /* - * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled - * through MMR - */ - clrbits_le32(®->pllctl, 0x00000020); - /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */ - clrbits_le32(®->pllctl, 0x00000200); - - /* Set PLLEN=0 => PLL BYPASS MODE */ - clrbits_le32(®->pllctl, 0x00000001); - - am1808_waitloop(150); - - if (reg == davinci_pllc0_regs) { - /* - * Select the Clock Mode bit 8 as External Clock or On Chip - * Oscilator - */ - dv_maskbits(®->pllctl, 0xFFFFFEFF); - setbits_le32(®->pllctl, (CONFIG_SYS_DV_CLKMODE << 8)); - } - - /* Clear PLLRST bit to reset the PLL */ - clrbits_le32(®->pllctl, 0x00000008); - - /* Disable the PLL output */ - setbits_le32(®->pllctl, 0x00000010); - - /* PLL initialization sequence */ - /* - * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of - * power down bit - */ - clrbits_le32(®->pllctl, 0x00000002); - - /* Enable the PLL from Disable Mode PLLDIS bit to 0 */ - clrbits_le32(®->pllctl, 0x00000010); - - /* Program the required multiplier value in PLLM */ - writel(pllmult, ®->pllm); - - /* program the postdiv */ - if (reg == davinci_pllc0_regs) - writel((0x8000 | CONFIG_SYS_AM1808_PLL0_POSTDIV), - ®->postdiv); - else - writel((0x8000 | CONFIG_SYS_AM1808_PLL1_POSTDIV), - ®->postdiv); - - /* - * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that - * no GO operation is currently in progress - */ - while ((readl(®->pllstat) & 0x1) == 1) - ; - - if (reg == davinci_pllc0_regs) { - writel(CONFIG_SYS_AM1808_PLL0_PLLDIV1, ®->plldiv1); - writel(CONFIG_SYS_AM1808_PLL0_PLLDIV2, ®->plldiv2); - writel(CONFIG_SYS_AM1808_PLL0_PLLDIV3, ®->plldiv3); - writel(CONFIG_SYS_AM1808_PLL0_PLLDIV4, ®->plldiv4); - writel(CONFIG_SYS_AM1808_PLL0_PLLDIV5, ®->plldiv5); - writel(CONFIG_SYS_AM1808_PLL0_PLLDIV6, ®->plldiv6); - writel(CONFIG_SYS_AM1808_PLL0_PLLDIV7, ®->plldiv7); - } else { - writel(CONFIG_SYS_AM1808_PLL1_PLLDIV1, ®->plldiv1); - writel(CONFIG_SYS_AM1808_PLL1_PLLDIV2, ®->plldiv2); - writel(CONFIG_SYS_AM1808_PLL1_PLLDIV3, ®->plldiv3); - } - - /* - * Set the GOSET bit in PLLCMD to 1 to initiate a new divider - * transition. - */ - setbits_le32(®->pllcmd, 0x01); - - /* - * Wait for the GOSTAT bit in PLLSTAT to clear to 0 - * (completion of phase alignment). - */ - while ((readl(®->pllstat) & 0x1) == 1) - ; - - /* Wait for PLL to reset properly. See PLL spec for PLL reset time */ - am1808_waitloop(200); - - /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */ - setbits_le32(®->pllctl, 0x00000008); - - /* Wait for PLL to lock. See PLL spec for PLL lock time */ - am1808_waitloop(2400); - - /* - * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass - * mode - */ - setbits_le32(®->pllctl, 0x00000001); - - - /* - * clear EMIFA and EMIFB clock source settings, let them - * run off SYSCLK - */ - if (reg == davinci_pllc0_regs) - dv_maskbits(&davinci_syscfg_regs->cfgchip3, 0xFFFFFFF8); - - return 0; -} - -void am1808_lpc_transition(unsigned char pscnum, unsigned char module, - unsigned char domain, unsigned char state) -{ - struct davinci_psc_regs *reg; - dv_reg_p mdstat, mdctl; - - if (pscnum == 0) { - reg = davinci_psc0_regs; - mdstat = ®->psc0.mdstat[module]; - mdctl = ®->psc0.mdctl[module]; - } else { - reg = davinci_psc1_regs; - mdstat = ®->psc1.mdstat[module]; - mdctl = ®->psc1.mdctl[module]; - } - - /* Wait for any outstanding transition to complete */ - while ((readl(®->ptstat) & (0x00000001 << domain))) - ; - - /* If we are already in that state, just return */ - if ((readl(mdstat) & 0x1F) == state) - return; - - /* Perform transition */ - writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl); - setbits_le32(®->ptcmd, (0x00000001 << domain)); - - /* Wait for transition to complete */ - while (readl(®->ptstat) & (0x00000001 << domain)) - ; - - /* Wait and verify the state */ - while ((readl(mdstat) & 0x1F) != state) - ; -} - -int am1808_ddr_setup(unsigned int freq) -{ - unsigned long tmp; - - /* Enable the Clock to DDR2/mDDR */ - am1808_lpc_transition(1, 6, 0, PSC_ENABLE); - - tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); - if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) { - /* Begin VTP Calibration */ - clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); - clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); - setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); - clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); - setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); - - /* Polling READY bit to see when VTP calibration is done */ - tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); - while ((tmp & VTP_READY) != VTP_READY) - tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); - - setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); - setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); - - setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); - } - - writel(CONFIG_SYS_AM1808_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); - clrbits_le32(&davinci_syscfg1_regs->ddr_slew, - (1 << DDR_SLEW_CMOSEN_BIT)); - - setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK); - - writel((CONFIG_SYS_AM1808_DDR2_SDBCR & ~0xf0000000) | - (readl(&dv_ddr2_regs_ctrl->sdbcr) & 0xf0000000), /*rsv Bytes*/ - &dv_ddr2_regs_ctrl->sdbcr); - writel(CONFIG_SYS_AM1808_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); - - writel(CONFIG_SYS_AM1808_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); - writel(CONFIG_SYS_AM1808_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); - - clrbits_le32(&dv_ddr2_regs_ctrl->sdbcr, - (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)); - - /* - * LPMODEN and MCLKSTOPEN must be set! - * Without this bits set, PSC don;t switch states !! - */ - writel(CONFIG_SYS_AM1808_DDR2_SDRCR | - (1 << DV_DDR_SRCR_LPMODEN_SHIFT) | - (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT), - &dv_ddr2_regs_ctrl->sdrcr); - - /* SyncReset the Clock to EMIF3A SDRAM */ - am1808_lpc_transition(1, 6, 0, PSC_SYNCRESET); - /* Enable the Clock to EMIF3A SDRAM */ - am1808_lpc_transition(1, 6, 0, PSC_ENABLE); - - /* disable self refresh */ - clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000); - writel(0x30, &dv_ddr2_regs_ctrl->pbbpr); - - return 0; -} - -static void am1808_set_mdctl(dv_reg_p mdctl) -{ - if ((readl(mdctl) & 0x1F) != PSC_ENABLE) - writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl); -} - -void am1808_psc_init(void) -{ - struct davinci_psc_regs *reg; - int i; - - /* PSC 0 domain 0 init */ - reg = davinci_psc0_regs; - while ((readl(®->ptstat) & 0x00000001)) - ; - - for (i = 3; i <= 4 ; i++) - am1808_set_mdctl(®->psc0.mdctl[i]); - - for (i = 7; i <= 12 ; i++) - am1808_set_mdctl(®->psc0.mdctl[i]); - - /* Do Always-On Power Domain Transitions */ - setbits_le32(®->ptcmd, 0x00000001); - while (readl(®->ptstat) & 0x00000001) - ; - - /* PSC1, domain 1 init */ - reg = davinci_psc1_regs; - while ((readl(®->ptstat) & 0x00000001)) - ; - - am1808_set_mdctl(®->psc1.mdctl[3]); - am1808_set_mdctl(®->psc1.mdctl[6]); - - /* UART1 + UART2 */ - for (i = 12 ; i <= 13 ; i++) - am1808_set_mdctl(®->psc1.mdctl[i]); - - am1808_set_mdctl(®->psc1.mdctl[26]); - am1808_set_mdctl(®->psc1.mdctl[31]); - - /* Do Always-On Power Domain Transitions */ - setbits_le32(®->ptcmd, 0x00000001); - while (readl(®->ptstat) & 0x00000001) - ; -} - -void am1808_pinmux_ctl(unsigned long offset, unsigned long mask, - unsigned long value) -{ - clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask); - setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value)); -} - -__attribute__((weak)) -void board_gpio_init(void) -{ - return; -} - -#if defined(CONFIG_NAND_SPL) -void nand_boot(void) -{ - __attribute__((noreturn)) void (*uboot)(void); - - /* copy image from NOR to RAM */ - memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, - (void *)CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE); - - /* and jump to it ... */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; - (*uboot)(); -} -#endif - -#if defined(CONFIG_NAND_SPL) -void board_init_f(ulong bootflag) -#else -int arch_cpu_init(void) -#endif -{ - /* - * copied from arch/arm/cpu/arm926ejs/start.S - * - * flush v4 I/D caches - */ - asm("mov r0, #0"); - asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */ - asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - asm("mrc p15, 0, r0, c1, c0, 0"); - /* clear bits 13, 9:8 (--V- --RS) */ - asm("bic r0, r0, #0x00002300"); - /* clear bits 7, 2:0 (B--- -CAM) */ - asm("bic r0, r0, #0x00000087"); - /* set bit 2 (A) Align */ - asm("orr r0, r0, #0x00000002"); - /* set bit 12 (I) I-Cache */ - asm("orr r0, r0, #0x00001000"); - asm("mcr p15, 0, r0, c1, c0, 0"); - - /* Unlock kick registers */ - writel(0x83e70b13, &davinci_syscfg_regs->kick0); - writel(0x95a4f1e0, &davinci_syscfg_regs->kick1); - - dv_maskbits(&davinci_syscfg_regs->suspsrc, - ((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16))); - - /* System PSC setup - enable all */ - am1808_psc_init(); - - /* Setup Pinmux */ - am1808_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX0); - am1808_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX1); - am1808_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX2); - am1808_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX3); - am1808_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX4); - am1808_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX5); - am1808_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX6); - am1808_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX7); - am1808_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX8); - am1808_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX9); - am1808_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX10); - am1808_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX11); - am1808_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX12); - am1808_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX13); - am1808_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX14); - am1808_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX15); - am1808_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX16); - am1808_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX17); - am1808_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX18); - am1808_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX19); - - /* PLL setup */ - am1808_pll_init(davinci_pllc0_regs, CONFIG_SYS_AM1808_PLL0_PLLM); - am1808_pll_init(davinci_pllc1_regs, CONFIG_SYS_AM1808_PLL1_PLLM); - - /* GPIO setup */ - board_gpio_init(); - - /* setup CSn config */ - writel(CONFIG_SYS_AM1808_CS2CFG, &davinci_emif_regs->ab1cr); - writel(CONFIG_SYS_AM1808_CS3CFG, &davinci_emif_regs->ab2cr); - - am1808_lpc_transition(1, 13, 0, PSC_ENABLE); - NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - - /* - * Fix Power and Emulation Management Register - * see sprufw3a.pdf page 37 Table 24 - */ - writel(readl((CONFIG_SYS_NS16550_COM1 + 0x30)) | 0x00006001, - (CONFIG_SYS_NS16550_COM1 + 0x30)); -#if defined(CONFIG_NAND_SPL) - puts("ddr init\n"); - am1808_ddr_setup(132); - - puts("boot u-boot ...\n"); - - nand_boot(); -#else - am1808_ddr_setup(132); - return 0; -#endif -} diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c new file mode 100644 index 0000000000..a532f8ab60 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -0,0 +1,291 @@ +/* + * SoC-specific lowlevel code for DA850 + * + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <common.h> +#include <nand.h> +#include <ns16550.h> +#include <post.h> +#include <asm/arch/da850_lowlevel.h> +#include <asm/arch/hardware.h> +#include <asm/arch/davinci_misc.h> +#include <asm/arch/ddr2_defs.h> +#include <asm/arch/emif_defs.h> +#include <asm/arch/pll_defs.h> + +void da850_waitloop(unsigned long loopcnt) +{ + unsigned long i; + + for (i = 0; i < loopcnt; i++) + asm(" NOP"); +} + +int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) +{ + if (reg == davinci_pllc0_regs) + /* Unlock PLL registers. */ + clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK); + + /* + * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled + * through MMR + */ + clrbits_le32(®->pllctl, PLLCTL_PLLENSRC); + /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */ + clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC); + + /* Set PLLEN=0 => PLL BYPASS MODE */ + clrbits_le32(®->pllctl, PLLCTL_PLLEN); + + da850_waitloop(150); + + if (reg == davinci_pllc0_regs) { + /* + * Select the Clock Mode bit 8 as External Clock or On Chip + * Oscilator + */ + dv_maskbits(®->pllctl, ~PLLCTL_RES_9); + setbits_le32(®->pllctl, + (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT)); + } + + /* Clear PLLRST bit to reset the PLL */ + clrbits_le32(®->pllctl, PLLCTL_PLLRST); + + /* Disable the PLL output */ + setbits_le32(®->pllctl, PLLCTL_PLLDIS); + + /* PLL initialization sequence */ + /* + * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of + * power down bit + */ + clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN); + + /* Enable the PLL from Disable Mode PLLDIS bit to 0 */ + clrbits_le32(®->pllctl, PLLCTL_PLLDIS); + + /* Program the required multiplier value in PLLM */ + writel(pllmult, ®->pllm); + + /* program the postdiv */ + if (reg == davinci_pllc0_regs) + writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV), + ®->postdiv); + else + writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV), + ®->postdiv); + + /* + * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that + * no GO operation is currently in progress + */ + while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT) + ; + + if (reg == davinci_pllc0_regs) { + writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1); + writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2); + writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3); + writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4); + writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5); + writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6); + writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7); + } else { + writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1); + writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2); + writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3); + } + + /* + * Set the GOSET bit in PLLCMD to 1 to initiate a new divider + * transition. + */ + setbits_le32(®->pllcmd, PLLCMD_GOSTAT); + + /* + * Wait for the GOSTAT bit in PLLSTAT to clear to 0 + * (completion of phase alignment). + */ + while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT) + ; + + /* Wait for PLL to reset properly. See PLL spec for PLL reset time */ + da850_waitloop(200); + + /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */ + setbits_le32(®->pllctl, PLLCTL_PLLRST); + + /* Wait for PLL to lock. See PLL spec for PLL lock time */ + da850_waitloop(2400); + + /* + * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass + * mode + */ + setbits_le32(®->pllctl, PLLCTL_PLLEN); + + + /* + * clear EMIFA and EMIFB clock source settings, let them + * run off SYSCLK + */ + if (reg == davinci_pllc0_regs) + dv_maskbits(&davinci_syscfg_regs->cfgchip3, + ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC)); + + return 0; +} + +int da850_ddr_setup(void) +{ + unsigned long tmp; + + /* Enable the Clock to DDR2/mDDR */ + lpsc_on(DAVINCI_LPSC_DDR_EMIF); + + tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); + if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) { + /* Begin VTP Calibration */ + clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); + clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); + setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); + clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); + setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); + + /* Polling READY bit to see when VTP calibration is done */ + tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); + while ((tmp & VTP_READY) != VTP_READY) + tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); + + setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); + setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); + + setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); + } + + writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); + clrbits_le32(&davinci_syscfg1_regs->ddr_slew, + (1 << DDR_SLEW_CMOSEN_BIT)); + + /* + * SDRAM Configuration Register (SDCR): + * First set the BOOTUNLOCK bit to make configuration bits + * writeable. + */ + setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK); + + /* + * Write the new value of these bits and clear BOOTUNLOCK. + * At the same time, set the TIMUNLOCK bit to allow changing + * the timing registers + */ + tmp = CONFIG_SYS_DA850_DDR2_SDBCR; + tmp &= ~DV_DDR_BOOTUNLOCK; + tmp |= DV_DDR_TIMUNLOCK; + writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); + + /* write memory configuration and timing */ + writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); + writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); + writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); + + /* clear the TIMUNLOCK bit and write the value of the CL field */ + tmp &= ~DV_DDR_TIMUNLOCK; + writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); + + /* + * LPMODEN and MCLKSTOPEN must be set! + * Without this bits set, PSC don;t switch states !! + */ + writel(CONFIG_SYS_DA850_DDR2_SDRCR | + (1 << DV_DDR_SRCR_LPMODEN_SHIFT) | + (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT), + &dv_ddr2_regs_ctrl->sdrcr); + + /* SyncReset the Clock to EMIF3A SDRAM */ + lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF); + /* Enable the Clock to EMIF3A SDRAM */ + lpsc_on(DAVINCI_LPSC_DDR_EMIF); + + /* disable self refresh */ + clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, + DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN); + writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); + + return 0; +} + +__attribute__((weak)) +void board_gpio_init(void) +{ + return; +} + +/* pinmux_resource[] vector is defined in the board specific file */ +extern const struct pinmux_resource pinmuxes[]; +extern const int pinmuxes_size; + +int arch_cpu_init(void) +{ + /* Unlock kick registers */ + writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); + writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); + + dv_maskbits(&davinci_syscfg_regs->suspsrc, + CONFIG_SYS_DA850_SYSCFG_SUSPSRC); + + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size)) + return 1; + + /* PLL setup */ + da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM); + da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM); + + /* GPIO setup */ + board_gpio_init(); + + /* setup CSn config */ +#if defined(CONFIG_SYS_DA850_CS2CFG) + writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr); +#endif +#if defined(CONFIG_SYS_DA850_CS3CFG) + writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr); +#endif + + lpsc_on(CONFIG_SYS_DA850_LPSC_UART); + NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + + /* + * Fix Power and Emulation Management Register + * see sprufw3a.pdf page 37 Table 24 + */ + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), + &davinci_uart2_ctrl_regs->pwremu_mgmt); + + da850_ddr_setup(); + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c new file mode 100644 index 0000000000..fa07fb591f --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c @@ -0,0 +1,171 @@ +/* + * Pinmux configurations for the DA850 SoCs + * + * Copyright (C) 2011 OMICRON electronics GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/arch/davinci_misc.h> +#include <asm/arch/hardware.h> +#include <asm/arch/pinmux_defs.h> + +/* SPI pin muxer settings */ +const struct pinmux_config spi1_pins_base[] = { + { pinmux(5), 1, 2 }, /* SPI1_CLK */ + { pinmux(5), 1, 4 }, /* SPI1_SOMI */ + { pinmux(5), 1, 5 }, /* SPI1_SIMO */ +}; + +const struct pinmux_config spi1_pins_scs0[] = { + { pinmux(5), 1, 1 }, /* SPI1_SCS[0] */ +}; + +/* UART pin muxer settings */ +const struct pinmux_config uart1_pins_txrx[] = { + { pinmux(4), 2, 6 }, /* UART1_RXD */ + { pinmux(4), 2, 7 }, /* UART1_TXD */ +}; + +const struct pinmux_config uart2_pins_txrx[] = { + { pinmux(4), 2, 4 }, /* UART2_RXD */ + { pinmux(4), 2, 5 }, /* UART2_TXD */ +}; + +const struct pinmux_config uart2_pins_rtscts[] = { + { pinmux(0), 4, 6 }, /* UART2_RTS */ + { pinmux(0), 4, 7 }, /* UART2_CTS */ +}; + +/* EMAC pin muxer settings*/ +const struct pinmux_config emac_pins_rmii[] = { + { pinmux(14), 8, 2 }, /* RMII_TXD[1] */ + { pinmux(14), 8, 3 }, /* RMII_TXD[0] */ + { pinmux(14), 8, 4 }, /* RMII_TXEN */ + { pinmux(14), 8, 5 }, /* RMII_RXD[1] */ + { pinmux(14), 8, 6 }, /* RMII_RXD[0] */ + { pinmux(14), 8, 7 }, /* RMII_RXER */ + { pinmux(15), 8, 1 }, /* RMII_CRS_DV */ +}; + +const struct pinmux_config emac_pins_mii[] = { + { pinmux(2), 8, 1 }, /* MII_TXEN */ + { pinmux(2), 8, 2 }, /* MII_TXCLK */ + { pinmux(2), 8, 3 }, /* MII_COL */ + { pinmux(2), 8, 4 }, /* MII_TXD[3] */ + { pinmux(2), 8, 5 }, /* MII_TXD[2] */ + { pinmux(2), 8, 6 }, /* MII_TXD[1] */ + { pinmux(2), 8, 7 }, /* MII_TXD[0] */ + { pinmux(3), 8, 0 }, /* MII_RXCLK */ + { pinmux(3), 8, 1 }, /* MII_RXDV */ + { pinmux(3), 8, 2 }, /* MII_RXER */ + { pinmux(3), 8, 3 }, /* MII_CRS */ + { pinmux(3), 8, 4 }, /* MII_RXD[3] */ + { pinmux(3), 8, 5 }, /* MII_RXD[2] */ + { pinmux(3), 8, 6 }, /* MII_RXD[1] */ + { pinmux(3), 8, 7 }, /* MII_RXD[0] */ +}; + +const struct pinmux_config emac_pins_mdio[] = { + { pinmux(4), 8, 0 }, /* MDIO_CLK */ + { pinmux(4), 8, 1 }, /* MDIO_D */ +}; + +/* I2C pin muxer settings */ +const struct pinmux_config i2c0_pins[] = { + { pinmux(4), 2, 2 }, /* I2C0_SCL */ + { pinmux(4), 2, 3 }, /* I2C0_SDA */ +}; + +const struct pinmux_config i2c1_pins[] = { + { pinmux(4), 4, 4 }, /* I2C1_SCL */ + { pinmux(4), 4, 5 }, /* I2C1_SDA */ +}; + +/* EMIFA pin muxer settings */ +const struct pinmux_config emifa_pins_cs2[] = { + { pinmux(7), 1, 0 }, /* EMA_CS2 */ +}; + +const struct pinmux_config emifa_pins_cs3[] = { + { pinmux(7), 1, 1 }, /* EMA_CS[3] */ +}; + +const struct pinmux_config emifa_pins_cs4[] = { + { pinmux(7), 1, 2 }, /* EMA_CS[4] */ +}; + +const struct pinmux_config emifa_pins_nand[] = { + { pinmux(7), 1, 4 }, /* EMA_WE */ + { pinmux(7), 1, 5 }, /* EMA_OE */ + { pinmux(9), 1, 0 }, /* EMA_D[7] */ + { pinmux(9), 1, 1 }, /* EMA_D[6] */ + { pinmux(9), 1, 2 }, /* EMA_D[5] */ + { pinmux(9), 1, 3 }, /* EMA_D[4] */ + { pinmux(9), 1, 4 }, /* EMA_D[3] */ + { pinmux(9), 1, 5 }, /* EMA_D[2] */ + { pinmux(9), 1, 6 }, /* EMA_D[1] */ + { pinmux(9), 1, 7 }, /* EMA_D[0] */ + { pinmux(12), 1, 5 }, /* EMA_A[2] */ + { pinmux(12), 1, 6 }, /* EMA_A[1] */ +}; + +/* NOR pin muxer settings */ +const struct pinmux_config emifa_pins_nor[] = { + { pinmux(5), 1, 6 }, /* EMA_BA[1] */ + { pinmux(6), 1, 6 }, /* EMA_WAIT[1] */ + { pinmux(7), 1, 4 }, /* EMA_WE */ + { pinmux(7), 1, 5 }, /* EMA_OE */ + { pinmux(8), 1, 0 }, /* EMA_D[15] */ + { pinmux(8), 1, 1 }, /* EMA_D[14] */ + { pinmux(8), 1, 2 }, /* EMA_D[13] */ + { pinmux(8), 1, 3 }, /* EMA_D[12] */ + { pinmux(8), 1, 4 }, /* EMA_D[11] */ + { pinmux(8), 1, 5 }, /* EMA_D[10] */ + { pinmux(8), 1, 6 }, /* EMA_D[9] */ + { pinmux(8), 1, 7 }, /* EMA_D[8] */ + { pinmux(9), 1, 0 }, /* EMA_D[7] */ + { pinmux(9), 1, 1 }, /* EMA_D[6] */ + { pinmux(9), 1, 2 }, /* EMA_D[5] */ + { pinmux(9), 1, 3 }, /* EMA_D[4] */ + { pinmux(9), 1, 4 }, /* EMA_D[3] */ + { pinmux(9), 1, 5 }, /* EMA_D[2] */ + { pinmux(9), 1, 6 }, /* EMA_D[1] */ + { pinmux(9), 1, 7 }, /* EMA_D[0] */ + { pinmux(10), 1, 1 }, /* EMA_A[22] */ + { pinmux(10), 1, 2 }, /* EMA_A[21] */ + { pinmux(10), 1, 3 }, /* EMA_A[20] */ + { pinmux(10), 1, 4 }, /* EMA_A[19] */ + { pinmux(10), 1, 5 }, /* EMA_A[18] */ + { pinmux(10), 1, 6 }, /* EMA_A[17] */ + { pinmux(10), 1, 7 }, /* EMA_A[16] */ + { pinmux(11), 1, 0 }, /* EMA_A[15] */ + { pinmux(11), 1, 1 }, /* EMA_A[14] */ + { pinmux(11), 1, 2 }, /* EMA_A[13] */ + { pinmux(11), 1, 3 }, /* EMA_A[12] */ + { pinmux(11), 1, 4 }, /* EMA_A[11] */ + { pinmux(11), 1, 5 }, /* EMA_A[10] */ + { pinmux(11), 1, 6 }, /* EMA_A[9] */ + { pinmux(11), 1, 7 }, /* EMA_A[8] */ + { pinmux(12), 1, 0 }, /* EMA_A[7] */ + { pinmux(12), 1, 1 }, /* EMA_A[6] */ + { pinmux(12), 1, 2 }, /* EMA_A[5] */ + { pinmux(12), 1, 3 }, /* EMA_A[4] */ + { pinmux(12), 1, 4 }, /* EMA_A[3] */ + { pinmux(12), 1, 5 }, /* EMA_A[2] */ + { pinmux(12), 1, 6 }, /* EMA_A[1] */ + { pinmux(12), 1, 7 }, /* EMA_A[0] */ +}; diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c index 3772e64cc4..6e998ded99 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c @@ -45,7 +45,8 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN); clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); - setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8); + setbits_le32(&dv_pll0_regs->pllctl, + clksrc << PLLCTL_CLOCK_MODE_SHIFT); /* * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled @@ -82,7 +83,7 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); /* Program the PostDiv for PLL1 */ - writel(0x8000, &dv_pll0_regs->postdiv); + writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); /* Post divider setting for PLL1 */ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1); @@ -126,7 +127,8 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv) * VDB has input on MXI pin */ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9); - setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8); + setbits_le32(&dv_pll1_regs->pllctl, + clksrc << PLLCTL_CLOCK_MODE_SHIFT); /* * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled @@ -151,7 +153,7 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv) writel(pllm, &dv_pll1_regs->pllm); writel(prediv, &dv_pll1_regs->prediv); - writel(0x8000, &dv_pll1_regs->postdiv); + writel(PLL_POSTDEN, &dv_pll1_regs->postdiv); /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE | @@ -261,21 +263,23 @@ void dm365_vpss_sync_reset(void) VPSS_CLK_CTL_VPSS_CLKMD); /* LPSC SyncReset DDR Clock Enable */ - writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) | - PSC_SYNCRESET), &dv_psc_regs->mdctl[47]); + writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) & + ~PSC_MD_STATE_MSK) | PSC_SYNCRESET), + &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]); writel((1 << PdNum), &dv_psc_regs->ptcmd); while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0)) ; - while (!((readl(&dv_psc_regs->mdstat[47]) & PSC_MD_STATE_MSK) == - PSC_SYNCRESET)) + while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) & + PSC_MD_STATE_MSK) == PSC_SYNCRESET)) ; } void dm365_por_reset(void) { - if (readl(&dv_pll0_regs->rstype) & 3) + if (readl(&dv_pll0_regs->rstype) & + (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) dm365_vpss_sync_reset(); } @@ -291,19 +295,20 @@ void dm365_psc_init(void) for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) { if (lpscgroup == 0) { - lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */ - lpsc_end = 28; + /* Enabling LPSC 3 to 28 SCR first */ + lpsc_start = DAVINCI_LPSC_VPSSMSTR; + lpsc_end = DAVINCI_LPSC_TIMER1; } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */ - lpsc_start = 38; - lpsc_end = 47; + lpsc_start = DAVINCI_LPSC_CFG5; + lpsc_end = DAVINCI_LPSC_VPSSMASTER; } else { - lpsc_start = 50; - lpsc_end = 51; + lpsc_start = DAVINCI_LPSC_MJCP; + lpsc_end = DAVINCI_LPSC_HDVICP; } /* NEXT=0x3, Enable LPSC's */ for (i = lpsc_start; i <= lpsc_end; i++) - setbits_le32(&dv_psc_regs->mdctl[i], 0x3); + setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE); /* * Program goctl to start transition sequence for LPSCs @@ -322,7 +327,7 @@ void dm365_psc_init(void) /* Wait for MODSTAT = ENABLE from LPSC's */ for (i = lpsc_start; i <= lpsc_end; i++) while (!((readl(&dv_psc_regs->mdstat[i]) & - PSC_MD_STATE_MSK) == 0x3)) + PSC_MD_STATE_MSK) == PSC_ENABLE)) ; } } @@ -332,7 +337,7 @@ static void dm365_emif_init(void) writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr); writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr); - setbits_le32(&davinci_emif_regs->nandfcr, 1); + setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND); writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr); @@ -361,31 +366,12 @@ int post_log(char *format, ...) void dm36x_lowlevel_init(ulong bootflag) { - /* - * copied from arch/arm/cpu/arm926ejs/start.S - * - * flush v4 I/D caches - */ - asm("mov r0, #0"); - asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */ - asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - asm("mrc p15, 0, r0, c1, c0, 0"); - /* clear bits 13, 9:8 (--V- --RS) */ - asm("bic r0, r0, #0x00002300"); - /* clear bits 7, 2:0 (B--- -CAM) */ - asm("bic r0, r0, #0x00000087"); - /* set bit 2 (A) Align */ - asm("orr r0, r0, #0x00000002"); - /* set bit 12 (I) I-Cache */ - asm("orr r0, r0, #0x00001000"); - asm("mcr p15, 0, r0, c1, c0, 0"); + struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs = + (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 + + DAVINCI_UART_CTRL_BASE); /* Mask all interrupts */ - writel(0x04, &dv_aintc_regs->intctl); + writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl); writel(0x0, &dv_aintc_regs->eabase); writel(0x0, &dv_aintc_regs->eint0); writel(0x0, &dv_aintc_regs->eint1); @@ -422,7 +408,10 @@ void dm36x_lowlevel_init(ulong bootflag) * Fix Power and Emulation Management Register * see sprufh2.pdf page 38 Table 22 */ - writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30)); + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), + &davinci_uart_ctrl_regs->pwremu_mgmt); + puts("ddr init\n"); dm365_ddr_setup(); diff --git a/arch/arm/cpu/arm926ejs/davinci/dp83848.c b/arch/arm/cpu/arm926ejs/davinci/dp83848.c index c71c685f72..d435e4bed7 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dp83848.c +++ b/arch/arm/cpu/arm926ejs/davinci/dp83848.c @@ -29,6 +29,7 @@ #include <net.h> #include <dp83848.h> #include <asm/arch/emac_defs.h> +#include "../../../../../drivers/net/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/cpu/arm926ejs/davinci/et1011c.c index df35e44d13..68650e5a62 100644 --- a/arch/arm/cpu/arm926ejs/davinci/et1011c.c +++ b/arch/arm/cpu/arm926ejs/davinci/et1011c.c @@ -22,6 +22,7 @@ #include <net.h> #include <miiphy.h> #include <asm/arch/emac_defs.h> +#include "../../../../../drivers/net/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c b/arch/arm/cpu/arm926ejs/davinci/ksz8873.c index 634eda0a02..3546e7fe2a 100644 --- a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c +++ b/arch/arm/cpu/arm926ejs/davinci/ksz8873.c @@ -36,6 +36,7 @@ #include <net.h> #include <asm/arch/emac_defs.h> #include <asm/io.h> +#include "../../../../../drivers/net/davinci_emac.h" int ksz8873_is_phy_connected(int phy_addr) { diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c index 733d413729..cce1fe4cb2 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c +++ b/arch/arm/cpu/arm926ejs/davinci/lxt972.c @@ -30,6 +30,7 @@ #include <miiphy.h> #include <lxt971a.h> #include <asm/arch/emac_defs.h> +#include "../../../../../drivers/net/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/cpu/arm926ejs/davinci/misc.c new file mode 100644 index 0000000000..5f510b61db --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/misc.c @@ -0,0 +1,150 @@ +/* + * Miscelaneous DaVinci functions. + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <i2c.h> +#include <net.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <asm/arch/davinci_misc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SPL_BUILD +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} +#endif + +#ifdef CONFIG_DRIVER_TI_EMAC +/* + * Read ethernet MAC address from EEPROM for DVEVM compatible boards. + * Returns 1 if found, 0 otherwise. + */ +int dvevm_read_mac_address(uint8_t *buf) +{ +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR + /* Read MAC address. */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6)) + goto i2cerr; + + /* Check that MAC address is valid. */ + if (!is_valid_ether_addr(buf)) + goto err; + + return 1; /* Found */ + +i2cerr: + printf("Read from EEPROM @ 0x%02x failed\n", + CONFIG_SYS_I2C_EEPROM_ADDR); +err: +#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ + + return 0; +} + +/* + * Set the mii mode as MII or RMII + */ +#if defined(CONFIG_SOC_DA8XX) +void davinci_emac_mii_mode_sel(int mode_sel) +{ + int val; + + val = readl(&davinci_syscfg_regs->cfgchip3); + if (mode_sel == 0) + val &= ~(1 << 8); + else + val |= (1 << 8); + writel(val, &davinci_syscfg_regs->cfgchip3); +} +#endif +/* + * If there is no MAC address in the environment, then it will be initialized + * (silently) from the value in the EEPROM. + */ +void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) +{ + uint8_t env_enetaddr[6]; + + eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); + if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { + /* + * There is no MAC address in the environment, so we + * initialize it from the value in the EEPROM. + */ + debug("### Setting environment from EEPROM MAC address = " + "\"%pM\"\n", + env_enetaddr); + eth_setenv_enetaddr("ethaddr", rom_enetaddr); + } +} +#endif /* CONFIG_DRIVER_TI_EMAC */ + +#if defined(CONFIG_SOC_DA8XX) +#ifndef CONFIG_USE_IRQ +void irq_init(void) +{ + /* + * Mask all IRQs by clearing the global enable and setting + * the enable clear for all the 90 interrupts. + */ + writel(0, &davinci_aintc_regs->ger); + + writel(0, &davinci_aintc_regs->hier); + + writel(0xffffffff, &davinci_aintc_regs->ecr1); + writel(0xffffffff, &davinci_aintc_regs->ecr2); + writel(0xffffffff, &davinci_aintc_regs->ecr3); +} +#endif + +/* + * Enable PSC for various peripherals. + */ +int da8xx_configure_lpsc_items(const struct lpsc_resource *item, + const int n_items) +{ + int i; + + for (i = 0; i < n_items; i++) + lpsc_on(item[i].lpsc_no); + + return 0; +} +#endif diff --git a/arch/arm/cpu/arm926ejs/davinci/pinmux.c b/arch/arm/cpu/arm926ejs/davinci/pinmux.c new file mode 100644 index 0000000000..ce58f71886 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/pinmux.c @@ -0,0 +1,105 @@ +/* + * DaVinci pinmux functions. + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <asm/arch/davinci_misc.h> + +/* + * Change the setting of a pin multiplexer field. + * + * Takes an array of pinmux settings similar to: + * + * struct pinmux_config uart_pins[] = { + * { &davinci_syscfg_regs->pinmux[8], 2, 7 }, + * { &davinci_syscfg_regs->pinmux[9], 2, 0 } + * }; + * + * Stepping through the array, each pinmux[n] register has the given value + * set in the pin mux field specified. + * + * The number of pins in the array must be passed (ARRAY_SIZE can provide + * this value conveniently). + * + * Returns 0 if all field numbers and values are in the correct range, + * else returns -1. + */ +int davinci_configure_pin_mux(const struct pinmux_config *pins, + const int n_pins) +{ + int i; + + /* check for invalid pinmux values */ + for (i = 0; i < n_pins; i++) { + if (pins[i].field >= PIN_MUX_NUM_FIELDS || + (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0) + return -1; + } + + /* configure the pinmuxes */ + for (i = 0; i < n_pins; i++) { + const int offset = pins[i].field * PIN_MUX_FIELD_SIZE; + const unsigned int value = pins[i].value << offset; + const unsigned int mask = PIN_MUX_FIELD_MASK << offset; + const dv_reg *mux = pins[i].mux; + + writel(value | (readl(mux) & (~mask)), mux); + } + + return 0; +} + +/* + * Configure multiple pinmux resources. + * + * Takes an pinmux_resource array of pinmux_config and pin counts: + * + * const struct pinmux_resource pinmuxes[] = { + * PINMUX_ITEM(uart_pins), + * PINMUX_ITEM(i2c_pins), + * }; + * + * The number of items in the array must be passed (ARRAY_SIZE can provide + * this value conveniently). + * + * Each item entry is configured in the defined order. If configuration + * of any item fails, -1 is returned and none of the following items are + * configured. On success, 0 is returned. + */ +int davinci_configure_pin_mux_items(const struct pinmux_resource *item, + const int n_items) +{ + int i; + + for (i = 0; i < n_items; i++) { + if (davinci_configure_pin_mux(item[i].pins, + item[i].n_pins) != 0) + return -1; + } + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c index 8f38056455..75314b91b3 100644 --- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c +++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * (C) Copyright 2010 diff --git a/arch/arm/cpu/arm926ejs/mx28/Makefile b/arch/arm/cpu/arm926ejs/mx28/Makefile new file mode 100644 index 0000000000..7845310cfe --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx28/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS = clock.o mx28.o iomux.o timer.o + +SRCS := $(START:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mx28/clock.c new file mode 100644 index 0000000000..f698506007 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx28/clock.c @@ -0,0 +1,355 @@ +/* + * Freescale i.MX28 clock setup code + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> + +/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */ +#define PLL_FREQ_KHZ 480000 +#define PLL_FREQ_COEF 18 +/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */ +#define XTAL_FREQ_KHZ 24000 + +#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) +#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000) + +static uint32_t mx28_get_pclk(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + uint32_t clkctrl, clkseq, clkfrac; + uint32_t frac, div; + + clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu); + + /* No support of fractional divider calculation */ + if (clkctrl & + (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) { + return 0; + } + + clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); + + /* XTAL Path */ + if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) { + div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >> + CLKCTRL_CPU_DIV_XTAL_OFFSET; + return XTAL_FREQ_MHZ / div; + } + + /* REF Path */ + clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0); + frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK; + div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; + return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; +} + +static uint32_t mx28_get_hclk(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + uint32_t div; + uint32_t clkctrl; + + clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus); + + /* No support of fractional divider calculation */ + if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN) + return 0; + + div = clkctrl & CLKCTRL_HBUS_DIV_MASK; + return mx28_get_pclk() / div; +} + +static uint32_t mx28_get_emiclk(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + uint32_t frac, div; + uint32_t clkctrl, clkseq, clkfrac; + + clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); + clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi); + + /* XTAL Path */ + if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) { + div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >> + CLKCTRL_EMI_DIV_XTAL_OFFSET; + return XTAL_FREQ_MHZ / div; + } + + clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0); + + /* REF Path */ + frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >> + CLKCTRL_FRAC0_EMIFRAC_OFFSET; + div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK; + return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; +} + +static uint32_t mx28_get_gpmiclk(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + uint32_t frac, div; + uint32_t clkctrl, clkseq, clkfrac; + + clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); + clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi); + + /* XTAL Path */ + if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) { + div = clkctrl & CLKCTRL_GPMI_DIV_MASK; + return XTAL_FREQ_MHZ / div; + } + + clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1); + + /* REF Path */ + frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >> + CLKCTRL_FRAC1_GPMIFRAC_OFFSET; + div = clkctrl & CLKCTRL_GPMI_DIV_MASK; + return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; +} + +/* + * Set IO clock frequency, in kHz + */ +void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t div; + + if (freq == 0) + return; + + if (io > MXC_IOCLK1) + return; + + div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq; + + if (div < 18) + div = 18; + + if (div > 35) + div = 35; + + if (io == MXC_IOCLK0) { + writel(CLKCTRL_FRAC0_CLKGATEIO0, + &clkctrl_regs->hw_clkctrl_frac0_set); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, + CLKCTRL_FRAC0_IO0FRAC_MASK, + div << CLKCTRL_FRAC0_IO0FRAC_OFFSET); + writel(CLKCTRL_FRAC0_CLKGATEIO0, + &clkctrl_regs->hw_clkctrl_frac0_clr); + } else { + writel(CLKCTRL_FRAC0_CLKGATEIO1, + &clkctrl_regs->hw_clkctrl_frac0_set); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, + CLKCTRL_FRAC0_IO1FRAC_MASK, + div << CLKCTRL_FRAC0_IO1FRAC_OFFSET); + writel(CLKCTRL_FRAC0_CLKGATEIO1, + &clkctrl_regs->hw_clkctrl_frac0_clr); + } +} + +/* + * Get IO clock, returns IO clock in kHz + */ +static uint32_t mx28_get_ioclk(enum mxs_ioclock io) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t tmp, ret; + + if (io > MXC_IOCLK1) + return 0; + + tmp = readl(&clkctrl_regs->hw_clkctrl_frac0); + + if (io == MXC_IOCLK0) + ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >> + CLKCTRL_FRAC0_IO0FRAC_OFFSET; + else + ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >> + CLKCTRL_FRAC0_IO1FRAC_OFFSET; + + return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret; +} + +/* + * Configure SSP clock frequency, in kHz + */ +void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t clk, clkreg; + + if (ssp > MXC_SSPCLK3) + return; + + clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + + (ssp * sizeof(struct mx28_register)); + + clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); + while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) + ; + + if (xtal) + clk = XTAL_FREQ_KHZ; + else + clk = mx28_get_ioclk(ssp >> 1); + + if (freq > clk) + return; + + /* Calculate the divider and cap it if necessary */ + clk /= freq; + if (clk > CLKCTRL_SSP_DIV_MASK) + clk = CLKCTRL_SSP_DIV_MASK; + + clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk); + while (readl(clkreg) & CLKCTRL_SSP_BUSY) + ; + + if (xtal) + writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp, + &clkctrl_regs->hw_clkctrl_clkseq_set); + else + writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp, + &clkctrl_regs->hw_clkctrl_clkseq_clr); +} + +/* + * Return SSP frequency, in kHz + */ +static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t clkreg; + uint32_t clk, tmp; + + if (ssp > MXC_SSPCLK3) + return 0; + + tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq); + if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp)) + return XTAL_FREQ_KHZ; + + clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + + (ssp * sizeof(struct mx28_register)); + + tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK; + + if (tmp == 0) + return 0; + + clk = mx28_get_ioclk(ssp >> 1); + + return clk / tmp; +} + +/* + * Set SSP/MMC bus frequency, in kHz) + */ +void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq) +{ + struct mx28_ssp_regs *ssp_regs; + const uint32_t sspclk = mx28_get_sspclk(bus); + uint32_t reg; + uint32_t divide, rate, tgtclk; + + ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000)); + + /* + * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), + * CLOCK_DIVIDE has to be an even value from 2 to 254, and + * CLOCK_RATE could be any integer from 0 to 255. + */ + for (divide = 2; divide < 254; divide += 2) { + rate = sspclk / freq / divide; + if (rate <= 256) + break; + } + + tgtclk = sspclk / divide / rate; + while (tgtclk > freq) { + rate++; + tgtclk = sspclk / divide / rate; + } + if (rate > 256) + rate = 256; + + /* Always set timeout the maximum */ + reg = SSP_TIMING_TIMEOUT_MASK | + (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) | + ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET); + writel(reg, &ssp_regs->hw_ssp_timing); + + debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n", + bus, tgtclk, freq); +} + +uint32_t mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return mx28_get_pclk() * 1000000; + case MXC_GPMI_CLK: + return mx28_get_gpmiclk() * 1000000; + case MXC_AHB_CLK: + case MXC_IPG_CLK: + return mx28_get_hclk() * 1000000; + case MXC_EMI_CLK: + return mx28_get_emiclk(); + case MXC_IO0_CLK: + return mx28_get_ioclk(MXC_IOCLK0); + case MXC_IO1_CLK: + return mx28_get_ioclk(MXC_IOCLK1); + case MXC_SSP0_CLK: + return mx28_get_sspclk(MXC_SSPCLK0); + case MXC_SSP1_CLK: + return mx28_get_sspclk(MXC_SSPCLK1); + case MXC_SSP2_CLK: + return mx28_get_sspclk(MXC_SSPCLK2); + case MXC_SSP3_CLK: + return mx28_get_sspclk(MXC_SSPCLK3); + } + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mx28/iomux.c b/arch/arm/cpu/arm926ejs/mx28/iomux.c new file mode 100644 index 0000000000..9ea411f22a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx28/iomux.c @@ -0,0 +1,109 @@ +/* + * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> + +#if defined(CONFIG_MX23) +#define DRIVE_OFFSET 0x200 +#define PULL_OFFSET 0x400 +#elif defined(CONFIG_MX28) +#define DRIVE_OFFSET 0x300 +#define PULL_OFFSET 0x600 +#else +#error "Please select CONFIG_MX23 or CONFIG_MX28" +#endif + +/* + * configures a single pad in the iomuxer + */ +int mxs_iomux_setup_pad(iomux_cfg_t pad) +{ + u32 reg, ofs, bp, bm; + void *iomux_base = (void *)MXS_PINCTRL_BASE; + struct mx28_register *mxs_reg; + + /* muxsel */ + ofs = 0x100; + ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; + bp = PAD_PIN(pad) % 16 * 2; + bm = 0x3 << bp; + reg = readl(iomux_base + ofs); + reg &= ~bm; + reg |= PAD_MUXSEL(pad) << bp; + writel(reg, iomux_base + ofs); + + /* drive */ + ofs = DRIVE_OFFSET; + ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; + /* mA */ + if (PAD_MA_VALID(pad)) { + bp = PAD_PIN(pad) % 8 * 4; + bm = 0x3 << bp; + reg = readl(iomux_base + ofs); + reg &= ~bm; + reg |= PAD_MA(pad) << bp; + writel(reg, iomux_base + ofs); + } + /* vol */ + if (PAD_VOL_VALID(pad)) { + bp = PAD_PIN(pad) % 8 * 4 + 2; + mxs_reg = (struct mx28_register *)(iomux_base + ofs); + if (PAD_VOL(pad)) + writel(1 << bp, &mxs_reg->reg_set); + else + writel(1 << bp, &mxs_reg->reg_clr); + } + + /* pull */ + if (PAD_PULL_VALID(pad)) { + ofs = PULL_OFFSET; + ofs += PAD_BANK(pad) * 0x10; + bp = PAD_PIN(pad); + mxs_reg = (struct mx28_register *)(iomux_base + ofs); + if (PAD_PULL(pad)) + writel(1 << bp, &mxs_reg->reg_set); + else + writel(1 << bp, &mxs_reg->reg_clr); + } + + return 0; +} + +int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) +{ + const iomux_cfg_t *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + ret = mxs_iomux_setup_pad(*p); + if (ret) + return ret; + p++; + } + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c new file mode 100644 index 0000000000..088c019b7b --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -0,0 +1,221 @@ +/* + * Freescale i.MX28 common code + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* 1 second delay should be plenty of time for block reset. */ +#define RESET_MAX_TIMEOUT 1000000 + +#define MX28_BLOCK_SFTRST (1 << 31) +#define MX28_BLOCK_CLKGATE (1 << 30) + +/* Lowlevel init isn't used on i.MX28, so just have a dummy here */ +inline void lowlevel_init(void) {} + +void reset_cpu(ulong ignored) __attribute__((noreturn)); + +void reset_cpu(ulong ignored) +{ + + struct mx28_rtc_regs *rtc_regs = + (struct mx28_rtc_regs *)MXS_RTC_BASE; + + /* Wait 1 uS before doing the actual watchdog reset */ + writel(1, &rtc_regs->hw_rtc_watchdog); + writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set); + + /* Endless loop, reset will exit from here */ + for (;;) + ; +} + +int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout) +{ + while (--timeout) { + if ((readl(®->reg) & mask) == mask) + break; + udelay(1); + } + + return !timeout; +} + +int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout) +{ + while (--timeout) { + if ((readl(®->reg) & mask) == 0) + break; + udelay(1); + } + + return !timeout; +} + +int mx28_reset_block(struct mx28_register *reg) +{ + /* Clear SFTRST */ + writel(MX28_BLOCK_SFTRST, ®->reg_clr); + + if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) + return 1; + + /* Clear CLKGATE */ + writel(MX28_BLOCK_CLKGATE, ®->reg_clr); + + /* Set SFTRST */ + writel(MX28_BLOCK_SFTRST, ®->reg_set); + + /* Wait for CLKGATE being set */ + if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) + return 1; + + /* Clear SFTRST */ + writel(MX28_BLOCK_SFTRST, ®->reg_clr); + + if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) + return 1; + + /* Clear CLKGATE */ + writel(MX28_BLOCK_CLKGATE, ®->reg_clr); + + if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) + return 1; + + return 0; +} + +void mx28_fixup_vt(uint32_t start_addr) +{ + uint32_t *vt = (uint32_t *)0x20; + int i; + + for (i = 0; i < 8; i++) + vt[i] = start_addr + (4 * i); +} + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + mx28_fixup_vt(gd->relocaddr); + return 0; +} +#endif + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + extern uint32_t _start; + + mx28_fixup_vt((uint32_t)&_start); + + /* + * Enable NAND clock + */ + /* Clear bypass bit */ + writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, + &clkctrl_regs->hw_clkctrl_clkseq_set); + + /* Set GPMI clock to ref_gpmi / 12 */ + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, + CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); + + udelay(1000); + + /* + * Configure GPIO unit + */ + mxs_gpio_init(); + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("Freescale i.MX28 family\n"); + return 0; +} +#endif + +int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000); + printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK)); + printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000); + return 0; +} + +/* + * Initializes on-chip ethernet controllers. + */ +#ifdef CONFIG_CMD_NET +int cpu_eth_init(bd_t *bis) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* Turn on ENET clocks */ + clrbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE); + + /* Set up ENET PLL for 50 MHz */ + /* Power on ENET PLL */ + writel(CLKCTRL_PLL2CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll2ctrl0_set); + + udelay(10); + + /* Gate on ENET PLL */ + writel(CLKCTRL_PLL2CTRL0_CLKGATE, + &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr); + + /* Enable pad output */ + setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN); + + return 0; +} +#endif + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks, + "display clocks", + "" +); diff --git a/arch/arm/cpu/arm926ejs/mx28/timer.c b/arch/arm/cpu/arm926ejs/mx28/timer.c new file mode 100644 index 0000000000..dbc904d087 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx28/timer.c @@ -0,0 +1,141 @@ +/* + * Freescale i.MX28 timer driver + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +/* Maximum fixed count */ +#define TIMER_LOAD_VAL 0xffffffff + +DECLARE_GLOBAL_DATA_PTR; + +#define timestamp (gd->tbl) +#define lastdec (gd->lastinc) + +/* + * This driver uses 1kHz clock source. + */ +#define MX28_INCREMENTER_HZ 1000 + +static inline unsigned long tick_to_time(unsigned long tick) +{ + return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); +} + +static inline unsigned long time_to_tick(unsigned long time) +{ + return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); +} + +/* Calculate how many ticks happen in "us" microseconds */ +static inline unsigned long us_to_tick(unsigned long us) +{ + return (us * MX28_INCREMENTER_HZ) / 1000000; +} + +int timer_init(void) +{ + struct mx28_timrot_regs *timrot_regs = + (struct mx28_timrot_regs *)MXS_TIMROT_BASE; + + /* Reset Timers and Rotary Encoder module */ + mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); + + /* Set fixed_count to 0 */ + writel(0, &timrot_regs->hw_timrot_fixed_count0); + + /* Set UPDATE bit and 1Khz frequency */ + writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD | + TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL, + &timrot_regs->hw_timrot_timctrl0); + + /* Set fixed_count to maximal value */ + writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); + + return 0; +} + +ulong get_timer(ulong base) +{ + struct mx28_timrot_regs *timrot_regs = + (struct mx28_timrot_regs *)MXS_TIMROT_BASE; + + /* Current tick value */ + uint32_t now = readl(&timrot_regs->hw_timrot_running_count0); + + if (lastdec >= now) { + /* + * normal mode (non roll) + * move stamp forward with absolut diff ticks + */ + timestamp += (lastdec - now); + } else { + /* we have rollover of decrementer */ + timestamp += (TIMER_LOAD_VAL - now) + lastdec; + + } + lastdec = now; + + return tick_to_time(timestamp) - base; +} + +/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ +#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0 + +void __udelay(unsigned long usec) +{ + uint32_t old, new, incr; + uint32_t counter = 0; + + old = readl(MX28_HW_DIGCTL_MICROSECONDS); + + while (counter < usec) { + new = readl(MX28_HW_DIGCTL_MICROSECONDS); + + /* Check if the timer wrapped. */ + if (new < old) { + incr = 0xffffffff - old; + incr += new; + } else { + incr = new - old; + } + + /* + * Check if we are close to the maximum time and the counter + * would wrap if incremented. If that's the case, break out + * from the loop as the requested delay time passed. + */ + if (counter + incr < counter) + break; + + counter += incr; + old = new; + } +} diff --git a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c index 0052daba8e..02332eee0e 100644 --- a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c +++ b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c @@ -11,6 +11,7 @@ #include <common.h> #include <command.h> +#include <linux/compiler.h> #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) @@ -151,8 +152,8 @@ int print_cpuinfo (void) u8 die_rev; u32 omap_id; u8 cpu_type; - u32 system_serial_high; - u32 system_serial_low; + __maybe_unused u32 system_serial_high; + __maybe_unused u32 system_serial_low; u32 system_rev = 0; jtag_id = omap_get_jtag_id(); diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 339c5ed6bd..6a09c028e4 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -194,9 +194,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit -#endif /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: @@ -301,10 +299,12 @@ clear_bss: #endif mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: #ifndef CONFIG_SPL_BUILD bl coloured_LED_init @@ -353,7 +353,6 @@ _dynsym_start_ofs: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -372,14 +371,15 @@ cpu_init_crit: orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* * Go setup Memory and board specific bits prior to relocation. */ mov ip, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + mov pc, lr /* back to my caller */ #ifndef CONFIG_SPL_BUILD /* diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 92a5a96800..f97fa3d448 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -29,10 +29,10 @@ START := start.o ifndef CONFIG_SPL_BUILD COBJS += cache_v7.o -COBJS += cpu.o endif -COBJS += syslib.o +COBJS += cpu.o +COBJS += syslib.o SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 091e3e0842..662c4962e6 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -65,6 +65,7 @@ int cleanup_before_linux(void) * dcache_disable() in turn flushes the d-cache and disables MMU */ dcache_disable(); + v7_outer_cache_disable(); /* * After D-cache is flushed and before it is disabled there may diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 0769a645c3..933ce05b76 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -91,7 +91,7 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN) refclk *= 2; - refclk /= pdf + 1; + do_div(refclk, pdf + 1); temp = refclk * mfn_abs; do_div(temp, mfd + 1); ret = refclk * mfi; diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 1dee81f22a..a684611265 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -33,6 +33,13 @@ ifdef CONFIG_OMAP COBJS += gpio.o endif +ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) +COBJS += hwinit-common.o +COBJS += clocks-common.o +COBJS += emif-common.o +SOBJS += lowlevel_init.o +endif + ifdef CONFIG_SPL_BUILD COBJS += spl.o ifdef CONFIG_SPL_NAND_SUPPORT @@ -43,6 +50,12 @@ COBJS += spl_mmc.o endif endif +ifndef CONFIG_SPL_BUILD +ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) +COBJS += mem-common.o +endif +endif + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c new file mode 100644 index 0000000000..1da90a4d93 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -0,0 +1,599 @@ +/* + * + * Clock initialization for OMAP4 + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * Based on previous work by: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * Rajendra Nayak <rnayak@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/omap_common.h> +#include <asm/gpio.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/utils.h> +#include <asm/omap_gpio.h> + +#ifndef CONFIG_SPL_BUILD +/* + * printing to console doesn't work unless + * this code is executed from SPL + */ +#define printf(fmt, args...) +#define puts(s) +#endif + +static inline u32 __get_sys_clk_index(void) +{ + u32 ind; + /* + * For ES1 the ROM code calibration of sys clock is not reliable + * due to hw issue. So, use hard-coded value. If this value is not + * correct for any board over-ride this function in board file + * From ES2.0 onwards you will get this information from + * CM_SYS_CLKSEL + */ + if (omap_revision() == OMAP4430_ES1_0) + ind = OMAP_SYS_CLK_IND_38_4_MHZ; + else { + /* SYS_CLKSEL - 1 to match the dpll param array indices */ + ind = (readl(&prcm->cm_sys_clksel) & + CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; + } + return ind; +} + +u32 get_sys_clk_index(void) + __attribute__ ((weak, alias("__get_sys_clk_index"))); + +u32 get_sys_clk_freq(void) +{ + u8 index = get_sys_clk_index(); + return sys_clk_array[index]; +} + +static inline void do_bypass_dpll(u32 *const base) +{ + struct dpll_regs *dpll_regs = (struct dpll_regs *)base; + + clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_FAST_RELOCK_BYPASS << + CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_bypass(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, + LDELAY)) { + printf("Bypassing DPLL failed %p\n", base); + } +} + +static inline void do_lock_dpll(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_lock(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, + &dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("DPLL locking failed for %p\n", base); + hang(); + } +} + +inline u32 check_for_lock(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK; + + return lock; +} + +static void do_setup_dpll(u32 *const base, const struct dpll_params *params, + u8 lock, char *dpll) +{ + u32 temp, M, N; + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + temp = readl(&dpll_regs->cm_clksel_dpll); + + if (check_for_lock(base)) { + /* + * The Dpll has already been locked by rom code using CH. + * Check if M,N are matching with Ideal nominal opp values. + * If matches, skip the rest otherwise relock. + */ + M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT; + N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT; + if ((M != (params->m)) || (N != (params->n))) { + debug("\n %s Dpll locked, but not for ideal M = %d," + "N = %d values, current values are M = %d," + "N= %d" , dpll, params->m, params->n, + M, N); + } else { + /* Dpll locked with ideal values for nominal opps. */ + debug("\n %s Dpll already locked with ideal" + "nominal opp values", dpll); + goto setup_post_dividers; + } + } + + bypass_dpll(base); + + /* Set M & N */ + temp &= ~CM_CLKSEL_DPLL_M_MASK; + temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; + + temp &= ~CM_CLKSEL_DPLL_N_MASK; + temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; + + writel(temp, &dpll_regs->cm_clksel_dpll); + + /* Lock */ + if (lock) + do_lock_dpll(base); + +setup_post_dividers: + setup_post_dividers(base, params); + + /* Wait till the DPLL locks */ + if (lock) + wait_for_lock(base); +} + +u32 omap_ddr_clk(void) +{ + u32 ddr_clk, sys_clk_khz, omap_rev, divider; + const struct dpll_params *core_dpll_params; + + omap_rev = omap_revision(); + sys_clk_khz = get_sys_clk_freq() / 1000; + + core_dpll_params = get_core_dpll_params(); + + debug("sys_clk %d\n ", sys_clk_khz * 1000); + + /* Find Core DPLL locked frequency first */ + ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / + (core_dpll_params->n + 1); + + if (omap_rev < OMAP5430_ES1_0) { + /* + * DDR frequency is PHY_ROOT_CLK/2 + * PHY_ROOT_CLK = Fdpll/2/M2 + */ + divider = 4; + } else { + /* + * DDR frequency is PHY_ROOT_CLK + * PHY_ROOT_CLK = Fdpll/2/M2 + */ + divider = 2; + } + + ddr_clk = ddr_clk / divider / core_dpll_params->m2; + ddr_clk *= 1000; /* convert to Hz */ + debug("ddr_clk %d\n ", ddr_clk); + + return ddr_clk; +} + +/* + * Lock MPU dpll + * + * Resulting MPU frequencies: + * 4430 ES1.0 : 600 MHz + * 4430 ES2.x : 792 MHz (OPP Turbo) + * 4460 : 920 MHz (OPP Turbo) - DCC disabled + */ +void configure_mpu_dpll(void) +{ + const struct dpll_params *params; + struct dpll_regs *mpu_dpll_regs; + u32 omap_rev; + omap_rev = omap_revision(); + + /* + * DCC and clock divider settings for 4460. + * DCC is required, if more than a certain frequency is required. + * For, 4460 > 1GHZ. + * 5430 > 1.4GHZ. + */ + if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) { + mpu_dpll_regs = + (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu; + bypass_dpll(&prcm->cm_clkmode_dpll_mpu); + clrbits_le32(&prcm->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); + setbits_le32(&prcm->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); + clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, + CM_CLKSEL_DCC_EN_MASK); + } + + params = get_mpu_dpll_params(); + + do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); + debug("MPU DPLL locked\n"); +} + +static void setup_dplls(void) +{ + u32 temp; + const struct dpll_params *params; + + debug("setup_dplls\n"); + + /* CORE dpll */ + params = get_core_dpll_params(); /* default - safest */ + /* + * Do not lock the core DPLL now. Just set it up. + * Core DPLL will be locked after setting up EMIF + * using the FREQ_UPDATE method(freq_update_core()) + */ + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, + "core"); + /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ + temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | + (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | + (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); + writel(temp, &prcm->cm_clksel_core); + debug("Core DPLL configured\n"); + + /* lock PER dpll */ + params = get_per_dpll_params(); + do_setup_dpll(&prcm->cm_clkmode_dpll_per, + params, DPLL_LOCK, "per"); + debug("PER DPLL locked\n"); + + /* MPU dpll */ + configure_mpu_dpll(); +} + +#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL +static void setup_non_essential_dplls(void) +{ + u32 sys_clk_khz, abe_ref_clk; + u32 sd_div, num, den; + const struct dpll_params *params; + + sys_clk_khz = get_sys_clk_freq() / 1000; + + /* IVA */ + clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, + CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); + + params = get_iva_dpll_params(); + do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); + + /* + * USB: + * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction + * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) + * - where CLKINP is sys_clk in MHz + * Use CLKINP in KHz and adjust the denominator accordingly so + * that we have enough accuracy and at the same time no overflow + */ + params = get_usb_dpll_params(); + num = params->m * sys_clk_khz; + den = (params->n + 1) * 250 * 1000; + num += den - 1; + sd_div = num / den; + clrsetbits_le32(&prcm->cm_clksel_dpll_usb, + CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, + sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); + + /* Now setup the dpll with the regular function */ + do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); + + /* Configure ABE dpll */ + params = get_abe_dpll_params(); +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; +#else + abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; + /* + * We need to enable some additional options to achieve + * 196.608MHz from 32768 Hz + */ + setbits_le32(&prcm->cm_clkmode_dpll_abe, + CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| + CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| + CM_CLKMODE_DPLL_LPMODE_EN_MASK| + CM_CLKMODE_DPLL_REGM4XEN_MASK); + /* Spend 4 REFCLK cycles at each stage */ + clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, + CM_CLKMODE_DPLL_RAMP_RATE_MASK, + 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); +#endif + + /* Select the right reference clk */ + clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, + CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, + abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); + /* Lock the dpll */ + do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); +} +#endif + +void do_scale_tps62361(u32 reg, u32 volt_mv) +{ + u32 temp, step; + + step = volt_mv - TPS62361_BASE_VOLT_MV; + step /= 10; + + temp = TPS62361_I2C_SLAVE_ADDR | + (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | + (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) | + PRM_VC_VAL_BYPASS_VALID_BIT; + debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step); + + writel(temp, &prcm->prm_vc_val_bypass); + if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, + &prcm->prm_vc_val_bypass, LDELAY)) { + puts("Scaling voltage failed for vdd_mpu from TPS\n"); + } +} + +void do_scale_vcore(u32 vcore_reg, u32 volt_mv) +{ + u32 temp, offset_code; + u32 step = 12660; /* 12.66 mV represented in uV */ + u32 offset = volt_mv; + + /* convert to uV for better accuracy in the calculations */ + offset *= 1000; + + if (omap_revision() == OMAP4430_ES1_0) + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; + else + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; + + offset_code = (offset + step - 1) / step; + /* The code starts at 1 not 0 */ + offset_code++; + + debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, + offset_code); + + temp = SMPS_I2C_SLAVE_ADDR | + (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | + (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) | + PRM_VC_VAL_BYPASS_VALID_BIT; + writel(temp, &prcm->prm_vc_val_bypass); + if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, + &prcm->prm_vc_val_bypass, LDELAY)) { + printf("Scaling voltage failed for 0x%x\n", vcore_reg); + } +} + +static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Enable clock domain - %p\n", clkctrl_reg); +} + +static inline void wait_for_clk_enable(u32 *clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + u32 bound = LDELAY; + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock enable failed for 0x%p idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} + +static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, + u32 wait_for_enable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Enable clock module - %p\n", clkctrl_addr); + if (wait_for_enable) + wait_for_clk_enable(clkctrl_addr); +} + +void freq_update_core(void) +{ + u32 freq_config1 = 0; + const struct dpll_params *core_dpll_params; + + core_dpll_params = get_core_dpll_params(); + /* Put EMIF clock domain in sw wakeup mode */ + enable_clock_domain(&prcm->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); + wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + + freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | + SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; + + freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & + SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; + + freq_config1 |= (core_dpll_params->m2 << + SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & + SHADOW_FREQ_CONFIG1_M2_DIV_MASK; + + writel(freq_config1, &prcm->cm_shadow_freq_config1); + if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, + &prcm->cm_shadow_freq_config1, LDELAY)) { + puts("FREQ UPDATE procedure failed!!"); + hang(); + } + + /* Put EMIF clock domain back in hw auto mode */ + enable_clock_domain(&prcm->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); + wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); +} + +void bypass_dpll(u32 *const base) +{ + do_bypass_dpll(base); + wait_for_bypass(base); +} + +void lock_dpll(u32 *const base) +{ + do_lock_dpll(base); + wait_for_lock(base); +} + +void setup_clocks_for_console(void) +{ + /* Do not add any spl_debug prints in this function */ + clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + /* Enable all UARTs - console will be on one of them */ + clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO << + CD_CLKCTRL_CLKTRCTRL_SHIFT); +} + +void setup_sri2c(void) +{ + u32 sys_clk_khz, cycles_hi, cycles_low, temp; + + sys_clk_khz = get_sys_clk_freq() / 1000; + + /* + * Setup the dedicated I2C controller for Voltage Control + * I2C clk - high period 40% low period 60% + */ + cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; + cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; + /* values to be set in register - less by 5 & 7 respectively */ + cycles_hi -= 5; + cycles_low -= 7; + temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | + (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); + writel(temp, &prcm->prm_vc_cfg_i2c_clk); + + /* Disable high speed mode and all advanced features */ + writel(0x0, &prcm->prm_vc_cfg_i2c_mode); +} + +void do_enable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_hw_auto, + u32 *const *clk_modules_explicit_en, + u8 wait_for_enable) +{ + u32 i, max = 100; + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains[i]; i++) { + enable_clock_domain(clk_domains[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in HW_AUTO */ + for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) { + enable_clock_module(clk_modules_hw_auto[i], + MODULE_CLKCTRL_MODULEMODE_HW_AUTO, + wait_for_enable); + }; + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { + enable_clock_module(clk_modules_explicit_en[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; + + /* Put the clock domains in HW_AUTO mode now */ + for (i = 0; (i < max) && clk_domains[i]; i++) { + enable_clock_domain(clk_domains[i], + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + } +} + +void prcm_init(void) +{ + switch (omap_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + enable_basic_clocks(); + scale_vcores(); + setup_dplls(); +#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL + setup_non_essential_dplls(); + enable_non_essential_clocks(); +#endif + break; + default: + break; + } + + if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) + enable_basic_uboot_clocks(); +} diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c new file mode 100644 index 0000000000..62678ff5d3 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -0,0 +1,1140 @@ +/* + * EMIF programming + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/emif.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/omap_common.h> +#include <asm/utils.h> + +inline u32 emif_num(u32 base) +{ + if (base == EMIF1_BASE) + return 1; + else if (base == EMIF2_BASE) + return 2; + else + return 0; +} + + +static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) +{ + u32 mr; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + if (omap_revision() == OMAP4430_ES2_0) + mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); + else + mr = readl(&emif->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), + cs, mr_addr, mr); + return mr; +} + +static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif->emif_lpddr2_mode_reg_data); +} + +void emif_reset_phy(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 iodft; + + iodft = readl(&emif->emif_iodft_tlgc); + iodft |= EMIF_REG_RESET_PHY_MASK; + writel(iodft, &emif->emif_iodft_tlgc); +} + +static void do_lpddr2_init(u32 base, u32 cs) +{ + u32 mr_addr; + + /* Wait till device auto initialization is complete */ + while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT); + /* + * tZQINIT = 1 us + * Enough loops assuming a maximum of 2GHz + */ + sdelay(2000); + set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); + set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); + /* + * Enable refresh along with writing MR2 + * Encoding of RL in MR2 is (RL - 2) + */ + mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; + set_mr(base, cs, mr_addr, RL_FINAL - 2); +} + +static void lpddr2_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* Not NVM */ + clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); + + /* + * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM + * when EMIF_SDRAM_CONFIG register is written + */ + setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + + /* + * Set the SDRAM_CONFIG and PHY_CTRL for the + * un-locked frequency & default RL + */ + writel(regs->sdram_config_init, &emif->emif_sdram_config); + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + + do_lpddr2_init(base, CS0); + if (regs->sdram_config & EMIF_REG_EBANK_MASK) + do_lpddr2_init(base, CS1); + + writel(regs->sdram_config, &emif->emif_sdram_config); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + + /* Enable refresh now */ + clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + +} + +void emif_update_timings(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); + if (omap_revision() == OMAP4430_ES1_0) { + /* ES1 bug EMIF should be in force idle during freq_update */ + writel(0, &emif->emif_pwr_mgmt_ctrl); + } else { + writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); + writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); + } + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); + writel(regs->zq_config, &emif->emif_zq_config); + writel(regs->temp_alert_config, &emif->emif_temp_alert_config); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + + if (omap_revision() == OMAP5430_ES1_0) { + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, + &emif->emif_l3_config); + } else if (omap_revision() >= OMAP4460_ES1_0) { + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, + &emif->emif_l3_config); + } else { + writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, + &emif->emif_l3_config); + } +} + +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) + +/* + * Organization and refresh requirements for LPDDR2 devices of different + * types and densities. Derived from JESD209-2 section 2.4 + */ +const struct lpddr2_addressing addressing_table[] = { + /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ + {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ + {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ + {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ + {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ + {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ + {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ + {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ + {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ + {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ + {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ +}; + +static const u32 lpddr2_density_2_size_in_mbytes[] = { + 8, /* 64Mb */ + 16, /* 128Mb */ + 32, /* 256Mb */ + 64, /* 512Mb */ + 128, /* 1Gb */ + 256, /* 2Gb */ + 512, /* 4Gb */ + 1024, /* 8Gb */ + 2048, /* 16Gb */ + 4096 /* 32Gb */ +}; + +/* + * Calculate the period of DDR clock from frequency value and set the + * denominator and numerator in global variables for easy access later + */ +static void set_ddr_clk_period(u32 freq) +{ + /* + * period = 1/freq + * period_in_ns = 10^9/freq + */ + *T_num = 1000000000; + *T_den = freq; + cancel_out(T_num, T_den, 200); + +} + +/* + * Convert time in nano seconds to number of cycles of DDR clock + */ +static inline u32 ns_2_cycles(u32 ns) +{ + return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); +} + +/* + * ns_2_cycles with the difference that the time passed is 2 times the actual + * value(to avoid fractions). The cycles returned is for the original value of + * the timing parameter + */ +static inline u32 ns_x2_2_cycles(u32 ns) +{ + return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); +} + +/* + * Find addressing table index based on the device's type(S2 or S4) and + * density + */ +s8 addressing_table_index(u8 type, u8 density, u8 width) +{ + u8 index; + if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) + return -1; + + /* + * Look at the way ADDR_TABLE_INDEX* values have been defined + * in emif.h compared to LPDDR2_DENSITY_* values + * The table is layed out in the increasing order of density + * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed + * at the end + */ + if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) + index = ADDR_TABLE_INDEX1GS2; + else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) + index = ADDR_TABLE_INDEX2GS2; + else + index = density; + + debug("emif: addressing table index %d\n", index); + + return index; +} + +/* + * Find the the right timing table from the array of timing + * tables of the device using DDR clock frequency + */ +static const struct lpddr2_ac_timings *get_timings_table(const struct + lpddr2_ac_timings const *const *device_timings, + u32 freq) +{ + u32 i, temp, freq_nearest; + const struct lpddr2_ac_timings *timings = 0; + + emif_assert(freq <= MAX_LPDDR2_FREQ); + emif_assert(device_timings); + + /* + * Start with the maximum allowed frequency - that is always safe + */ + freq_nearest = MAX_LPDDR2_FREQ; + /* + * Find the timings table that has the max frequency value: + * i. Above or equal to the DDR frequency - safe + * ii. The lowest that satisfies condition (i) - optimal + */ + for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { + temp = device_timings[i]->max_freq; + if ((temp >= freq) && (temp <= freq_nearest)) { + freq_nearest = temp; + timings = device_timings[i]; + } + } + debug("emif: timings table: %d\n", freq_nearest); + return timings; +} + +/* + * Finds the value of emif_sdram_config_reg + * All parameters are programmed based on the device on CS0. + * If there is a device on CS1, it will be same as that on CS0 or + * it will be NVM. We don't support NVM yet. + * If cs1_device pointer is NULL it is assumed that there is no device + * on CS1 + */ +static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, + const struct lpddr2_device_details *cs1_device, + const struct lpddr2_addressing *addressing, + u8 RL) +{ + u32 config_reg = 0; + + config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; + config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << + EMIF_REG_IBANK_POS_SHIFT; + + config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; + + config_reg |= RL << EMIF_REG_CL_SHIFT; + + config_reg |= addressing->row_sz[cs0_device->io_width] << + EMIF_REG_ROWSIZE_SHIFT; + + config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; + + config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << + EMIF_REG_EBANK_SHIFT; + + config_reg |= addressing->col_sz[cs0_device->io_width] << + EMIF_REG_PAGESIZE_SHIFT; + + return config_reg; +} + +static u32 get_sdram_ref_ctrl(u32 freq, + const struct lpddr2_addressing *addressing) +{ + u32 ref_ctrl = 0, val = 0, freq_khz; + freq_khz = freq / 1000; + /* + * refresh rate to be set is 'tREFI * freq in MHz + * division by 10000 to account for khz and x10 in t_REFI_us_x10 + */ + val = addressing->t_REFI_us_x10 * freq_khz / 10000; + ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT; + + return ref_ctrl; +} + +static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing) +{ + u32 tim1 = 0, val = 0; + val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; + tim1 |= val << EMIF_REG_T_WTR_SHIFT; + + if (addressing->num_banks == BANKS8) + val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / + (4 * (*T_num)) - 1; + else + val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; + + tim1 |= val << EMIF_REG_T_RRD_SHIFT; + + val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; + tim1 |= val << EMIF_REG_T_RC_SHIFT; + + val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; + tim1 |= val << EMIF_REG_T_RAS_SHIFT; + + val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; + tim1 |= val << EMIF_REG_T_WR_SHIFT; + + val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; + tim1 |= val << EMIF_REG_T_RCD_SHIFT; + + val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; + tim1 |= val << EMIF_REG_T_RP_SHIFT; + + return tim1; +} + +static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, + const struct lpddr2_min_tck *min_tck) +{ + u32 tim2 = 0, val = 0; + val = max(min_tck->tCKE, timings->tCKE) - 1; + tim2 |= val << EMIF_REG_T_CKE_SHIFT; + + val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; + tim2 |= val << EMIF_REG_T_RTP_SHIFT; + + /* + * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the + * same value + */ + val = ns_2_cycles(timings->tXSR) - 1; + tim2 |= val << EMIF_REG_T_XSRD_SHIFT; + tim2 |= val << EMIF_REG_T_XSNR_SHIFT; + + val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; + tim2 |= val << EMIF_REG_T_XP_SHIFT; + + return tim2; +} + +static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing) +{ + u32 tim3 = 0, val = 0; + val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); + tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT; + + val = ns_2_cycles(timings->tRFCab) - 1; + tim3 |= val << EMIF_REG_T_RFC_SHIFT; + + val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; + tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT; + + val = ns_2_cycles(timings->tZQCS) - 1; + tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT; + + val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; + tim3 |= val << EMIF_REG_T_CKESR_SHIFT; + + return tim3; +} + +static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, + const struct lpddr2_addressing *addressing, + u8 volt_ramp) +{ + u32 zq = 0, val = 0; + if (volt_ramp) + val = + EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / + addressing->t_REFI_us_x10; + else + val = + EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / + addressing->t_REFI_us_x10; + zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; + + zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; + + zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; + + zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; + + /* + * Assuming that two chipselects have a single calibration resistor + * If there are indeed two calibration resistors, then this flag should + * be enabled to take advantage of dual calibration feature. + * This data should ideally come from board files. But considering + * that none of the boards today have calibration resistors per CS, + * it would be an unnecessary overhead. + */ + zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; + + zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; + + zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; + + return zq; +} + +static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, + const struct lpddr2_addressing *addressing, + u8 is_derated) +{ + u32 alert = 0, interval; + interval = + TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; + if (is_derated) + interval *= 4; + alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT; + + alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT; + + alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT; + + alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT; + + alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT; + + alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT; + + return alert; +} + +static u32 get_read_idle_ctrl_reg(u8 volt_ramp) +{ + u32 idle = 0, val = 0; + if (volt_ramp) + val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; + else + /*Maximum value in normal conditions - suggested by hw team */ + val = 0x1FF; + idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT; + + idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT; + + return idle; +} + +static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) +{ + u32 phy = 0, val = 0; + + phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; + + if (freq <= 100000000) + val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; + else if (freq <= 200000000) + val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; + else + val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; + phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT; + + /* Other fields are constant magic values. Hardcode them together */ + phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << + EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; + + return phy; +} + +static u32 get_emif_mem_size(struct emif_device_details *devices) +{ + u32 size_mbytes = 0, temp; + + if (!devices) + return 0; + + if (devices->cs0_device_details) { + temp = devices->cs0_device_details->density; + size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; + } + + if (devices->cs1_device_details) { + temp = devices->cs1_device_details->density; + size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; + } + /* convert to bytes */ + return size_mbytes << 20; +} + +/* Gets the encoding corresponding to a given DMM section size */ +u32 get_dmm_section_size_map(u32 section_size) +{ + /* + * Section size mapping: + * 0x0: 16-MiB section + * 0x1: 32-MiB section + * 0x2: 64-MiB section + * 0x3: 128-MiB section + * 0x4: 256-MiB section + * 0x5: 512-MiB section + * 0x6: 1-GiB section + * 0x7: 2-GiB section + */ + section_size >>= 24; /* divide by 16 MB */ + return log_2_n_round_down(section_size); +} + +static void emif_calculate_regs( + const struct emif_device_details *emif_dev_details, + u32 freq, struct emif_regs *regs) +{ + u32 temp, sys_freq; + const struct lpddr2_addressing *addressing; + const struct lpddr2_ac_timings *timings; + const struct lpddr2_min_tck *min_tck; + const struct lpddr2_device_details *cs0_dev_details = + emif_dev_details->cs0_device_details; + const struct lpddr2_device_details *cs1_dev_details = + emif_dev_details->cs1_device_details; + const struct lpddr2_device_timings *cs0_dev_timings = + emif_dev_details->cs0_device_timings; + + emif_assert(emif_dev_details); + emif_assert(regs); + /* + * You can not have a device on CS1 without one on CS0 + * So configuring EMIF without a device on CS0 doesn't + * make sense + */ + emif_assert(cs0_dev_details); + emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); + /* + * If there is a device on CS1 it should be same type as CS0 + * (or NVM. But NVM is not supported in this driver yet) + */ + emif_assert((cs1_dev_details == NULL) || + (cs1_dev_details->type == LPDDR2_TYPE_NVM) || + (cs0_dev_details->type == cs1_dev_details->type)); + emif_assert(freq <= MAX_LPDDR2_FREQ); + + set_ddr_clk_period(freq); + + /* + * The device on CS0 is used for all timing calculations + * There is only one set of registers for timings per EMIF. So, if the + * second CS(CS1) has a device, it should have the same timings as the + * device on CS0 + */ + timings = get_timings_table(cs0_dev_timings->ac_timings, freq); + emif_assert(timings); + min_tck = cs0_dev_timings->min_tck; + + temp = addressing_table_index(cs0_dev_details->type, + cs0_dev_details->density, + cs0_dev_details->io_width); + + emif_assert((temp >= 0)); + addressing = &(addressing_table[temp]); + emif_assert(addressing); + + sys_freq = get_sys_clk_freq(); + + regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, + cs1_dev_details, + addressing, RL_BOOT); + + regs->sdram_config = get_sdram_config_reg(cs0_dev_details, + cs1_dev_details, + addressing, RL_FINAL); + + regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); + + regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); + + regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); + + regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); + + regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); + + regs->temp_alert_config = + get_temp_alert_config(cs1_dev_details, addressing, 0); + + regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, + LPDDR2_VOLTAGE_STABLE); + + regs->emif_ddr_phy_ctlr_1_init = + get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); + + regs->emif_ddr_phy_ctlr_1 = + get_ddr_phy_ctrl_1(freq, RL_FINAL); + + regs->freq = freq; + + print_timing_reg(regs->sdram_config_init); + print_timing_reg(regs->sdram_config); + print_timing_reg(regs->ref_ctrl); + print_timing_reg(regs->sdram_tim1); + print_timing_reg(regs->sdram_tim2); + print_timing_reg(regs->sdram_tim3); + print_timing_reg(regs->read_idle_ctrl); + print_timing_reg(regs->temp_alert_config); + print_timing_reg(regs->zq_config); + print_timing_reg(regs->emif_ddr_phy_ctlr_1); + print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); +} +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + +#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +const char *get_lpddr2_type(u8 type_id) +{ + switch (type_id) { + case LPDDR2_TYPE_S4: + return "LPDDR2-S4"; + case LPDDR2_TYPE_S2: + return "LPDDR2-S2"; + default: + return NULL; + } +} + +const char *get_lpddr2_io_width(u8 width_id) +{ + switch (width_id) { + case LPDDR2_IO_WIDTH_8: + return "x8"; + case LPDDR2_IO_WIDTH_16: + return "x16"; + case LPDDR2_IO_WIDTH_32: + return "x32"; + default: + return NULL; + } +} + +const char *get_lpddr2_manufacturer(u32 manufacturer) +{ + switch (manufacturer) { + case LPDDR2_MANUFACTURER_SAMSUNG: + return "Samsung"; + case LPDDR2_MANUFACTURER_QIMONDA: + return "Qimonda"; + case LPDDR2_MANUFACTURER_ELPIDA: + return "Elpida"; + case LPDDR2_MANUFACTURER_ETRON: + return "Etron"; + case LPDDR2_MANUFACTURER_NANYA: + return "Nanya"; + case LPDDR2_MANUFACTURER_HYNIX: + return "Hynix"; + case LPDDR2_MANUFACTURER_MOSEL: + return "Mosel"; + case LPDDR2_MANUFACTURER_WINBOND: + return "Winbond"; + case LPDDR2_MANUFACTURER_ESMT: + return "ESMT"; + case LPDDR2_MANUFACTURER_SPANSION: + return "Spansion"; + case LPDDR2_MANUFACTURER_SST: + return "SST"; + case LPDDR2_MANUFACTURER_ZMOS: + return "ZMOS"; + case LPDDR2_MANUFACTURER_INTEL: + return "Intel"; + case LPDDR2_MANUFACTURER_NUMONYX: + return "Numonyx"; + case LPDDR2_MANUFACTURER_MICRON: + return "Micron"; + default: + return NULL; + } +} + +static void display_sdram_details(u32 emif_nr, u32 cs, + struct lpddr2_device_details *device) +{ + const char *mfg_str; + const char *type_str; + char density_str[10]; + u32 density; + + debug("EMIF%d CS%d\t", emif_nr, cs); + + if (!device) { + debug("None\n"); + return; + } + + mfg_str = get_lpddr2_manufacturer(device->manufacturer); + type_str = get_lpddr2_type(device->type); + + density = lpddr2_density_2_size_in_mbytes[device->density]; + if ((density / 1024 * 1024) == density) { + density /= 1024; + sprintf(density_str, "%d GB", density); + } else + sprintf(density_str, "%d MB", density); + if (mfg_str && type_str) + debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); +} + +static u8 is_lpddr2_sdram_present(u32 base, u32 cs, + struct lpddr2_device_details *lpddr2_device) +{ + u32 mr = 0, temp; + + mr = get_mr(base, cs, LPDDR2_MR0); + if (mr > 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; + if (temp) { + /* Not SDRAM */ + return 0; + } + temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; + + if (temp) { + /* DNV supported - But DNV is only supported for NVM */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR4); + if (mr > 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR5); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + if (!get_lpddr2_manufacturer(mr)) { + /* Manufacturer not identified */ + return 0; + } + lpddr2_device->manufacturer = mr; + + mr = get_mr(base, cs, LPDDR2_MR6); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR7); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR8); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; + if (!get_lpddr2_type(temp)) { + /* Not SDRAM */ + return 0; + } + lpddr2_device->type = temp; + + temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; + if (temp > LPDDR2_DENSITY_32Gb) { + /* Density not supported */ + return 0; + } + lpddr2_device->density = temp; + + temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; + if (!get_lpddr2_io_width(temp)) { + /* IO width unsupported value */ + return 0; + } + lpddr2_device->io_width = temp; + + /* + * If all the above tests pass we should + * have a device on this chip-select + */ + return 1; +} + +struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details) +{ + u32 phy; + u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE; + + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + if (!lpddr2_dev_details) + return NULL; + + /* Do the minimum init for mode register accesses */ + if (!running_from_sdram()) { + phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); + writel(phy, &emif->emif_ddr_phy_ctrl_1); + } + + if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) + return NULL; + + display_sdram_details(emif_num(base), cs, lpddr2_dev_details); + + return lpddr2_dev_details; +} +#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ + +static void do_sdram_init(u32 base) +{ + const struct emif_regs *regs; + u32 in_sdram, emif_nr; + + debug(">>do_sdram_init() %x\n", base); + + in_sdram = running_from_sdram(); + emif_nr = (base == EMIF1_BASE) ? 1 : 2; + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + emif_get_reg_dump(emif_nr, ®s); + if (!regs) { + debug("EMIF: reg dump not provided\n"); + return; + } +#else + /* + * The user has not provided the register values. We need to + * calculate it based on the timings and the DDR frequency + */ + struct emif_device_details dev_details; + struct emif_regs calculated_regs; + + /* + * Get device details: + * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set + * - Obtained from user otherwise + */ + struct lpddr2_device_details cs0_dev_details, cs1_dev_details; + emif_reset_phy(base); + dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, + &cs0_dev_details); + dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, + &cs1_dev_details); + emif_reset_phy(base); + + /* Return if no devices on this EMIF */ + if (!dev_details.cs0_device_details && + !dev_details.cs1_device_details) { + emif_sizes[emif_nr - 1] = 0; + return; + } + + if (!in_sdram) + emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details); + + /* + * Get device timings: + * - Default timings specified by JESD209-2 if + * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set + * - Obtained from user otherwise + */ + emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, + &dev_details.cs1_device_timings); + + /* Calculate the register values */ + emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs); + regs = &calculated_regs; +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + + /* + * Initializing the LPDDR2 device can not happen from SDRAM. + * Changing the timing registers in EMIF can happen(going from one + * OPP to another) + */ + if (!in_sdram) + lpddr2_init(base, regs); + + /* Write to the shadow registers */ + emif_update_timings(base, regs); + + debug("<<do_sdram_init() %x\n", base); +} + +void emif_post_init_config(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 omap_rev = omap_revision(); + + if (omap_rev == OMAP5430_ES1_0) + return; + + /* reset phy on ES2.0 */ + if (omap_rev == OMAP4430_ES2_0) + emif_reset_phy(base); + + /* Put EMIF back in smart idle on ES1.0 */ + if (omap_rev == OMAP4430_ES1_0) + writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); +} + +void dmm_init(u32 base) +{ + const struct dmm_lisa_map_regs *lisa_map_regs; + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + emif_get_dmm_regs(&lisa_map_regs); +#else + u32 emif1_size, emif2_size, mapped_size, section_map = 0; + u32 section_cnt, sys_addr; + struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; + + mapped_size = 0; + section_cnt = 3; + sys_addr = CONFIG_SYS_SDRAM_BASE; + emif1_size = emif_sizes[0]; + emif2_size = emif_sizes[1]; + debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); + + if (!emif1_size && !emif2_size) + return; + + /* symmetric interleaved section */ + if (emif1_size && emif2_size) { + mapped_size = min(emif1_size, emif2_size); + section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; + section_map |= 0 << EMIF_SDRC_ADDR_SHIFT; + /* only MSB */ + section_map |= (sys_addr >> 24) << + EMIF_SYS_ADDR_SHIFT; + section_map |= get_dmm_section_size_map(mapped_size * 2) + << EMIF_SYS_SIZE_SHIFT; + lis_map_regs_calculated.dmm_lisa_map_3 = section_map; + emif1_size -= mapped_size; + emif2_size -= mapped_size; + sys_addr += (mapped_size * 2); + section_cnt--; + } + + /* + * Single EMIF section(we can have a maximum of 1 single EMIF + * section- either EMIF1 or EMIF2 or none, but not both) + */ + if (emif1_size) { + section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; + section_map |= get_dmm_section_size_map(emif1_size) + << EMIF_SYS_SIZE_SHIFT; + /* only MSB */ + section_map |= (mapped_size >> 24) << + EMIF_SDRC_ADDR_SHIFT; + /* only MSB */ + section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT; + section_cnt--; + } + if (emif2_size) { + section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; + section_map |= get_dmm_section_size_map(emif2_size) << + EMIF_SYS_SIZE_SHIFT; + /* only MSB */ + section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT; + /* only MSB */ + section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT; + section_cnt--; + } + + if (section_cnt == 2) { + /* Only 1 section - either symmetric or single EMIF */ + lis_map_regs_calculated.dmm_lisa_map_3 = section_map; + lis_map_regs_calculated.dmm_lisa_map_2 = 0; + lis_map_regs_calculated.dmm_lisa_map_1 = 0; + } else { + /* 2 sections - 1 symmetric, 1 single EMIF */ + lis_map_regs_calculated.dmm_lisa_map_2 = section_map; + lis_map_regs_calculated.dmm_lisa_map_1 = 0; + } + + /* TRAP for invalid TILER mappings in section 0 */ + lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; + + lisa_map_regs = &lis_map_regs_calculated; +#endif + struct dmm_lisa_map_regs *hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)base; + + writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); + + writel(lisa_map_regs->dmm_lisa_map_3, + &hw_lisa_map_regs->dmm_lisa_map_3); + writel(lisa_map_regs->dmm_lisa_map_2, + &hw_lisa_map_regs->dmm_lisa_map_2); + writel(lisa_map_regs->dmm_lisa_map_1, + &hw_lisa_map_regs->dmm_lisa_map_1); + writel(lisa_map_regs->dmm_lisa_map_0, + &hw_lisa_map_regs->dmm_lisa_map_0); + + if (omap_revision() >= OMAP4460_ES1_0) { + hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)MA_BASE; + + writel(lisa_map_regs->dmm_lisa_map_3, + &hw_lisa_map_regs->dmm_lisa_map_3); + writel(lisa_map_regs->dmm_lisa_map_2, + &hw_lisa_map_regs->dmm_lisa_map_2); + writel(lisa_map_regs->dmm_lisa_map_1, + &hw_lisa_map_regs->dmm_lisa_map_1); + writel(lisa_map_regs->dmm_lisa_map_0, + &hw_lisa_map_regs->dmm_lisa_map_0); + } +} + +/* + * SDRAM initialization: + * SDRAM initialization has two parts: + * 1. Configuring the SDRAM device + * 2. Update the AC timings related parameters in the EMIF module + * (1) should be done only once and should not be done while we are + * running from SDRAM. + * (2) can and should be done more than once if OPP changes. + * Particularly, this may be needed when we boot without SPL and + * and using Configuration Header(CH). ROM code supports only at 50% OPP + * at boot (low power boot). So u-boot has to switch to OPP100 and update + * the frequency. So, + * Doing (1) and (2) makes sense - first time initialization + * Doing (2) and not (1) makes sense - OPP change (when using CH) + * Doing (1) and not (2) doen't make sense + * See do_sdram_init() for the details + */ +void sdram_init(void) +{ + u32 in_sdram, size_prog, size_detect; + + debug(">>sdram_init()\n"); + + if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) + return; + + in_sdram = running_from_sdram(); + debug("in_sdram = %d\n", in_sdram); + + if (!in_sdram) + bypass_dpll(&prcm->cm_clkmode_dpll_core); + + + do_sdram_init(EMIF1_BASE); + do_sdram_init(EMIF2_BASE); + + if (!in_sdram) { + dmm_init(DMM_BASE); + emif_post_init_config(EMIF1_BASE); + emif_post_init_config(EMIF2_BASE); + } + + /* for the shadow registers to take effect */ + freq_update_core(); + + /* Do some testing after the init */ + if (!in_sdram) { + size_prog = omap_sdram_size(); + size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + size_prog); + /* Compare with the size programmed */ + if (size_detect != size_prog) { + printf("SDRAM: identified size not same as expected" + " size identified: %x expected: %x\n", + size_detect, + size_prog); + } else + debug("get_ram_size() successful"); + } + + debug("<<sdram_init()\n"); +} diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c new file mode 100644 index 0000000000..f65705db12 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -0,0 +1,267 @@ +/* + * + * Common functions for OMAP4/5 based boards + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Author : + * Aneesh V <aneesh@ti.com> + * Steve Sakoman <steve@sakoman.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/sizes.h> +#include <asm/emif.h> +#include <asm/omap_common.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * This is used to verify if the configuration header + * was executed by rom code prior to control of transfer + * to the bootloader. SPL is responsible for saving and + * passing the boot_params pointer to the u-boot. + */ +struct omap_boot_parameters boot_params __attribute__ ((section(".data"))); + +#ifdef CONFIG_SPL_BUILD +/* + * We use static variables because global data is not ready yet. + * Initialized data is available in SPL right from the beginning. + * We would not typically need to save these parameters in regular + * U-Boot. This is needed only in SPL at the moment. + */ +u32 omap_bootmode = MMCSD_MODE_FAT; + +u32 omap_boot_device(void) +{ + return (u32) (boot_params.omap_bootdevice); +} + +u32 omap_boot_mode(void) +{ + return omap_bootmode; +} +#endif + +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *) array; + + for (i = 0; i < size; i++, pad++) + writew(pad->val, base + pad->offset); +} + +static void set_mux_conf_regs(void) +{ + switch (omap_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + set_muxconf_regs_essential(); + break; + case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: +#ifdef CONFIG_SYS_ENABLE_PADS_ALL + set_muxconf_regs_non_essential(); +#endif + break; + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + set_muxconf_regs_essential(); +#ifdef CONFIG_SYS_ENABLE_PADS_ALL + set_muxconf_regs_non_essential(); +#endif + break; + } +} + +u32 cortex_rev(void) +{ + + unsigned int rev; + + /* Read Main ID Register (MIDR) */ + asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); + + return rev; +} + +void omap_rev_string(char *omap_rev_string) +{ + u32 omap_rev = omap_revision(); + u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; + u32 major_rev = (omap_rev & 0x00000F00) >> 8; + u32 minor_rev = (omap_rev & 0x000000F0) >> 4; + + sprintf(omap_rev_string, "OMAP%x ES%x.%x", omap_variant, major_rev, + minor_rev); +} + +#ifdef CONFIG_SPL_BUILD +static void init_boot_params(void) +{ + boot_params_ptr = (u32 *) &boot_params; +} +#endif + +/* + * Routine: s_init + * Description: Does early system init of watchdog, muxing, andclocks + * Watchdog disable is done always. For the rest what gets done + * depends on the boot mode in which this function is executed + * 1. s_init of SPL running from SRAM + * 2. s_init of U-Boot running from FLASH + * 3. s_init of U-Boot loaded to SDRAM by SPL + * 4. s_init of U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * Please have a look at the respective functions to see what gets + * done in each of these cases + * This function is called with SRAM stack. + */ +void s_init(void) +{ + init_omap_revision(); + watchdog_init(); + set_mux_conf_regs(); +#ifdef CONFIG_SPL_BUILD + setup_clocks_for_console(); + preloader_console_init(); + do_io_settings(); +#endif + prcm_init(); +#ifdef CONFIG_SPL_BUILD + /* For regular u-boot sdram_init() is called from dram_init() */ + sdram_init(); + init_boot_params(); +#endif +} + +/* + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + */ +void wait_for_command_complete(struct watchdog *wd_base) +{ + int pending = 1; + do { + pending = readl(&wd_base->wwps); + } while (pending); +} + +/* + * Routine: watchdog_init + * Description: Shut down watch dogs + */ +void watchdog_init(void) +{ + struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; + + writel(WD_UNLOCK1, &wd2_base->wspr); + wait_for_command_complete(wd2_base); + writel(WD_UNLOCK2, &wd2_base->wspr); +} + + +/* + * This function finds the SDRAM size available in the system + * based on DMM section configurations + * This is needed because the size of memory installed may be + * different on different versions of the board + */ +u32 omap_sdram_size(void) +{ + u32 section, i, total_size = 0, size, addr; + + for (i = 0; i < 4; i++) { + section = __raw_readl(DMM_BASE + i*4); + addr = section & EMIF_SYS_ADDR_MASK; + /* See if the address is valid */ + if ((addr >= DRAM_ADDR_SPACE_START) && + (addr < DRAM_ADDR_SPACE_END)) { + size = ((section & EMIF_SYS_SIZE_MASK) >> + EMIF_SYS_SIZE_SHIFT); + size = 1 << size; + size *= SZ_16M; + total_size += size; + } + } + + return total_size; +} + + +/* + * Routine: dram_init + * Description: sets uboots idea of sdram size + */ +int dram_init(void) +{ + sdram_init(); + gd->ram_size = omap_sdram_size(); + return 0; +} + +/* + * Print board information + */ +int checkboard(void) +{ + puts(sysinfo.board_string); + return 0; +} + +/* +* This function is called by start_armboot. You can reliably use static +* data. Any boot-time function that require static data should be +* called from here +*/ +int arch_cpu_init(void) +{ + return 0; +} + +/* + * get_device_type(): tell if GP/HS/EMU/TST + */ +u32 get_device_type(void) +{ + return 0; +} + +/* + * Print CPU information + */ +int print_cpuinfo(void) +{ + char rev_string_buffer[50]; + + omap_rev_string(rev_string_buffer); + printf("CPU : %s\n", rev_string_buffer); + + return 0; +} +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 91525ecd46..35f38acf5d 100644 --- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -26,8 +26,8 @@ * MA 02111-1307 USA */ -#include <asm/arch/omap4.h> -#ifdef CONFIG_SPL_BUILD +#include <asm/arch/omap.h> + .global save_boot_params save_boot_params: /* @@ -43,21 +43,40 @@ save_boot_params: cmp r2, r0 blt 1f - /* Store the boot device in omap4_boot_device */ - ldr r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device + /* + * store the boot params passed from rom code or saved + * and passed by SPL + */ + cmp r0, #0 + beq 1f + ldr r1, =boot_params + str r0, [r1] +#ifdef CONFIG_SPL_BUILD + /* Store the boot device in omap_boot_device */ + ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device and r2, #BOOT_DEVICE_MASK - ldr r3, =omap4_boot_device - str r2, [r3] @ omap4_boot_device <- r1 + ldr r3, =boot_params + strb r2, [r3, #BOOT_DEVICE_OFFSET] @ omap_boot_device <- r1 - /* Store the boot mode (raw/FAT) in omap4_boot_mode */ + /* boot mode is passed only for devices that can raw/fat mode */ + cmp r2, #2 + blt 2f + cmp r2, #7 + bgt 2f + /* Store the boot mode (raw/FAT) in omap_boot_mode */ ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode - ldr r3, =omap4_boot_mode + ldr r3, =omap_bootmode str r2, [r3] +#endif +2: + ldrb r2, [r0, #CH_FLAGS_OFFSET] + ldr r3, =boot_params + strb r2, [r3, #CH_FLAGS_OFFSET] 1: bx lr -#endif + .globl lowlevel_init lowlevel_init: diff --git a/arch/arm/cpu/armv7/omap4/mem.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 878f0e3042..878f0e3042 100644 --- a/arch/arm/cpu/armv7/omap4/mem.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 2c59d2b36b..9c35a09038 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; +u32* boot_params_ptr = NULL; struct spl_image_info spl_image; /* Define global data structure pointer to it*/ @@ -92,12 +93,17 @@ void spl_parse_image_header(const struct image_header *header) static void jump_to_image_no_args(void) { - typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn)); + typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn)); image_entry_noargs_t image_entry = (image_entry_noargs_t) spl_image.entry_point; debug("image entry point: 0x%X\n", spl_image.entry_point); - image_entry(); + /* Pass the saved boot_params from rom code */ +#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU) + image_entry = (image_entry_noargs_t)0x80100000; +#endif + u32 boot_params_ptr_addr = (u32)&boot_params_ptr; + image_entry((u32 *)boot_params_ptr_addr); } void jump_to_image_no_args(void) __attribute__ ((noreturn)); @@ -110,7 +116,10 @@ void board_init_r(gd_t *id, ulong dummy) CONFIG_SYS_SPL_MALLOC_SIZE); timer_init(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + +#ifdef CONFIG_SPL_BOARD_INIT + spl_board_init(); +#endif boot_device = omap_boot_device(); debug("boot device - %d\n", boot_device); diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 8e8589157c..ac597be25a 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -31,7 +31,11 @@ COBJS += board.o COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o +endif +COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o COBJS-$(CONFIG_EMIF4) += emif4.o COBJS-$(CONFIG_SDRC) += sdrc.o diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index a9fdb4f8ed..1f33c6398c 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -40,6 +40,7 @@ #include <asm/armv7.h> #include <asm/arch/gpio.h> #include <asm/omap_common.h> +#include <i2c.h> /* Declarations */ extern omap3_sysinfo sysinfo; @@ -89,18 +90,12 @@ u32 omap_boot_device(void) return omap3_boot_device; } -#endif /* CONFIG_SPL_BUILD */ - - -/****************************************************************************** - * Routine: delay - * Description: spinning delay to use before udelay works - *****************************************************************************/ -static inline void delay(unsigned long loops) +void spl_board_init(void) { - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); } +#endif /* CONFIG_SPL_BUILD */ + /****************************************************************************** * Routine: secure_unlock @@ -227,7 +222,7 @@ void s_init(void) #endif set_muxconf_regs(); - delay(100); + sdelay(100); prcm_init(); diff --git a/arch/arm/cpu/armv7/omap3/emac.c b/arch/arm/cpu/armv7/omap3/emac.c new file mode 100644 index 0000000000..14667f18d5 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/emac.c @@ -0,0 +1,44 @@ +/* + * + * DaVinci EMAC initialization. + * + * (C) Copyright 2011, Ilya Yanok, Emcraft Systems + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/am35x_def.h> + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ + u32 reset; + + /* ensure that the module is out of reset */ + reset = readl(&am35x_scm_general_regs->ip_sw_reset); + reset &= ~CPGMACSS_SW_RST; + writel(reset, &am35x_scm_general_regs->ip_sw_reset); + + return davinci_emac_initialize(); +} diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index a308ebdb6a..2f6930b22d 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -216,6 +216,14 @@ lowlevel_init: ldr sp, SRAM_STACK str ip, [sp] /* stash old link register */ mov ip, lr /* save link reg across call */ +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) +/* + * No need to copy/exec the clock code - DPLL adjust already done + * in NAND/oneNAND Boot. + */ + ldr r1, =SRAM_CLK_CODE + bl cpy_clk_code +#endif /* NAND Boot */ bl s_init /* go setup pll, mux, memory */ ldr ip, [sp] /* restore save ip */ mov lr, ip /* restore link reg */ diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index a01c303e71..2fe5ac7c39 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -86,6 +86,7 @@ u32 mem_ok(u32 cs) writel(0x0, addr + 4); /* remove pattern off the bus */ val1 = readl(addr + 0x400); /* get pos A value */ val2 = readl(addr); /* get val2 */ + writel(0x0, addr + 0x400); /* clear pos A */ if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ return 0; @@ -105,9 +106,15 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, writel(gpmc_config[3], &cs->config4); writel(gpmc_config[4], &cs->config5); writel(gpmc_config[5], &cs->config6); - /* Enable the config */ - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); + + /* + * Enable the config. size is the CS size and goes in + * bits 11:8. We set bit 6 to enable this CS and the base + * address goes into bits 5:0. + */ + writel((size << 8) | (GPMC_CS_ENABLE << 6) | + ((base >> 24) & GPMC_BASEADDR_MASK), + &cs->config7); sdelay(2000); } diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 0dd1955431..a27b4b124e 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -58,10 +58,9 @@ u32 is_mem_sdr(void) /* * make_cs1_contiguous - - * - For es2 and above remap cs1 behind cs0 to allow command line - * mem=xyz use all memory with out discontinuous support compiled in. - * Could do it at the ATAG, but there really is two banks... - * - Called as part of 2nd phase DDR init. + * - When we have CS1 populated we want to have it mapped after cs0 to allow + * command line mem=xyz use all memory with out discontinuous support + * compiled in. We could do it in the ATAG, but there really is two banks... */ void make_cs1_contiguous(void) { @@ -109,15 +108,58 @@ u32 get_sdr_cs_offset(u32 cs) } /* + * write_sdrc_timings - + * - Takes CS and associated timings and initalize SDRAM + * - Test CS to make sure it's OK for use + */ +static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, + u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr) +{ + /* Setup timings we got from the board. */ + writel(mcfg, &sdrc_base->cs[cs].mcfg); + writel(ctrla, &sdrc_actim_base->ctrla); + writel(ctrlb, &sdrc_actim_base->ctrlb); + writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); + writel(CMD_NOP, &sdrc_base->cs[cs].manual); + writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(mr, &sdrc_base->cs[cs].mr); + + /* + * Test ram in this bank + * Disable if bad or not present + */ + if (!mem_ok(cs)) + writel(0, &sdrc_base->cs[cs].mcfg); +} + +/* * do_sdrc_init - - * - Initialize the SDRAM for use. - * - code called once in C-Stack only context for CS0 and a possible 2nd - * time depending on memory configuration from stack+global context + * - Code called once in C-Stack only context for CS0 and with early being + * true and a possible 2nd time depending on memory configuration from + * stack+global context. */ void do_sdrc_init(u32 cs, u32 early) { struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; + u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr; + + sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; + /* + * When called in the early context this may be SPL and we will + * need to set all of the timings. This ends up being board + * specific so we call a helper function to take care of this + * for us. Otherwise, to be safe, we need to copy the settings + * from the first bank to the second. We will setup CS0, + * then set cs_cfg to the appropriate value then try and + * setup CS1. + */ +#ifdef CONFIG_SPL_BUILD + get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr); +#endif if (early) { /* reset sdrc controller */ writel(SOFTRESET, &sdrc_base->sysconfig); @@ -128,73 +170,38 @@ void do_sdrc_init(u32 cs, u32 early) /* setup sdrc to ball mux */ writel(SDRC_SHARING, &sdrc_base->sharing); - /* Disable Power Down of CKE cuz of 1 CKE on combo part */ + /* Disable Power Down of CKE because of 1 CKE on combo part */ writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power); writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); - } - -/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need - * to prevent this to be build in non-SPL build */ #ifdef CONFIG_SPL_BUILD - /* If we use a SPL there is no x-loader nor config header so we have - * to do the job ourselfs - */ - if (cs == CS0) { - sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; - - /* General SDRC config */ - writel(V_MCFG, &sdrc_base->cs[cs].mcfg); - writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl); - - /* AC timings */ - writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla); - writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb); - - /* Initialize */ - writel(CMD_NOP, &sdrc_base->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, + rfr_ctrl, mr); + make_cs1_contiguous(); + write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb, + rfr_ctrl, mr); +#endif - writel(V_MR, &sdrc_base->cs[cs].mr); } -#endif /* - * SDRC timings are set up by x-load or config header - * We don't need to redo them here. - * Older x-loads configure only CS0 - * configure CS1 to handle this ommission + * If we aren't using SPL we have been loaded by some + * other means which may not have correctly initialized + * both CS0 and CS1 (such as some older versions of x-loader) + * so we may be asked now to setup CS1. */ if (cs == CS1) { - sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; - sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; - writel(readl(&sdrc_base->cs[CS0].mcfg), - &sdrc_base->cs[CS1].mcfg); - writel(readl(&sdrc_base->cs[CS0].rfr_ctrl), - &sdrc_base->cs[CS1].rfr_ctrl); - writel(readl(&sdrc_actim_base0->ctrla), - &sdrc_actim_base1->ctrla); - writel(readl(&sdrc_actim_base0->ctrlb), - &sdrc_actim_base1->ctrlb); - - writel(CMD_NOP, &sdrc_base->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(readl(&sdrc_base->cs[CS0].mr), - &sdrc_base->cs[CS1].mr); - } + mcfg = readl(&sdrc_base->cs[CS0].mcfg), + rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); + ctrla = readl(&sdrc_actim_base0->ctrla), + ctrlb = readl(&sdrc_actim_base0->ctrlb); + mr = readl(&sdrc_base->cs[CS0].mr); + write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb, + rfr_ctrl, mr); - /* - * Test ram in this bank - * Disable if bad or not present - */ - if (!mem_ok(cs)) - writel(0, &sdrc_base->cs[cs].mcfg); + } } /* @@ -207,16 +214,16 @@ int dram_init(void) size0 = get_sdr_cs_size(CS0); /* - * If a second bank of DDR is attached to CS1 this is - * where it can be started. Early init code will init - * memory on CS0. + * We always need to have cs_cfg point at where the second + * bank would be, if present. Failure to do so can lead to + * strange situations where memory isn't detected and + * configured correctly. CS0 will already have been setup + * at this point. */ - if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { - do_sdrc_init(CS1, NOT_EARLY); - make_cs1_contiguous(); + make_cs1_contiguous(); + do_sdrc_init(CS1, NOT_EARLY); + size1 = get_sdr_cs_size(CS1); - size1 = get_sdr_cs_size(CS1); - } gd->ram_size = size0 + size1; return 0; diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c new file mode 100644 index 0000000000..0871fc92f7 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2011 + * Texas Instruments, <www.ti.com> + * + * Author : + * Tom Rini <trini@ti.com> + * + * Initial Code from: + * Richard Woodruff <r-woodruff2@ti.com> + * Jian Zhang <jzhang@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/mtd/nand.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> + +static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; + +/* nand_command: Send a flash command to the flash chip */ +static void nand_command(u8 command) +{ + writeb(command, &gpmc_config->cs[0].nand_cmd); + + if (command == NAND_CMD_RESET) { + unsigned char ret_val; + writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); + do { + /* Wait until ready */ + ret_val = readl(&gpmc_config->cs[0].nand_dat); + } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY); + } +} + +/* + * Many boards will want to know the results of the NAND_CMD_READID command + * in order to decide what to do about DDR initialization. This function + * allows us to do that very early and to pass those results back to the + * board so it can make whatever decisions need to be made. + */ +void identify_nand_chip(int *mfr, int *id) +{ + /* Make sure that we have setup GPMC for NAND correctly. */ + writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); + writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); + writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3); + writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4); + writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5); + writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6); + + /* + * Enable the config. The CS size goes in bits 11:8. We set + * bit 6 to enable the CS and the base address goes into bits 5:0. + */ + writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) | + ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK), + &gpmc_config->cs[0].config7); + + sdelay(2000); + + /* Issue a RESET and then READID */ + nand_command(NAND_CMD_RESET); + nand_command(NAND_CMD_READID); + + /* Set the address to read to 0x0 */ + writeb(0x0, &gpmc_config->cs[0].nand_adr); + + /* Read off the manufacturer and device id. */ + *mfr = readb(&gpmc_config->cs[0].nand_dat); + *id = readb(&gpmc_config->cs[0].nand_dat); +} diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index e7ee0b8c0a..83160a28f3 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -25,17 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -SOBJS += lowlevel_init.o - -COBJS += board.o +COBJS += sdram_elpida.o +COBJS += hwinit.o COBJS += clocks.o COBJS += emif.o -COBJS += sdram_elpida.o - -ifndef CONFIG_SPL_BUILD -COBJS += mem.o -COBJS += sys_info.o -endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c deleted file mode 100644 index 2497e3e729..0000000000 --- a/arch/arm/cpu/armv7/omap4/board.c +++ /dev/null @@ -1,384 +0,0 @@ -/* - * - * Common functions for OMAP4 based boards - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Author : - * Aneesh V <aneesh@ti.com> - * Steve Sakoman <steve@sakoman.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/armv7.h> -#include <asm/arch/cpu.h> -#include <asm/arch/sys_proto.h> -#include <asm/sizes.h> -#include <asm/arch/emif.h> -#include <asm/arch/gpio.h> -#include "omap4_mux_data.h" - -DECLARE_GLOBAL_DATA_PTR; - -u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; - -static const struct gpio_bank gpio_bank_44xx[6] = { - { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX }, -}; - -const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; - -#ifdef CONFIG_SPL_BUILD -/* - * We use static variables because global data is not ready yet. - * Initialized data is available in SPL right from the beginning. - * We would not typically need to save these parameters in regular - * U-Boot. This is needed only in SPL at the moment. - */ -u32 omap4_boot_device = BOOT_DEVICE_MMC1; -u32 omap4_boot_mode = MMCSD_MODE_FAT; - -u32 omap_boot_device(void) -{ - return omap4_boot_device; -} - -u32 omap_boot_mode(void) -{ - return omap4_boot_mode; -} - -/* - * Some tuning of IOs for optimal power and performance - */ -static void do_io_settings(void) -{ - u32 lpddr2io; - struct control_lpddr2io_regs *lpddr2io_regs = - (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; - struct omap4_sys_ctrl_regs *const ctrl = - (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; - - u32 omap4_rev = omap_revision(); - - if (omap4_rev == OMAP4430_ES1_0) - lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; - else if (omap4_rev == OMAP4430_ES2_0) - lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; - else - lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; - - /* EMIF1 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1); - /* No pull for GR10 as per hw team's recommendation */ - writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io1_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3); - - /* EMIF2 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1); - /* No pull for GR10 as per hw team's recommendation */ - writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io2_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3); - - /* - * Some of these settings (TRIM values) come from eFuse and are - * in turn programmed in the eFuse at manufacturing time after - * calibration of the device. Do the software over-ride only if - * the device is not correctly trimmed - */ - if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) { - - writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_iva_voltage_ctrl); - - writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_mpu_voltage_ctrl); - - writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_core_voltage_ctrl); - } - - if (!readl(&ctrl->control_efuse_1)) - writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1); - - if (!readl(&ctrl->control_efuse_2)) - writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2); -} -#endif - -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) -{ - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *) array; - - for (i = 0; i < size; i++, pad++) - writew(pad->val, base + pad->offset); -} - -static void set_muxconf_regs_essential(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, - sizeof(core_padconf_array_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, - sizeof(wkup_padconf_array_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() >= OMAP4460_ES1_0) - do_set_mux(CONTROL_PADCONF_WKUP, - wkup_padconf_array_essential_4460, - sizeof(wkup_padconf_array_essential_4460) / - sizeof(struct pad_conf_entry)); -} - -static void set_mux_conf_regs(void) -{ - switch (omap4_hw_init_context()) { - case OMAP_INIT_CONTEXT_SPL: - set_muxconf_regs_essential(); - break; - case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: - set_muxconf_regs_non_essential(); - break; - case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: - case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: - set_muxconf_regs_essential(); - set_muxconf_regs_non_essential(); - break; - } -} - -static u32 cortex_a9_rev(void) -{ - - unsigned int rev; - - /* Read Main ID Register (MIDR) */ - asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); - - return rev; -} - -static void init_omap4_revision(void) -{ - /* - * For some of the ES2/ES1 boards ID_CODE is not reliable: - * Also, ES1 and ES2 have different ARM revisions - * So use ARM revision for identification - */ - unsigned int arm_rev = cortex_a9_rev(); - - switch (arm_rev) { - case MIDR_CORTEX_A9_R0P1: - *omap4_revision = OMAP4430_ES1_0; - break; - case MIDR_CORTEX_A9_R1P2: - switch (readl(CONTROL_ID_CODE)) { - case OMAP4430_CONTROL_ID_CODE_ES2_0: - *omap4_revision = OMAP4430_ES2_0; - break; - case OMAP4430_CONTROL_ID_CODE_ES2_1: - *omap4_revision = OMAP4430_ES2_1; - break; - case OMAP4430_CONTROL_ID_CODE_ES2_2: - *omap4_revision = OMAP4430_ES2_2; - break; - default: - *omap4_revision = OMAP4430_ES2_0; - break; - } - break; - case MIDR_CORTEX_A9_R1P3: - *omap4_revision = OMAP4430_ES2_3; - break; - case MIDR_CORTEX_A9_R2P10: - switch (readl(CONTROL_ID_CODE)) { - case OMAP4460_CONTROL_ID_CODE_ES1_0: - *omap4_revision = OMAP4460_ES1_0; - break; - case OMAP4460_CONTROL_ID_CODE_ES1_1: - *omap4_revision = OMAP4460_ES1_1; - break; - default: - *omap4_revision = OMAP4460_ES1_0; - break; - } - break; - default: - *omap4_revision = OMAP4430_SILICON_ID_INVALID; - break; - } -} - -void omap_rev_string(char *omap4_rev_string) -{ - u32 omap4_rev = omap_revision(); - u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16; - u32 major_rev = (omap4_rev & 0x00000F00) >> 8; - u32 minor_rev = (omap4_rev & 0x000000F0) >> 4; - - sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev, - minor_rev); -} - -/* - * Routine: s_init - * Description: Does early system init of watchdog, muxing, andclocks - * Watchdog disable is done always. For the rest what gets done - * depends on the boot mode in which this function is executed - * 1. s_init of SPL running from SRAM - * 2. s_init of U-Boot running from FLASH - * 3. s_init of U-Boot loaded to SDRAM by SPL - * 4. s_init of U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * Please have a look at the respective functions to see what gets - * done in each of these cases - * This function is called with SRAM stack. - */ -void s_init(void) -{ - init_omap4_revision(); - watchdog_init(); - set_mux_conf_regs(); -#ifdef CONFIG_SPL_BUILD - setup_clocks_for_console(); - preloader_console_init(); - do_io_settings(); -#endif - prcm_init(); -#ifdef CONFIG_SPL_BUILD - /* For regular u-boot sdram_init() is called from dram_init() */ - sdram_init(); -#endif -} - -/* - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - */ -void wait_for_command_complete(struct watchdog *wd_base) -{ - int pending = 1; - do { - pending = readl(&wd_base->wwps); - } while (pending); -} - -/* - * Routine: watchdog_init - * Description: Shut down watch dogs - */ -void watchdog_init(void) -{ - struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; - - writel(WD_UNLOCK1, &wd2_base->wspr); - wait_for_command_complete(wd2_base); - writel(WD_UNLOCK2, &wd2_base->wspr); -} - - -/* - * This function finds the SDRAM size available in the system - * based on DMM section configurations - * This is needed because the size of memory installed may be - * different on different versions of the board - */ -u32 omap4_sdram_size(void) -{ - u32 section, i, total_size = 0, size, addr; - for (i = 0; i < 4; i++) { - section = __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4); - addr = section & OMAP44XX_SYS_ADDR_MASK; - /* See if the address is valid */ - if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) && - (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) { - size = ((section & OMAP44XX_SYS_SIZE_MASK) >> - OMAP44XX_SYS_SIZE_SHIFT); - size = 1 << size; - size *= SZ_16M; - total_size += size; - } - } - return total_size; -} - - -/* - * Routine: dram_init - * Description: sets uboots idea of sdram size - */ -int dram_init(void) -{ - sdram_init(); - gd->ram_size = omap4_sdram_size(); - - return 0; -} - -/* - * Print board information - */ -int checkboard(void) -{ - puts(sysinfo.board_string); - return 0; -} - -/* -* This function is called by start_armboot. You can reliably use static -* data. Any boot-time function that require static data should be -* called from here -*/ -int arch_cpu_init(void) -{ - return 0; -} - -#ifndef CONFIG_SYS_L2CACHE_OFF -void v7_outer_cache_enable(void) -{ - set_pl310_ctrl_reg(1); -} - -void v7_outer_cache_disable(void) -{ - set_pl310_ctrl_reg(0); -} -#endif - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 095ba39aeb..0886f92431 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -50,7 +50,7 @@ struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; -static const u32 sys_clk_array[8] = { +const u32 sys_clk_array[8] = { 12000000, /* 12 MHz */ 13000000, /* 13 MHz */ 16800000, /* 16.8 MHz */ @@ -79,14 +79,14 @@ static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = { }; /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ -static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = { - {66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; /* dpll locked at 1200 MHz - MPU clk at 600 MHz */ @@ -168,7 +168,6 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = { 750, 0, 1, 1, -1, -1, -1, -1 }; - static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -179,98 +178,10 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -static inline u32 __get_sys_clk_index(void) -{ - u32 ind; - /* - * For ES1 the ROM code calibration of sys clock is not reliable - * due to hw issue. So, use hard-coded value. If this value is not - * correct for any board over-ride this function in board file - * From ES2.0 onwards you will get this information from - * CM_SYS_CLKSEL - */ - if (omap_revision() == OMAP4430_ES1_0) - ind = OMAP_SYS_CLK_IND_38_4_MHZ; - else { - /* SYS_CLKSEL - 1 to match the dpll param array indices */ - ind = (readl(&prcm->cm_sys_clksel) & - CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; - } - return ind; -} - -u32 get_sys_clk_index(void) - __attribute__ ((weak, alias("__get_sys_clk_index"))); - -u32 get_sys_clk_freq(void) -{ - u8 index = get_sys_clk_index(); - return sys_clk_array[index]; -} - -static inline void do_bypass_dpll(u32 *const base) -{ - struct dpll_regs *dpll_regs = (struct dpll_regs *)base; - - clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, - CM_CLKMODE_DPLL_DPLL_EN_MASK, - DPLL_EN_FAST_RELOCK_BYPASS << - CM_CLKMODE_DPLL_EN_SHIFT); -} - -static inline void wait_for_bypass(u32 *const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, - LDELAY)) { - printf("Bypassing DPLL failed %p\n", base); - } -} - -static inline void do_lock_dpll(u32 *const base) +void setup_post_dividers(u32 *const base, const struct dpll_params *params) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, - CM_CLKMODE_DPLL_DPLL_EN_MASK, - DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); -} - -static inline void wait_for_lock(u32 *const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, - &dpll_regs->cm_idlest_dpll, LDELAY)) { - printf("DPLL locking failed for %p\n", base); - hang(); - } -} - -static void do_setup_dpll(u32 *const base, const struct dpll_params *params, - u8 lock) -{ - u32 temp; - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - bypass_dpll(base); - - /* Set M & N */ - temp = readl(&dpll_regs->cm_clksel_dpll); - - temp &= ~CM_CLKSEL_DPLL_M_MASK; - temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; - - temp &= ~CM_CLKSEL_DPLL_N_MASK; - temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; - - writel(temp, &dpll_regs->cm_clksel_dpll); - - /* Lock */ - if (lock) - do_lock_dpll(base); - /* Setup post-dividers */ if (params->m2 >= 0) writel(params->m2, &dpll_regs->cm_div_m2_dpll); @@ -284,10 +195,29 @@ static void do_setup_dpll(u32 *const base, const struct dpll_params *params, writel(params->m6, &dpll_regs->cm_div_m6_dpll); if (params->m7 >= 0) writel(params->m7, &dpll_regs->cm_div_m7_dpll); +} + +/* + * Lock MPU dpll + * + * Resulting MPU frequencies: + * 4430 ES1.0 : 600 MHz + * 4430 ES2.x : 792 MHz (OPP Turbo) + * 4460 : 920 MHz (OPP Turbo) - DCC disabled + */ +const struct dpll_params *get_mpu_dpll_params(void) +{ + u32 omap_rev, sysclk_ind; - /* Wait till the DPLL locks */ - if (lock) - wait_for_lock(base); + omap_rev = omap_revision(); + sysclk_ind = get_sys_clk_index(); + + if (omap_rev == OMAP4430_ES1_0) + return &mpu_dpll_params_1200mhz[sysclk_ind]; + else if (omap_rev < OMAP4460_ES1_0) + return &mpu_dpll_params_1600mhz[sysclk_ind]; + else + return &mpu_dpll_params_1840mhz[sysclk_ind]; } const struct dpll_params *get_core_dpll_params(void) @@ -306,228 +236,33 @@ const struct dpll_params *get_core_dpll_params(void) } } -u32 omap4_ddr_clk(void) -{ - u32 ddr_clk, sys_clk_khz; - const struct dpll_params *core_dpll_params; - - sys_clk_khz = get_sys_clk_freq() / 1000; - - core_dpll_params = get_core_dpll_params(); - debug("sys_clk %d\n ", sys_clk_khz * 1000); - - /* Find Core DPLL locked frequency first */ - ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / - (core_dpll_params->n + 1); - /* - * DDR frequency is PHY_ROOT_CLK/2 - * PHY_ROOT_CLK = Fdpll/2/M2 - */ - ddr_clk = ddr_clk / 4 / core_dpll_params->m2; - - ddr_clk *= 1000; /* convert to Hz */ - debug("ddr_clk %d\n ", ddr_clk); - - return ddr_clk; +const struct dpll_params *get_per_dpll_params(void) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &per_dpll_params_1536mhz[sysclk_ind]; } -/* - * Lock MPU dpll - * - * Resulting MPU frequencies: - * 4430 ES1.0 : 600 MHz - * 4430 ES2.x : 792 MHz (OPP Turbo) - * 4460 : 920 MHz (OPP Turbo) - DCC disabled - */ -void configure_mpu_dpll(void) +const struct dpll_params *get_iva_dpll_params(void) { - const struct dpll_params *params; - struct dpll_regs *mpu_dpll_regs; - u32 omap4_rev, sysclk_ind; - - omap4_rev = omap_revision(); - sysclk_ind = get_sys_clk_index(); - - if (omap4_rev == OMAP4430_ES1_0) - params = &mpu_dpll_params_1200mhz[sysclk_ind]; - else if (omap4_rev < OMAP4460_ES1_0) - params = &mpu_dpll_params_1584mhz[sysclk_ind]; - else - params = &mpu_dpll_params_1840mhz[sysclk_ind]; - - /* DCC and clock divider settings for 4460 */ - if (omap4_rev >= OMAP4460_ES1_0) { - mpu_dpll_regs = - (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu; - bypass_dpll(&prcm->cm_clkmode_dpll_mpu); - clrbits_le32(&prcm->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); - setbits_le32(&prcm->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); - clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, - CM_CLKSEL_DCC_EN_MASK); - } - - do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK); - debug("MPU DPLL locked\n"); + u32 sysclk_ind = get_sys_clk_index(); + return &iva_dpll_params_1862mhz[sysclk_ind]; } -static void setup_dplls(void) +const struct dpll_params *get_usb_dpll_params(void) { - u32 sysclk_ind, temp; - const struct dpll_params *params; - debug("setup_dplls\n"); - - sysclk_ind = get_sys_clk_index(); - - /* CORE dpll */ - params = get_core_dpll_params(); /* default - safest */ - /* - * Do not lock the core DPLL now. Just set it up. - * Core DPLL will be locked after setting up EMIF - * using the FREQ_UPDATE method(freq_update_core()) - */ - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK); - /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ - temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | - (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | - (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); - writel(temp, &prcm->cm_clksel_core); - debug("Core DPLL configured\n"); - - /* lock PER dpll */ - do_setup_dpll(&prcm->cm_clkmode_dpll_per, - &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK); - debug("PER DPLL locked\n"); - - /* MPU dpll */ - configure_mpu_dpll(); + u32 sysclk_ind = get_sys_clk_index(); + return &usb_dpll_params_1920mhz[sysclk_ind]; } -static void setup_non_essential_dplls(void) +const struct dpll_params *get_abe_dpll_params(void) { - u32 sys_clk_khz, abe_ref_clk; - u32 sysclk_ind, sd_div, num, den; - const struct dpll_params *params; - - sysclk_ind = get_sys_clk_index(); - sys_clk_khz = get_sys_clk_freq() / 1000; - - /* IVA */ - clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, - CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); - - do_setup_dpll(&prcm->cm_clkmode_dpll_iva, - &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK); - - /* - * USB: - * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction - * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) - * - where CLKINP is sys_clk in MHz - * Use CLKINP in KHz and adjust the denominator accordingly so - * that we have enough accuracy and at the same time no overflow - */ - params = &usb_dpll_params_1920mhz[sysclk_ind]; - num = params->m * sys_clk_khz; - den = (params->n + 1) * 250 * 1000; - num += den - 1; - sd_div = num / den; - clrsetbits_le32(&prcm->cm_clksel_dpll_usb, - CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, - sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); - - /* Now setup the dpll with the regular function */ - do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK); - -#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK - params = &abe_dpll_params_sysclk_196608khz[sysclk_ind]; - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + u32 sysclk_ind = get_sys_clk_index(); + return &abe_dpll_params_sysclk_196608khz[sysclk_ind]; #else - params = &abe_dpll_params_32k_196608khz; - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; - /* - * We need to enable some additional options to achieve - * 196.608MHz from 32768 Hz - */ - setbits_le32(&prcm->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| - CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| - CM_CLKMODE_DPLL_LPMODE_EN_MASK| - CM_CLKMODE_DPLL_REGM4XEN_MASK); - /* Spend 4 REFCLK cycles at each stage */ - clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_RAMP_RATE_MASK, - 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); + return &abe_dpll_params_32k_196608khz; #endif - - /* Select the right reference clk */ - clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, - CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, - abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); - /* Lock the dpll */ - do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK); -} - -static void do_scale_tps62361(u32 reg, u32 volt_mv) -{ - u32 temp, step; - - step = volt_mv - TPS62361_BASE_VOLT_MV; - step /= 10; - - /* - * Select SET1 in TPS62361: - * VSEL1 is grounded on board. So the following selects - * VSEL1 = 0 and VSEL0 = 1 - */ - gpio_direction_output(TPS62361_VSEL0_GPIO, 0); - gpio_set_value(TPS62361_VSEL0_GPIO, 1); - - temp = TPS62361_I2C_SLAVE_ADDR | - (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | - (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) | - PRM_VC_VAL_BYPASS_VALID_BIT; - debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step); - - writel(temp, &prcm->prm_vc_val_bypass); - if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, - &prcm->prm_vc_val_bypass, LDELAY)) { - puts("Scaling voltage failed for vdd_mpu from TPS\n"); - } -} - -static void do_scale_vcore(u32 vcore_reg, u32 volt_mv) -{ - u32 temp, offset_code; - u32 step = 12660; /* 12.66 mV represented in uV */ - u32 offset = volt_mv; - - /* convert to uV for better accuracy in the calculations */ - offset *= 1000; - - if (omap_revision() == OMAP4430_ES1_0) - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; - else - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; - - offset_code = (offset + step - 1) / step; - /* The code starts at 1 not 0 */ - offset_code++; - - debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, - offset_code); - - temp = SMPS_I2C_SLAVE_ADDR | - (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | - (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) | - PRM_VC_VAL_BYPASS_VALID_BIT; - writel(temp, &prcm->prm_vc_val_bypass); - if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, - &prcm->prm_vc_val_bypass, LDELAY)) { - printf("Scaling voltage failed for 0x%x\n", vcore_reg); - } } /* @@ -536,32 +271,16 @@ static void do_scale_vcore(u32 vcore_reg, u32 volt_mv) * enabled in bootloader. Voltage initialization in the kernel will set * these to the nominal values after enabling Smart-Reflex */ -static void scale_vcores(void) +void scale_vcores(void) { - u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev; + u32 volt, omap_rev; - sys_clk_khz = get_sys_clk_freq() / 1000; + setup_sri2c(); - /* - * Setup the dedicated I2C controller for Voltage Control - * I2C clk - high period 40% low period 60% - */ - cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; - cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; - /* values to be set in register - less by 5 & 7 respectively */ - cycles_hi -= 5; - cycles_low -= 7; - temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | - (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); - writel(temp, &prcm->prm_vc_cfg_i2c_clk); - - /* Disable high speed mode and all advanced features */ - writel(0x0, &prcm->prm_vc_cfg_i2c_mode); - - omap4_rev = omap_revision(); + omap_rev = omap_revision(); /* TPS - supplies vdd_mpu on 4460 */ - if (omap4_rev >= OMAP4460_ES1_0) { - volt = 1430; + if (omap_rev >= OMAP4460_ES1_0) { + volt = 1313; do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt); } @@ -576,8 +295,8 @@ static void scale_vcores(void) * * 4460 : supplies vdd_core */ - if (omap4_rev < OMAP4460_ES1_0) { - volt = 1417; + if (omap_rev < OMAP4460_ES1_0) { + volt = 1325; do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); } else { volt = 1200; @@ -593,55 +312,18 @@ static void scale_vcores(void) * 4430 : supplies vdd_core * 4460 : not connected */ - if (omap4_rev < OMAP4460_ES1_0) { + if (omap_rev < OMAP4460_ES1_0) { volt = 1200; do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); } } -static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) -{ - clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, - enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); - debug("Enable clock domain - %p\n", clkctrl_reg); -} - -static inline void wait_for_clk_enable(u32 *clkctrl_addr) -{ - u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; - u32 bound = LDELAY; - - while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || - (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { - - clkctrl = readl(clkctrl_addr); - idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> - MODULE_CLKCTRL_IDLEST_SHIFT; - if (--bound == 0) { - printf("Clock enable failed for 0x%p idlest 0x%x\n", - clkctrl_addr, clkctrl); - return; - } - } -} - -static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, - u32 wait_for_enable) -{ - clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, - enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); - debug("Enable clock module - %p\n", clkctrl_addr); - if (wait_for_enable) - wait_for_clk_enable(clkctrl_addr); -} - /* * Enable essential clock domains, modules and * do some additional special settings needed */ -static void enable_basic_clocks(void) +void enable_basic_clocks(void) { - u32 i, max = 100, wait_for_enable = 1; u32 *const clk_domains_essential[] = { &prcm->cm_l4per_clkstctrl, &prcm->cm_l3init_clkstctrl, @@ -651,30 +333,23 @@ static void enable_basic_clocks(void) }; u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_memif_emif_1_clkctrl, + &prcm->cm_memif_emif_2_clkctrl, + &prcm->cm_l4cfg_l4_cfg_clkctrl, &prcm->cm_wkup_gpio1_clkctrl, &prcm->cm_l4per_gpio2_clkctrl, &prcm->cm_l4per_gpio3_clkctrl, &prcm->cm_l4per_gpio4_clkctrl, &prcm->cm_l4per_gpio5_clkctrl, &prcm->cm_l4per_gpio6_clkctrl, - &prcm->cm_memif_emif_1_clkctrl, - &prcm->cm_memif_emif_2_clkctrl, - &prcm->cm_l3init_hsusbotg_clkctrl, - &prcm->cm_l3init_usbphy_clkctrl, - &prcm->cm_l4cfg_l4_cfg_clkctrl, 0 }; u32 *const clk_modules_explicit_en_essential[] = { - &prcm->cm_l4per_gptimer2_clkctrl, + &prcm->cm_wkup_gptimer1_clkctrl, &prcm->cm_l3init_hsmmc1_clkctrl, &prcm->cm_l3init_hsmmc2_clkctrl, - &prcm->cm_l4per_mcspi1_clkctrl, - &prcm->cm_wkup_gptimer1_clkctrl, - &prcm->cm_l4per_i2c1_clkctrl, - &prcm->cm_l4per_i2c2_clkctrl, - &prcm->cm_l4per_i2c3_clkctrl, - &prcm->cm_l4per_i2c4_clkctrl, + &prcm->cm_l4per_gptimer2_clkctrl, &prcm->cm_wkup_wdtimer2_clkctrl, &prcm->cm_l4per_uart3_clkctrl, 0 @@ -698,40 +373,45 @@ static void enable_basic_clocks(void) setbits_le32(&prcm->cm_l3init_usbphy_clkctrl, USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); - /* Put the clock domains in SW_WKUP mode */ - for (i = 0; (i < max) && clk_domains_essential[i]; i++) { - enable_clock_domain(clk_domains_essential[i], - CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - } + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void enable_basic_uboot_clocks(void) +{ + u32 *const clk_domains_essential[] = { + 0 + }; - /* Clock modules that need to be put in HW_AUTO */ - for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) { - enable_clock_module(clk_modules_hw_auto_essential[i], - MODULE_CLKCTRL_MODULEMODE_HW_AUTO, - wait_for_enable); + u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_l3init_hsusbotg_clkctrl, + &prcm->cm_l3init_usbphy_clkctrl, + 0 }; - /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ - for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) { - enable_clock_module(clk_modules_explicit_en_essential[i], - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, - wait_for_enable); + u32 *const clk_modules_explicit_en_essential[] = { + &prcm->cm_l4per_mcspi1_clkctrl, + &prcm->cm_l4per_i2c1_clkctrl, + &prcm->cm_l4per_i2c2_clkctrl, + &prcm->cm_l4per_i2c3_clkctrl, + &prcm->cm_l4per_i2c4_clkctrl, + 0 }; - /* Put the clock domains in HW_AUTO mode now */ - for (i = 0; (i < max) && clk_domains_essential[i]; i++) { - enable_clock_domain(clk_domains_essential[i], - CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - } + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); } /* * Enable non-essential clock domains, modules and * do some additional special settings needed */ -static void enable_non_essential_clocks(void) +void enable_non_essential_clocks(void) { - u32 i, max = 100, wait_for_enable = 0; u32 *const clk_domains_non_essential[] = { &prcm->cm_mpu_m3_clkstctrl, &prcm->cm_ivahd_clkstctrl, @@ -807,135 +487,13 @@ static void enable_non_essential_clocks(void) /* Enable all optional functional clocks of DSS */ setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - /* Put the clock domains in SW_WKUP mode */ - for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { - enable_clock_domain(clk_domains_non_essential[i], - CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - } - - /* Clock modules that need to be put in HW_AUTO */ - for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) { - enable_clock_module(clk_modules_hw_auto_non_essential[i], - MODULE_CLKCTRL_MODULEMODE_HW_AUTO, - wait_for_enable); - }; - - /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ - for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i]; - i++) { - enable_clock_module(clk_modules_explicit_en_non_essential[i], - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, - wait_for_enable); - }; - - /* Put the clock domains in HW_AUTO mode now */ - for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { - enable_clock_domain(clk_domains_non_essential[i], - CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - } + do_enable_clocks(clk_domains_non_essential, + clk_modules_hw_auto_non_essential, + clk_modules_explicit_en_non_essential, + 0); /* Put camera module in no sleep mode */ clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << MODULE_CLKCTRL_MODULEMODE_SHIFT); } - - -void freq_update_core(void) -{ - u32 freq_config1 = 0; - const struct dpll_params *core_dpll_params; - - core_dpll_params = get_core_dpll_params(); - /* Put EMIF clock domain in sw wakeup mode */ - enable_clock_domain(&prcm->cm_memif_clkstctrl, - CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); - wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); - - freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | - SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; - - freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & - SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; - - freq_config1 |= (core_dpll_params->m2 << - SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & - SHADOW_FREQ_CONFIG1_M2_DIV_MASK; - - writel(freq_config1, &prcm->cm_shadow_freq_config1); - if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, - &prcm->cm_shadow_freq_config1, LDELAY)) { - puts("FREQ UPDATE procedure failed!!"); - hang(); - } - - /* Put EMIF clock domain back in hw auto mode */ - enable_clock_domain(&prcm->cm_memif_clkstctrl, - CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); - wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); -} - -void bypass_dpll(u32 *const base) -{ - do_bypass_dpll(base); - wait_for_bypass(base); -} - -void lock_dpll(u32 *const base) -{ - do_lock_dpll(base); - wait_for_lock(base); -} - -void setup_clocks_for_console(void) -{ - /* Do not add any spl_debug prints in this function */ - clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_SW_WKUP << - CD_CLKCTRL_CLKTRCTRL_SHIFT); - - /* Enable all UARTs - console will be on one of them */ - clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_HW_AUTO << - CD_CLKCTRL_CLKTRCTRL_SHIFT); -} - -void prcm_init(void) -{ - switch (omap4_hw_init_context()) { - case OMAP_INIT_CONTEXT_SPL: - case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: - case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: - enable_basic_clocks(); - scale_vcores(); - setup_dplls(); - setup_non_essential_dplls(); - enable_non_essential_clocks(); - break; - default: - break; - } -} diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c index 988b2050fa..ca4823dd79 100644 --- a/arch/arm/cpu/armv7/omap4/emif.c +++ b/arch/arm/cpu/armv7/omap4/emif.c @@ -26,645 +26,15 @@ */ #include <common.h> -#include <asm/arch/emif.h> -#include <asm/arch/clocks.h> +#include <asm/emif.h> #include <asm/arch/sys_proto.h> -#include <asm/omap_common.h> #include <asm/utils.h> -static inline u32 emif_num(u32 base) -{ - if (base == OMAP44XX_EMIF1) - return 1; - else if (base == OMAP44XX_EMIF2) - return 2; - else - return 0; -} - -static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) -{ - u32 mr; - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; - writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); - if (omap_revision() == OMAP4430_ES2_0) - mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); - else - mr = readl(&emif->emif_lpddr2_mode_reg_data); - debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), - cs, mr_addr, mr); - return mr; -} - -static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; - writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); - writel(mr_val, &emif->emif_lpddr2_mode_reg_data); -} - -void emif_reset_phy(u32 base) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 iodft; - - iodft = readl(&emif->emif_iodft_tlgc); - iodft |= OMAP44XX_REG_RESET_PHY_MASK; - writel(iodft, &emif->emif_iodft_tlgc); -} - -static void do_lpddr2_init(u32 base, u32 cs) -{ - u32 mr_addr; - - /* Wait till device auto initialization is complete */ - while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) - ; - set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT); - /* - * tZQINIT = 1 us - * Enough loops assuming a maximum of 2GHz - */ - sdelay(2000); - set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); - set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); - /* - * Enable refresh along with writing MR2 - * Encoding of RL in MR2 is (RL - 2) - */ - mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK; - set_mr(base, cs, mr_addr, RL_FINAL - 2); -} - -static void lpddr2_init(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - /* Not NVM */ - clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK); - - /* - * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM - * when EMIF_SDRAM_CONFIG register is written - */ - setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK); - - /* - * Set the SDRAM_CONFIG and PHY_CTRL for the - * un-locked frequency & default RL - */ - writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); - - do_lpddr2_init(base, CS0); - if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK) - do_lpddr2_init(base, CS1); - - writel(regs->sdram_config, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - - /* Enable refresh now */ - clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK); - -} - -static void emif_update_timings(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); - writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); - writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); - writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); - if (omap_revision() == OMAP4430_ES1_0) { - /* ES1 bug EMIF should be in force idle during freq_update */ - writel(0, &emif->emif_pwr_mgmt_ctrl); - } else { - writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); - writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); - } - writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); - writel(regs->zq_config, &emif->emif_zq_config); - writel(regs->temp_alert_config, &emif->emif_temp_alert_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - - if (omap_revision() >= OMAP4460_ES1_0) { - writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, - &emif->emif_l3_config); - } else { - writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, - &emif->emif_l3_config); - } -} - #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) - -static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM; -static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN; -static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE; - -/* - * Organization and refresh requirements for LPDDR2 devices of different - * types and densities. Derived from JESD209-2 section 2.4 - */ -const struct lpddr2_addressing addressing_table[] = { - /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ - {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ - {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ - {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ - {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ - {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ - {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ - {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ - {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ - {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ - {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ -}; - -static const u32 lpddr2_density_2_size_in_mbytes[] = { - 8, /* 64Mb */ - 16, /* 128Mb */ - 32, /* 256Mb */ - 64, /* 512Mb */ - 128, /* 1Gb */ - 256, /* 2Gb */ - 512, /* 4Gb */ - 1024, /* 8Gb */ - 2048, /* 16Gb */ - 4096 /* 32Gb */ -}; - -/* - * Calculate the period of DDR clock from frequency value and set the - * denominator and numerator in global variables for easy access later - */ -static void set_ddr_clk_period(u32 freq) -{ - /* - * period = 1/freq - * period_in_ns = 10^9/freq - */ - *T_num = 1000000000; - *T_den = freq; - cancel_out(T_num, T_den, 200); - -} - -/* - * Convert time in nano seconds to number of cycles of DDR clock - */ -static inline u32 ns_2_cycles(u32 ns) -{ - return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); -} - -/* - * ns_2_cycles with the difference that the time passed is 2 times the actual - * value(to avoid fractions). The cycles returned is for the original value of - * the timing parameter - */ -static inline u32 ns_x2_2_cycles(u32 ns) -{ - return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); -} - -/* - * Find addressing table index based on the device's type(S2 or S4) and - * density - */ -s8 addressing_table_index(u8 type, u8 density, u8 width) -{ - u8 index; - if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) - return -1; - - /* - * Look at the way ADDR_TABLE_INDEX* values have been defined - * in emif.h compared to LPDDR2_DENSITY_* values - * The table is layed out in the increasing order of density - * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed - * at the end - */ - if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) - index = ADDR_TABLE_INDEX1GS2; - else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) - index = ADDR_TABLE_INDEX2GS2; - else - index = density; - - debug("emif: addressing table index %d\n", index); - - return index; -} - -/* - * Find the the right timing table from the array of timing - * tables of the device using DDR clock frequency - */ -static const struct lpddr2_ac_timings *get_timings_table(const struct - lpddr2_ac_timings const *const *device_timings, - u32 freq) -{ - u32 i, temp, freq_nearest; - const struct lpddr2_ac_timings *timings = 0; - - emif_assert(freq <= MAX_LPDDR2_FREQ); - emif_assert(device_timings); - - /* - * Start with the maximum allowed frequency - that is always safe - */ - freq_nearest = MAX_LPDDR2_FREQ; - /* - * Find the timings table that has the max frequency value: - * i. Above or equal to the DDR frequency - safe - * ii. The lowest that satisfies condition (i) - optimal - */ - for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { - temp = device_timings[i]->max_freq; - if ((temp >= freq) && (temp <= freq_nearest)) { - freq_nearest = temp; - timings = device_timings[i]; - } - } - debug("emif: timings table: %d\n", freq_nearest); - return timings; -} - -/* - * Finds the value of emif_sdram_config_reg - * All parameters are programmed based on the device on CS0. - * If there is a device on CS1, it will be same as that on CS0 or - * it will be NVM. We don't support NVM yet. - * If cs1_device pointer is NULL it is assumed that there is no device - * on CS1 - */ -static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, - const struct lpddr2_device_details *cs1_device, - const struct lpddr2_addressing *addressing, - u8 RL) -{ - u32 config_reg = 0; - - config_reg |= (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT; - config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << - OMAP44XX_REG_IBANK_POS_SHIFT; - - config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT; - - config_reg |= RL << OMAP44XX_REG_CL_SHIFT; - - config_reg |= addressing->row_sz[cs0_device->io_width] << - OMAP44XX_REG_ROWSIZE_SHIFT; - - config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT; - - config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << - OMAP44XX_REG_EBANK_SHIFT; - - config_reg |= addressing->col_sz[cs0_device->io_width] << - OMAP44XX_REG_PAGESIZE_SHIFT; - - return config_reg; -} - -static u32 get_sdram_ref_ctrl(u32 freq, - const struct lpddr2_addressing *addressing) -{ - u32 ref_ctrl = 0, val = 0, freq_khz; - freq_khz = freq / 1000; - /* - * refresh rate to be set is 'tREFI * freq in MHz - * division by 10000 to account for khz and x10 in t_REFI_us_x10 - */ - val = addressing->t_REFI_us_x10 * freq_khz / 10000; - ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT; - - return ref_ctrl; -} - -static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, - const struct lpddr2_min_tck *min_tck, - const struct lpddr2_addressing *addressing) -{ - u32 tim1 = 0, val = 0; - val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; - tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT; - - if (addressing->num_banks == BANKS8) - val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / - (4 * (*T_num)) - 1; - else - val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; - - tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT; - - val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; - tim1 |= val << OMAP44XX_REG_T_RC_SHIFT; - - val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; - tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT; - - val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; - tim1 |= val << OMAP44XX_REG_T_WR_SHIFT; - - val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; - tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT; - - val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; - tim1 |= val << OMAP44XX_REG_T_RP_SHIFT; - - return tim1; -} - -static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, - const struct lpddr2_min_tck *min_tck) -{ - u32 tim2 = 0, val = 0; - val = max(min_tck->tCKE, timings->tCKE) - 1; - tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT; - - val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; - tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT; - - /* - * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the - * same value - */ - val = ns_2_cycles(timings->tXSR) - 1; - tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT; - tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT; - - val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; - tim2 |= val << OMAP44XX_REG_T_XP_SHIFT; - - return tim2; -} - -static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, - const struct lpddr2_min_tck *min_tck, - const struct lpddr2_addressing *addressing) -{ - u32 tim3 = 0, val = 0; - val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); - tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT; - - val = ns_2_cycles(timings->tRFCab) - 1; - tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT; - - val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; - tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT; - - val = ns_2_cycles(timings->tZQCS) - 1; - tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT; - - val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; - tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT; - - return tim3; -} - -static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, - const struct lpddr2_addressing *addressing, - u8 volt_ramp) -{ - u32 zq = 0, val = 0; - if (volt_ramp) - val = - EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / - addressing->t_REFI_us_x10; - else - val = - EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / - addressing->t_REFI_us_x10; - zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT; - - zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT; - - zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT; - - zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT; - - /* - * Assuming that two chipselects have a single calibration resistor - * If there are indeed two calibration resistors, then this flag should - * be enabled to take advantage of dual calibration feature. - * This data should ideally come from board files. But considering - * that none of the boards today have calibration resistors per CS, - * it would be an unnecessary overhead. - */ - zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT; - - zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT; - - zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT; - - return zq; -} - -static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, - const struct lpddr2_addressing *addressing, - u8 is_derated) -{ - u32 alert = 0, interval; - interval = - TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; - if (is_derated) - interval *= 4; - alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT; - - alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT; - - alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT; - - alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT; - - alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT; - - alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT; - - return alert; -} - -static u32 get_read_idle_ctrl_reg(u8 volt_ramp) -{ - u32 idle = 0, val = 0; - if (volt_ramp) - val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; - else - /*Maximum value in normal conditions - suggested by hw team */ - val = 0x1FF; - idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT; - - idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT; - - return idle; -} - -static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) -{ - u32 phy = 0, val = 0; - - phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT; - - if (freq <= 100000000) - val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; - else if (freq <= 200000000) - val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; - else - val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; - phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT; - - /* Other fields are constant magic values. Hardcode them together */ - phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << - OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; - - return phy; -} - -static u32 get_emif_mem_size(struct emif_device_details *devices) -{ - u32 size_mbytes = 0, temp; - - if (!devices) - return 0; - - if (devices->cs0_device_details) { - temp = devices->cs0_device_details->density; - size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; - } - - if (devices->cs1_device_details) { - temp = devices->cs1_device_details->density; - size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; - } - /* convert to bytes */ - return size_mbytes << 20; -} - -/* Gets the encoding corresponding to a given DMM section size */ -u32 get_dmm_section_size_map(u32 section_size) -{ - /* - * Section size mapping: - * 0x0: 16-MiB section - * 0x1: 32-MiB section - * 0x2: 64-MiB section - * 0x3: 128-MiB section - * 0x4: 256-MiB section - * 0x5: 512-MiB section - * 0x6: 1-GiB section - * 0x7: 2-GiB section - */ - section_size >>= 24; /* divide by 16 MB */ - return log_2_n_round_down(section_size); -} - -static void emif_calculate_regs( - const struct emif_device_details *emif_dev_details, - u32 freq, struct emif_regs *regs) -{ - u32 temp, sys_freq; - const struct lpddr2_addressing *addressing; - const struct lpddr2_ac_timings *timings; - const struct lpddr2_min_tck *min_tck; - const struct lpddr2_device_details *cs0_dev_details = - emif_dev_details->cs0_device_details; - const struct lpddr2_device_details *cs1_dev_details = - emif_dev_details->cs1_device_details; - const struct lpddr2_device_timings *cs0_dev_timings = - emif_dev_details->cs0_device_timings; - - emif_assert(emif_dev_details); - emif_assert(regs); - /* - * You can not have a device on CS1 without one on CS0 - * So configuring EMIF without a device on CS0 doesn't - * make sense - */ - emif_assert(cs0_dev_details); - emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); - /* - * If there is a device on CS1 it should be same type as CS0 - * (or NVM. But NVM is not supported in this driver yet) - */ - emif_assert((cs1_dev_details == NULL) || - (cs1_dev_details->type == LPDDR2_TYPE_NVM) || - (cs0_dev_details->type == cs1_dev_details->type)); - emif_assert(freq <= MAX_LPDDR2_FREQ); - - set_ddr_clk_period(freq); - - /* - * The device on CS0 is used for all timing calculations - * There is only one set of registers for timings per EMIF. So, if the - * second CS(CS1) has a device, it should have the same timings as the - * device on CS0 - */ - timings = get_timings_table(cs0_dev_timings->ac_timings, freq); - emif_assert(timings); - min_tck = cs0_dev_timings->min_tck; - - temp = addressing_table_index(cs0_dev_details->type, - cs0_dev_details->density, - cs0_dev_details->io_width); - - emif_assert((temp >= 0)); - addressing = &(addressing_table[temp]); - emif_assert(addressing); - - sys_freq = get_sys_clk_freq(); - - regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, - cs1_dev_details, - addressing, RL_BOOT); - - regs->sdram_config = get_sdram_config_reg(cs0_dev_details, - cs1_dev_details, - addressing, RL_FINAL); - - regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); - - regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); - - regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); - - regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); - - regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); - - regs->temp_alert_config = - get_temp_alert_config(cs1_dev_details, addressing, 0); - - regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, - LPDDR2_VOLTAGE_STABLE); - - regs->emif_ddr_phy_ctlr_1_init = - get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); - - regs->emif_ddr_phy_ctlr_1 = - get_ddr_phy_ctrl_1(freq, RL_FINAL); - - regs->freq = freq; - - print_timing_reg(regs->sdram_config_init); - print_timing_reg(regs->sdram_config); - print_timing_reg(regs->ref_ctrl); - print_timing_reg(regs->sdram_tim1); - print_timing_reg(regs->sdram_tim2); - print_timing_reg(regs->sdram_tim3); - print_timing_reg(regs->read_idle_ctrl); - print_timing_reg(regs->temp_alert_config); - print_timing_reg(regs->zq_config); - print_timing_reg(regs->emif_ddr_phy_ctlr_1); - print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); -} -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ +u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM; +u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN; +u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE; +#endif #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS /* Base AC Timing values specified by JESD209-2 for 400MHz operation */ @@ -691,30 +61,6 @@ static const struct lpddr2_ac_timings timings_jedec_400_mhz = { .tFAW = 50 }; -/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */ -static const struct lpddr2_ac_timings timings_jedec_333_mhz = { - .max_freq = 333000000, - .RL = 5, - .tRPab = 21, - .tRCD = 18, - .tWR = 15, - .tRASmin = 42, - .tRRD = 10, - .tWTRx2 = 15, - .tXSR = 140, - .tXPx2 = 15, - .tRFCab = 130, - .tRTPx2 = 15, - .tCKE = 3, - .tCKESR = 15, - .tZQCS = 90, - .tZQCL = 360, - .tZQINIT = 1000, - .tDQSCKMAXx2 = 11, - .tRASmax = 70, - .tFAW = 50 -}; - /* Base AC Timing values specified by JESD209-2 for 200 MHz operation */ static const struct lpddr2_ac_timings timings_jedec_200_mhz = { .max_freq = 200000000, @@ -764,7 +110,6 @@ static const struct lpddr2_min_tck min_tck_jedec = { static const struct lpddr2_ac_timings const* jedec_ac_timings[MAX_NUM_SPEEDBINS] = { &timings_jedec_200_mhz, - &timings_jedec_333_mhz, &timings_jedec_400_mhz }; @@ -782,473 +127,3 @@ void emif_get_device_timings(u32 emif_nr, *cs1_device_timings = &jedec_default_timings; } #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ - -#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -const char *get_lpddr2_type(u8 type_id) -{ - switch (type_id) { - case LPDDR2_TYPE_S4: - return "LPDDR2-S4"; - case LPDDR2_TYPE_S2: - return "LPDDR2-S2"; - default: - return NULL; - } -} - -const char *get_lpddr2_io_width(u8 width_id) -{ - switch (width_id) { - case LPDDR2_IO_WIDTH_8: - return "x8"; - case LPDDR2_IO_WIDTH_16: - return "x16"; - case LPDDR2_IO_WIDTH_32: - return "x32"; - default: - return NULL; - } -} - -const char *get_lpddr2_manufacturer(u32 manufacturer) -{ - switch (manufacturer) { - case LPDDR2_MANUFACTURER_SAMSUNG: - return "Samsung"; - case LPDDR2_MANUFACTURER_QIMONDA: - return "Qimonda"; - case LPDDR2_MANUFACTURER_ELPIDA: - return "Elpida"; - case LPDDR2_MANUFACTURER_ETRON: - return "Etron"; - case LPDDR2_MANUFACTURER_NANYA: - return "Nanya"; - case LPDDR2_MANUFACTURER_HYNIX: - return "Hynix"; - case LPDDR2_MANUFACTURER_MOSEL: - return "Mosel"; - case LPDDR2_MANUFACTURER_WINBOND: - return "Winbond"; - case LPDDR2_MANUFACTURER_ESMT: - return "ESMT"; - case LPDDR2_MANUFACTURER_SPANSION: - return "Spansion"; - case LPDDR2_MANUFACTURER_SST: - return "SST"; - case LPDDR2_MANUFACTURER_ZMOS: - return "ZMOS"; - case LPDDR2_MANUFACTURER_INTEL: - return "Intel"; - case LPDDR2_MANUFACTURER_NUMONYX: - return "Numonyx"; - case LPDDR2_MANUFACTURER_MICRON: - return "Micron"; - default: - return NULL; - } -} - -static void display_sdram_details(u32 emif_nr, u32 cs, - struct lpddr2_device_details *device) -{ - const char *mfg_str; - const char *type_str; - char density_str[10]; - u32 density; - - debug("EMIF%d CS%d\t", emif_nr, cs); - - if (!device) { - debug("None\n"); - return; - } - - mfg_str = get_lpddr2_manufacturer(device->manufacturer); - type_str = get_lpddr2_type(device->type); - - density = lpddr2_density_2_size_in_mbytes[device->density]; - if ((density / 1024 * 1024) == density) { - density /= 1024; - sprintf(density_str, "%d GB", density); - } else - sprintf(density_str, "%d MB", density); - if (mfg_str && type_str) - debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); -} - -static u8 is_lpddr2_sdram_present(u32 base, u32 cs, - struct lpddr2_device_details *lpddr2_device) -{ - u32 mr = 0, temp; - - mr = get_mr(base, cs, LPDDR2_MR0); - if (mr > 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; - if (temp) { - /* Not SDRAM */ - return 0; - } - temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; - - if (temp) { - /* DNV supported - But DNV is only supported for NVM */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR4); - if (mr > 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR5); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - if (!get_lpddr2_manufacturer(mr)) { - /* Manufacturer not identified */ - return 0; - } - lpddr2_device->manufacturer = mr; - - mr = get_mr(base, cs, LPDDR2_MR6); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR7); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR8); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; - if (!get_lpddr2_type(temp)) { - /* Not SDRAM */ - return 0; - } - lpddr2_device->type = temp; - - temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; - if (temp > LPDDR2_DENSITY_32Gb) { - /* Density not supported */ - return 0; - } - lpddr2_device->density = temp; - - temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; - if (!get_lpddr2_io_width(temp)) { - /* IO width unsupported value */ - return 0; - } - lpddr2_device->io_width = temp; - - /* - * If all the above tests pass we should - * have a device on this chip-select - */ - return 1; -} - -struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, - struct lpddr2_device_details *lpddr2_dev_details) -{ - u32 phy; - u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2; - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - if (!lpddr2_dev_details) - return NULL; - - /* Do the minimum init for mode register accesses */ - if (!running_from_sdram()) { - phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); - writel(phy, &emif->emif_ddr_phy_ctrl_1); - } - - if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) - return NULL; - - display_sdram_details(emif_num(base), cs, lpddr2_dev_details); - - return lpddr2_dev_details; -} -#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ - -static void do_sdram_init(u32 base) -{ - const struct emif_regs *regs; - u32 in_sdram, emif_nr; - - debug(">>do_sdram_init() %x\n", base); - - in_sdram = running_from_sdram(); - emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2; - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - emif_get_reg_dump(emif_nr, ®s); - if (!regs) { - debug("EMIF: reg dump not provided\n"); - return; - } -#else - /* - * The user has not provided the register values. We need to - * calculate it based on the timings and the DDR frequency - */ - struct emif_device_details dev_details; - struct emif_regs calculated_regs; - - /* - * Get device details: - * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set - * - Obtained from user otherwise - */ - struct lpddr2_device_details cs0_dev_details, cs1_dev_details; - emif_reset_phy(base); - dev_details.cs0_device_details = emif_get_device_details(base, CS0, - &cs0_dev_details); - dev_details.cs1_device_details = emif_get_device_details(base, CS1, - &cs1_dev_details); - emif_reset_phy(base); - - /* Return if no devices on this EMIF */ - if (!dev_details.cs0_device_details && - !dev_details.cs1_device_details) { - emif_sizes[emif_nr - 1] = 0; - return; - } - - if (!in_sdram) - emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details); - - /* - * Get device timings: - * - Default timings specified by JESD209-2 if - * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set - * - Obtained from user otherwise - */ - emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, - &dev_details.cs1_device_timings); - - /* Calculate the register values */ - emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs); - regs = &calculated_regs; -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ - - /* - * Initializing the LPDDR2 device can not happen from SDRAM. - * Changing the timing registers in EMIF can happen(going from one - * OPP to another) - */ - if (!in_sdram) - lpddr2_init(base, regs); - - /* Write to the shadow registers */ - emif_update_timings(base, regs); - - debug("<<do_sdram_init() %x\n", base); -} - -static void emif_post_init_config(u32 base) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 omap4_rev = omap_revision(); - - /* reset phy on ES2.0 */ - if (omap4_rev == OMAP4430_ES2_0) - emif_reset_phy(base); - - /* Put EMIF back in smart idle on ES1.0 */ - if (omap4_rev == OMAP4430_ES1_0) - writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); -} - -static void dmm_init(u32 base) -{ - const struct dmm_lisa_map_regs *lisa_map_regs; - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - emif_get_dmm_regs(&lisa_map_regs); -#else - u32 emif1_size, emif2_size, mapped_size, section_map = 0; - u32 section_cnt, sys_addr; - struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; - - mapped_size = 0; - section_cnt = 3; - sys_addr = CONFIG_SYS_SDRAM_BASE; - emif1_size = emif_sizes[0]; - emif2_size = emif_sizes[1]; - debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); - - if (!emif1_size && !emif2_size) - return; - - /* symmetric interleaved section */ - if (emif1_size && emif2_size) { - mapped_size = min(emif1_size, emif2_size); - section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; - section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT; - /* only MSB */ - section_map |= (sys_addr >> 24) << - OMAP44XX_SYS_ADDR_SHIFT; - section_map |= get_dmm_section_size_map(mapped_size * 2) - << OMAP44XX_SYS_SIZE_SHIFT; - lis_map_regs_calculated.dmm_lisa_map_3 = section_map; - emif1_size -= mapped_size; - emif2_size -= mapped_size; - sys_addr += (mapped_size * 2); - section_cnt--; - } - - /* - * Single EMIF section(we can have a maximum of 1 single EMIF - * section- either EMIF1 or EMIF2 or none, but not both) - */ - if (emif1_size) { - section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; - section_map |= get_dmm_section_size_map(emif1_size) - << OMAP44XX_SYS_SIZE_SHIFT; - /* only MSB */ - section_map |= (mapped_size >> 24) << - OMAP44XX_SDRC_ADDR_SHIFT; - /* only MSB */ - section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT; - section_cnt--; - } - if (emif2_size) { - section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; - section_map |= get_dmm_section_size_map(emif2_size) << - OMAP44XX_SYS_SIZE_SHIFT; - /* only MSB */ - section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT; - /* only MSB */ - section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT; - section_cnt--; - } - - if (section_cnt == 2) { - /* Only 1 section - either symmetric or single EMIF */ - lis_map_regs_calculated.dmm_lisa_map_3 = section_map; - lis_map_regs_calculated.dmm_lisa_map_2 = 0; - lis_map_regs_calculated.dmm_lisa_map_1 = 0; - } else { - /* 2 sections - 1 symmetric, 1 single EMIF */ - lis_map_regs_calculated.dmm_lisa_map_2 = section_map; - lis_map_regs_calculated.dmm_lisa_map_1 = 0; - } - - /* TRAP for invalid TILER mappings in section 0 */ - lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; - - lisa_map_regs = &lis_map_regs_calculated; -#endif - struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)base; - - writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); - - writel(lisa_map_regs->dmm_lisa_map_3, - &hw_lisa_map_regs->dmm_lisa_map_3); - writel(lisa_map_regs->dmm_lisa_map_2, - &hw_lisa_map_regs->dmm_lisa_map_2); - writel(lisa_map_regs->dmm_lisa_map_1, - &hw_lisa_map_regs->dmm_lisa_map_1); - writel(lisa_map_regs->dmm_lisa_map_0, - &hw_lisa_map_regs->dmm_lisa_map_0); - - if (omap_revision() >= OMAP4460_ES1_0) { - hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)OMAP44XX_MA_LISA_MAP_BASE; - - writel(lisa_map_regs->dmm_lisa_map_3, - &hw_lisa_map_regs->dmm_lisa_map_3); - writel(lisa_map_regs->dmm_lisa_map_2, - &hw_lisa_map_regs->dmm_lisa_map_2); - writel(lisa_map_regs->dmm_lisa_map_1, - &hw_lisa_map_regs->dmm_lisa_map_1); - writel(lisa_map_regs->dmm_lisa_map_0, - &hw_lisa_map_regs->dmm_lisa_map_0); - } -} - -/* - * SDRAM initialization: - * SDRAM initialization has two parts: - * 1. Configuring the SDRAM device - * 2. Update the AC timings related parameters in the EMIF module - * (1) should be done only once and should not be done while we are - * running from SDRAM. - * (2) can and should be done more than once if OPP changes. - * Particularly, this may be needed when we boot without SPL and - * and using Configuration Header(CH). ROM code supports only at 50% OPP - * at boot (low power boot). So u-boot has to switch to OPP100 and update - * the frequency. So, - * Doing (1) and (2) makes sense - first time initialization - * Doing (2) and not (1) makes sense - OPP change (when using CH) - * Doing (1) and not (2) doen't make sense - * See do_sdram_init() for the details - */ -void sdram_init(void) -{ - u32 in_sdram, size_prog, size_detect; - - debug(">>sdram_init()\n"); - - if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) - return; - - in_sdram = running_from_sdram(); - debug("in_sdram = %d\n", in_sdram); - - if (!in_sdram) { - bypass_dpll(&prcm->cm_clkmode_dpll_core); - } - - do_sdram_init(OMAP44XX_EMIF1); - do_sdram_init(OMAP44XX_EMIF2); - - if (!in_sdram) { - dmm_init(OMAP44XX_DMM_LISA_MAP_BASE); - emif_post_init_config(OMAP44XX_EMIF1); - emif_post_init_config(OMAP44XX_EMIF2); - - } - - /* for the shadow registers to take effect */ - freq_update_core(); - - /* Do some testing after the init */ - if (!in_sdram) { - size_prog = omap4_sdram_size(); - size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - size_prog); - /* Compare with the size programmed */ - if (size_detect != size_prog) { - printf("SDRAM: identified size not same as expected" - " size identified: %x expected: %x\n", - size_detect, - size_prog); - } else - debug("get_ram_size() successful"); - } - - debug("<<sdram_init()\n"); -} diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c new file mode 100644 index 0000000000..37a86b4c2f --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -0,0 +1,180 @@ +/* + * + * Common functions for OMAP4 based boards + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Author : + * Aneesh V <aneesh@ti.com> + * Steve Sakoman <steve@sakoman.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/armv7.h> +#include <asm/arch/cpu.h> +#include <asm/arch/sys_proto.h> +#include <asm/sizes.h> +#include <asm/emif.h> +#include <asm/arch/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; + +static const struct gpio_bank gpio_bank_44xx[6] = { + { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; + +#ifdef CONFIG_SPL_BUILD +/* + * Some tuning of IOs for optimal power and performance + */ +void do_io_settings(void) +{ + u32 lpddr2io; + struct control_lpddr2io_regs *lpddr2io_regs = + (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; + struct omap4_sys_ctrl_regs *const ctrl = + (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; + + u32 omap4_rev = omap_revision(); + + if (omap4_rev == OMAP4430_ES1_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; + else if (omap4_rev == OMAP4430_ES2_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; + else + lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; + + /* EMIF1 */ + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0); + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1); + /* No pull for GR10 as per hw team's recommendation */ + writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, + &lpddr2io_regs->control_lpddr2io1_2); + writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3); + + /* EMIF2 */ + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0); + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1); + /* No pull for GR10 as per hw team's recommendation */ + writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, + &lpddr2io_regs->control_lpddr2io2_2); + writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3); + + /* + * Some of these settings (TRIM values) come from eFuse and are + * in turn programmed in the eFuse at manufacturing time after + * calibration of the device. Do the software over-ride only if + * the device is not correctly trimmed + */ + if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) { + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + &ctrl->control_ldosram_iva_voltage_ctrl); + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + &ctrl->control_ldosram_mpu_voltage_ctrl); + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + &ctrl->control_ldosram_core_voltage_ctrl); + } + + /* + * Over-ride the register + * i. unconditionally for all 4430 + * ii. only if un-trimmed for 4460 + */ + if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_1)) + writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1); + + if (!readl(&ctrl->control_efuse_2)) + writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2); +} +#endif + +void init_omap_revision(void) +{ + /* + * For some of the ES2/ES1 boards ID_CODE is not reliable: + * Also, ES1 and ES2 have different ARM revisions + * So use ARM revision for identification + */ + unsigned int arm_rev = cortex_rev(); + + switch (arm_rev) { + case MIDR_CORTEX_A9_R0P1: + *omap4_revision = OMAP4430_ES1_0; + break; + case MIDR_CORTEX_A9_R1P2: + switch (readl(CONTROL_ID_CODE)) { + case OMAP4_CONTROL_ID_CODE_ES2_0: + *omap4_revision = OMAP4430_ES2_0; + break; + case OMAP4_CONTROL_ID_CODE_ES2_1: + *omap4_revision = OMAP4430_ES2_1; + break; + case OMAP4_CONTROL_ID_CODE_ES2_2: + *omap4_revision = OMAP4430_ES2_2; + break; + default: + *omap4_revision = OMAP4430_ES2_0; + break; + } + break; + case MIDR_CORTEX_A9_R1P3: + *omap4_revision = OMAP4430_ES2_3; + break; + case MIDR_CORTEX_A9_R2P10: + switch (readl(CONTROL_ID_CODE)) { + case OMAP4460_CONTROL_ID_CODE_ES1_1: + *omap4_revision = OMAP4460_ES1_1; + break; + case OMAP4460_CONTROL_ID_CODE_ES1_0: + default: + *omap4_revision = OMAP4460_ES1_0; + break; + } + break; + default: + *omap4_revision = OMAP4430_SILICON_ID_INVALID; + break; + } +} + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + set_pl310_ctrl_reg(1); +} + +void v7_outer_cache_disable(void) +{ + set_pl310_ctrl_reg(0); +} +#endif diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h deleted file mode 100644 index b9403910c9..0000000000 --- a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h +++ /dev/null @@ -1,83 +0,0 @@ - /* - * (C) Copyright 2010 - * Texas Instruments Incorporated, <www.ti.com> - * - * Balaji Krishnamoorthy <balajitk@ti.com> - * Aneesh V <aneesh@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP4_MUX_DATA_H_ -#define _OMAP4_MUX_DATA_H_ - -#include <asm/arch/mux_omap4.h> - -const struct pad_conf_entry core_padconf_array_essential[] = { - -{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ -{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ -{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ -{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ -{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ -{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ -{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ -{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ -{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ -{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ -{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ -{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ -{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ -{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ -{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ -{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ -{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ -{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ -{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ -{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ -{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ -{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ -{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ -{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ -{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ -{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ -{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ -{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ -{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ -{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ -{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ -{UART3_TX_IRTX, (M0)} /* uart3_tx */ - -}; - -const struct pad_conf_entry wkup_padconf_array_essential[] = { - -{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ -{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ -{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ - -}; - -const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { - -{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */ - -}; - - -#endif /* _OMAP4_MUX_DATA_H_ */ diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index edc5326c38..a5ec7d3dcc 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -26,7 +26,7 @@ * MA 02111-1307 USA */ -#include <asm/arch/emif.h> +#include <asm/emif.h> #include <asm/arch/sys_proto.h> /* diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile new file mode 100644 index 0000000000..f8ca9ac367 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2010 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS += hwinit.o +COBJS += clocks.o +COBJS += emif.o +COBJS += sdram_elpida.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c new file mode 100644 index 0000000000..dd882a202e --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -0,0 +1,432 @@ +/* + * + * Clock initialization for OMAP5 + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * Sricharan R <r.sricharan@ti.com> + * + * Based on previous work by: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * Rajendra Nayak <rnayak@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/omap_common.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/utils.h> +#include <asm/omap_gpio.h> + +#ifndef CONFIG_SPL_BUILD +/* + * printing to console doesn't work unless + * this code is executed from SPL + */ +#define printf(fmt, args...) +#define puts(s) +#endif + +struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100; + +const u32 sys_clk_array[8] = { + 12000000, /* 12 MHz */ + 0, /* NA */ + 16800000, /* 16.8 MHz */ + 19200000, /* 19.2 MHz */ + 26000000, /* 26 MHz */ + 0, /* NA */ + 38400000, /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { + {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = { + {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { + {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = { + {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { + {266, 2, 1, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {570, 8, 1, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ + {665, 11, 1, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ + {532, 12, 1, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {665, 23, 1, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { + {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ + {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ + {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { + {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { + {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ + {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ + {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ + {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1 +}; + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +void setup_post_dividers(u32 *const base, const struct dpll_params *params) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, &dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, &dpll_regs->cm_div_m3_dpll); + if (params->h11 >= 0) + writel(params->h11, &dpll_regs->cm_div_h11_dpll); + if (params->h12 >= 0) + writel(params->h12, &dpll_regs->cm_div_h12_dpll); + if (params->h13 >= 0) + writel(params->h13, &dpll_regs->cm_div_h13_dpll); + if (params->h14 >= 0) + writel(params->h14, &dpll_regs->cm_div_h14_dpll); + if (params->h22 >= 0) + writel(params->h22, &dpll_regs->cm_div_h22_dpll); + if (params->h23 >= 0) + writel(params->h23, &dpll_regs->cm_div_h23_dpll); +} + +const struct dpll_params *get_mpu_dpll_params(void) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &mpu_dpll_params_1100mhz[sysclk_ind]; +} + +const struct dpll_params *get_core_dpll_params(void) +{ + u32 sysclk_ind = get_sys_clk_index(); + + /* Configuring the DDR to be at 532mhz */ + return &core_dpll_params_2128mhz_ddr266[sysclk_ind]; + +} + +const struct dpll_params *get_per_dpll_params(void) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &per_dpll_params_768mhz[sysclk_ind]; +} + +const struct dpll_params *get_iva_dpll_params(void) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &iva_dpll_params_2330mhz[sysclk_ind]; +} + +const struct dpll_params *get_usb_dpll_params(void) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &usb_dpll_params_1920mhz[sysclk_ind]; +} + +const struct dpll_params *get_abe_dpll_params(void) +{ +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + u32 sysclk_ind = get_sys_clk_index(); + return &abe_dpll_params_sysclk_196608khz[sysclk_ind]; +#else + return &abe_dpll_params_32k_196608khz; +#endif +} + +/* + * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva + * We set the maximum voltages allowed here because Smart-Reflex is not + * enabled in bootloader. Voltage initialization in the kernel will set + * these to the nominal values after enabling Smart-Reflex + */ +void scale_vcores(void) +{ + u32 volt; + + setup_sri2c(); + + /* Enable 1.22V from TPS for vdd_mpu */ + volt = 1220; + do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt); + + /* VCORE 1 - for vdd_core */ + volt = 1000; + do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + + /* VCORE 2 - for vdd_MM */ + volt = 1125; + do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); +} + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +void enable_basic_clocks(void) +{ + u32 *const clk_domains_essential[] = { + &prcm->cm_l4per_clkstctrl, + &prcm->cm_l3init_clkstctrl, + &prcm->cm_memif_clkstctrl, + &prcm->cm_l4cfg_clkstctrl, + 0 + }; + + u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_memif_emif_1_clkctrl, + &prcm->cm_memif_emif_2_clkctrl, + &prcm->cm_l4cfg_l4_cfg_clkctrl, + &prcm->cm_wkup_gpio1_clkctrl, + &prcm->cm_l4per_gpio2_clkctrl, + &prcm->cm_l4per_gpio3_clkctrl, + &prcm->cm_l4per_gpio4_clkctrl, + &prcm->cm_l4per_gpio5_clkctrl, + &prcm->cm_l4per_gpio6_clkctrl, + 0 + }; + + u32 *const clk_modules_explicit_en_essential[] = { + &prcm->cm_wkup_gptimer1_clkctrl, + &prcm->cm_l3init_hsmmc1_clkctrl, + &prcm->cm_l3init_hsmmc2_clkctrl, + &prcm->cm_l4per_gptimer2_clkctrl, + &prcm->cm_wkup_wdtimer2_clkctrl, + &prcm->cm_l4per_uart3_clkctrl, + &prcm->cm_l4per_i2c1_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, + GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, + GPTIMER1_CLKCTRL_CLKSEL_MASK); + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void enable_basic_uboot_clocks(void) +{ + u32 *const clk_domains_essential[] = { + 0 + }; + + u32 *const clk_modules_hw_auto_essential[] = { + 0 + }; + + u32 *const clk_modules_explicit_en_essential[] = { + &prcm->cm_l4per_mcspi1_clkctrl, + &prcm->cm_l4per_i2c2_clkctrl, + &prcm->cm_l4per_i2c3_clkctrl, + &prcm->cm_l4per_i2c4_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +/* + * Enable non-essential clock domains, modules and + * do some additional special settings needed + */ +void enable_non_essential_clocks(void) +{ + u32 *const clk_domains_non_essential[] = { + &prcm->cm_mpu_m3_clkstctrl, + &prcm->cm_ivahd_clkstctrl, + &prcm->cm_dsp_clkstctrl, + &prcm->cm_dss_clkstctrl, + &prcm->cm_sgx_clkstctrl, + &prcm->cm1_abe_clkstctrl, + &prcm->cm_c2c_clkstctrl, + &prcm->cm_cam_clkstctrl, + &prcm->cm_dss_clkstctrl, + &prcm->cm_sdma_clkstctrl, + 0 + }; + + u32 *const clk_modules_hw_auto_non_essential[] = { + &prcm->cm_mpu_m3_mpu_m3_clkctrl, + &prcm->cm_ivahd_ivahd_clkctrl, + &prcm->cm_ivahd_sl2_clkctrl, + &prcm->cm_dsp_dsp_clkctrl, + &prcm->cm_l3_2_gpmc_clkctrl, + &prcm->cm_l3instr_l3_3_clkctrl, + &prcm->cm_l3instr_l3_instr_clkctrl, + &prcm->cm_l3instr_intrconn_wp1_clkctrl, + &prcm->cm_l3init_hsi_clkctrl, + &prcm->cm_l3init_hsusbtll_clkctrl, + 0 + }; + + u32 *const clk_modules_explicit_en_non_essential[] = { + &prcm->cm1_abe_aess_clkctrl, + &prcm->cm1_abe_pdm_clkctrl, + &prcm->cm1_abe_dmic_clkctrl, + &prcm->cm1_abe_mcasp_clkctrl, + &prcm->cm1_abe_mcbsp1_clkctrl, + &prcm->cm1_abe_mcbsp2_clkctrl, + &prcm->cm1_abe_mcbsp3_clkctrl, + &prcm->cm1_abe_slimbus_clkctrl, + &prcm->cm1_abe_timer5_clkctrl, + &prcm->cm1_abe_timer6_clkctrl, + &prcm->cm1_abe_timer7_clkctrl, + &prcm->cm1_abe_timer8_clkctrl, + &prcm->cm1_abe_wdt3_clkctrl, + &prcm->cm_l4per_gptimer9_clkctrl, + &prcm->cm_l4per_gptimer10_clkctrl, + &prcm->cm_l4per_gptimer11_clkctrl, + &prcm->cm_l4per_gptimer3_clkctrl, + &prcm->cm_l4per_gptimer4_clkctrl, + &prcm->cm_l4per_hdq1w_clkctrl, + &prcm->cm_l4per_mcspi2_clkctrl, + &prcm->cm_l4per_mcspi3_clkctrl, + &prcm->cm_l4per_mcspi4_clkctrl, + &prcm->cm_l4per_mmcsd3_clkctrl, + &prcm->cm_l4per_mmcsd4_clkctrl, + &prcm->cm_l4per_mmcsd5_clkctrl, + &prcm->cm_l4per_uart1_clkctrl, + &prcm->cm_l4per_uart2_clkctrl, + &prcm->cm_l4per_uart4_clkctrl, + &prcm->cm_wkup_keyboard_clkctrl, + &prcm->cm_wkup_wdtimer2_clkctrl, + &prcm->cm_cam_iss_clkctrl, + &prcm->cm_cam_fdif_clkctrl, + &prcm->cm_dss_dss_clkctrl, + &prcm->cm_sgx_sgx_clkctrl, + &prcm->cm_l3init_hsusbhost_clkctrl, + &prcm->cm_l3init_fsusb_clkctrl, + 0 + }; + + /* Enable optional functional clock for ISS */ + setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable all optional functional clocks of DSS */ + setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); + + do_enable_clocks(clk_domains_non_essential, + clk_modules_hw_auto_non_essential, + clk_modules_explicit_en_non_essential, + 0); + + /* Put camera module in no sleep mode */ + clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, + CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk new file mode 100644 index 0000000000..639f699045 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/config.mk @@ -0,0 +1,28 @@ +# +# Copyright 2011 Linaro Limited +# See file CREDITS for list of people who contributed to this +# project. +# +# Aneesh V <annesh@ti.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +ifdef CONFIG_SPL_BUILD +ALL-y += $(OBJTREE)/MLO +else +ALL-y += $(obj)u-boot.img +endif diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c new file mode 100644 index 0000000000..8019ffe3d3 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/emif.c @@ -0,0 +1,105 @@ +/* + * EMIF programming + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> for OMAP4 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/emif.h> +#include <asm/arch/sys_proto.h> +#include <asm/utils.h> + +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) +static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM; +static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN; +static u32 *const emif_sizes = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_SIZE; +#endif + +#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +/* Base AC Timing values specified by JESD209-2 for 532MHz operation */ +static const struct lpddr2_ac_timings timings_jedec_532_mhz = { + .max_freq = 532000000, + .RL = 8, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +/* + * Min tCK values specified by JESD209-2 + * Min tCK specifies the minimum duration of some AC timing parameters in terms + * of the number of cycles. If the calculated number of cycles based on the + * absolute time value is less than the min tCK value, min tCK value should + * be used instead. This typically happens at low frequencies. + */ +static const struct lpddr2_min_tck min_tck_jedec = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings const* + jedec_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_jedec_532_mhz +}; + +static const struct lpddr2_device_timings jedec_default_timings = { + .ac_timings = jedec_ac_timings, + .min_tck = &min_tck_jedec +}; + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + /* Assume Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &jedec_default_timings; + *cs1_device_timings = NULL; +} +#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c new file mode 100644 index 0000000000..fa8e390c17 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -0,0 +1,78 @@ +/* + * + * Functions for omap5 based boards. + * + * (C) Copyright 2011 + * Texas Instruments, <www.ti.com> + * + * Author : + * Aneesh V <aneesh@ti.com> + * Steve Sakoman <steve@sakoman.com> + * Sricharan <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/armv7.h> +#include <asm/arch/cpu.h> +#include <asm/arch/sys_proto.h> +#include <asm/sizes.h> +#include <asm/utils.h> +#include <asm/arch/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 *const omap5_revision = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV; + +static struct gpio_bank gpio_bank_54xx[6] = { + { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; + +#ifdef CONFIG_SPL_BUILD +/* + * Some tuning of IOs for optimal power and performance + */ +void do_io_settings(void) +{ +} +#endif + +void init_omap_revision(void) +{ + /* + * For some of the ES2/ES1 boards ID_CODE is not reliable: + * Also, ES1 and ES2 have different ARM revisions + * So use ARM revision for identification + */ + unsigned int rev = cortex_rev(); + + switch (rev) { + case MIDR_CORTEX_A15_R0P0: + *omap5_revision = OMAP5430_ES1_0; + default: + *omap5_revision = OMAP5430_SILICON_ID_INVALID; + } +} diff --git a/arch/arm/cpu/armv7/omap5/sdram_elpida.c b/arch/arm/cpu/armv7/omap5/sdram_elpida.c new file mode 100644 index 0000000000..ad198e6d1b --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/sdram_elpida.c @@ -0,0 +1,178 @@ +/* + * Timing and Organization details of the Elpida parts used in OMAP5 + * EVM + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * Sricharan R <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/emif.h> +#include <asm/arch/sys_proto.h> + +/* + * This file provides details of the LPDDR2 SDRAM parts used on OMAP5 + * EVM. Since the parts used and geometry are identical for + * evm for a given OMAP5 revision, this information is kept + * here instead of being in board directory. However the key functions + * exported are weakly linked so that they can be over-ridden in the board + * directory if there is a OMAP5 board in the future that uses a different + * memory device or geometry. + * + * For any new board with different memory devices over-ride one or more + * of the following functions as per the CONFIG flags you intend to enable: + * - emif_get_reg_dump() + * - emif_get_dmm_regs() + * - emif_get_device_details() + * - emif_get_device_timings() + */ + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + +const struct emif_regs emif_regs_elpida_532_mhz_1cs = { + .sdram_config_init = 0x80801aB2, + .sdram_config = 0x808022B2, + .ref_ctrl = 0x0000081A, + .sdram_tim1 = 0x772F6873, + .sdram_tim2 = 0x304A129A, + .sdram_tim3 = 0x02F7E45F, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x000B3215, + .temp_alert_config = 0x08000A05, + .emif_ddr_phy_ctlr_1_init = 0x0E38200D, + .emif_ddr_phy_ctlr_1 = 0x0E38200D +}; + +const struct dmm_lisa_map_regs lisa_map_4G_x_1_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300 +}; + +static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) +{ + *regs = &emif_regs_elpida_532_mhz_1cs; +} +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) + __attribute__((weak, alias("emif_get_reg_dump_sdp"))); + +static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs + **dmm_lisa_regs) +{ + *dmm_lisa_regs = &lisa_map_4G_x_1_x_2; +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) + __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); + +#else + +static const struct lpddr2_device_details elpida_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + +static void emif_get_device_details_sdp(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) +{ + /* EMIF1 & EMIF2 have identical configuration */ + *cs0_device_details = elpida_4G_S4_details; + + /* Nothing is conected on cs1 */ + cs1_device_details = NULL; +} + +void emif_get_device_details(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) + __attribute__((weak, alias("emif_get_device_details_sdp"))); + +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + +#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +static const struct lpddr2_ac_timings timings_jedec_532_mhz = { + .max_freq = 532000000, + .RL = 8, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_min_tck min_tck_elpida = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_jedec_532_mhz +}; + +static const struct lpddr2_device_timings elpida_4G_S4_timings = { + .ac_timings = elpida_ac_timings, + .min_tck = &min_tck_elpida, +}; + +void emif_get_device_timings_sdp(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + /* Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &elpida_4G_S4_timings; + *cs1_device_timings = NULL; +} + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) + __attribute__((weak, alias("emif_get_device_timings_sdp"))); + +#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index ff95b84f55..58d279e003 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -82,7 +82,6 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) unsigned long period; unsigned long tcon; unsigned long tcnt; - unsigned long timer_rate_hz; unsigned long tcmp; /* @@ -100,7 +99,6 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) /* Check to see if we are changing the clock rate of the PWM */ tin_rate = pwm_calc_tin(pwm_id, period); - timer_rate_hz = tin_rate; tin_ns = NS_IN_HZ / tin_rate; tcnt = period_ns / tin_ns; diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index db8e9d2f18..d23dc9d719 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -32,6 +32,7 @@ #include <asm-offsets.h> #include <config.h> #include <version.h> +#include <asm/system.h> .globl _start _start: b reset @@ -143,29 +144,22 @@ reset: orr r0, r0, #0xd3 msr cpsr,r0 -#if defined(CONFIG_OMAP34XX) - /* Copy vectors to mask ROM indirect addr */ - adr r0, _start @ r0 <- current position of code - add r0, r0, #4 @ skip reset vector - mov r2, #64 @ r2 <- size to copy - add r2, r0, r2 @ r2 <- source end address - mov r1, #SRAM_OFFSET0 @ build vect addr - mov r3, #SRAM_OFFSET1 - add r1, r1, r3 - mov r3, #SRAM_OFFSET2 - add r1, r1, r3 -next: - ldmia r0!, {r3 - r10} @ copy from source address [r0] - stmia r1!, {r3 - r10} @ copy to target address [r1] - cmp r0, r2 @ until source end address [r2] - bne next @ loop until equal */ -#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) - /* No need to copy/exec the clock code - DPLL adjust already done - * in NAND/oneNAND Boot. - */ - bl cpy_clk_code @ put dpll adjust code behind vectors -#endif /* NAND Boot */ +/* + * Setup vector: + * (OMAP4 spl TEXT_BASE is not 32 byte aligned. + * Continue to use ROM code vector only in OMAP4 spl) + */ +#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) + /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register + bic r0, #CR_V @ V = 0 + mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register + + /* Set vector address in CP15 VBAR register */ + ldr r0, =_start + mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif + /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile index e8b59a30c9..e088832560 100644 --- a/arch/arm/cpu/pxa/Makefile +++ b/arch/arm/cpu/pxa/Makefile @@ -27,7 +27,12 @@ LIB = $(obj)lib$(CPU).o START = start.o -COBJS += cpu.o +COBJS-$(CONFIG_CPU_PXA25X) = pxa2xx.o +COBJS-$(CONFIG_CPU_PXA27X) = pxa2xx.o + +COBJS-y += cpuinfo.o + +COBJS = $(COBJS-y) COBJS += pxafb.o COBJS += timer.o COBJS += usb.o diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c new file mode 100644 index 0000000000..f1cdd408eb --- /dev/null +++ b/arch/arm/cpu/pxa/cpuinfo.c @@ -0,0 +1,132 @@ +/* + * PXA CPU information display + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <linux/compiler.h> + +#define CPU_MASK_PXA_REVID 0x00f + +#define CPU_MASK_PXA_PRODID 0x3f0 +#define CPU_VALUE_PXA25X 0x100 +#define CPU_VALUE_PXA27X 0x110 + +static uint32_t pxa_get_cpuid(void) +{ + uint32_t cpuid; + asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid)); + return cpuid; +} + +int cpu_is_pxa25x(void) +{ + uint32_t id = pxa_get_cpuid(); + id &= CPU_MASK_PXA_PRODID; + return id == CPU_VALUE_PXA25X; +} + +int cpu_is_pxa27x(void) +{ + uint32_t id = pxa_get_cpuid(); + id &= CPU_MASK_PXA_PRODID; + return id == CPU_VALUE_PXA27X; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +static const char *pxa25x_get_revision(void) +{ + static __maybe_unused const char * const revs_25x[] = { "A0" }; + static __maybe_unused const char * const revs_26x[] = { + "A0", "B0", "B1" + }; + static const char *unknown = "Unknown"; + uint32_t id; + + if (!cpu_is_pxa25x()) + return unknown; + + id = pxa_get_cpuid() & CPU_MASK_PXA_REVID; + +/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */ +#ifdef CONFIG_CPU_PXA26X + switch (id) { + case 3: return revs_26x[0]; + case 5: return revs_26x[1]; + case 6: return revs_26x[2]; + } +#else + if (id == 6) + return revs_25x[0]; +#endif + return unknown; +} + +static const char *pxa27x_get_revision(void) +{ + static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" }; + static const char *unknown = "Unknown"; + uint32_t id; + + if (!cpu_is_pxa27x()) + return unknown; + + id = pxa_get_cpuid() & CPU_MASK_PXA_REVID; + + if ((id == 5) || (id == 6) || (id > 7)) + return unknown; + + /* Cap the special PXA270 C5 case. */ + if (id == 7) + id = 5; + + return rev[id]; +} + +static int print_cpuinfo_pxa2xx(void) +{ + if (cpu_is_pxa25x()) { + puts("Marvell PXA25x rev. "); + puts(pxa25x_get_revision()); + } else if (cpu_is_pxa27x()) { + puts("Marvell PXA27x rev. "); + puts(pxa27x_get_revision()); + } else + return -EINVAL; + + puts("\n"); + + return 0; +} + +int print_cpuinfo(void) +{ + int ret; + + puts("CPU: "); + + ret = print_cpuinfo_pxa2xx(); + if (!ret) + return ret; + + return ret; +} +#endif diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/pxa2xx.c index df351c7fbc..09e8177f7b 100644 --- a/arch/arm/cpu/pxa/cpu.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -26,88 +26,52 @@ * MA 02111-1307 USA */ -/* - * CPU specific code - */ - #include <asm/io.h> #include <asm/system.h> #include <command.h> #include <common.h> #include <asm/arch/pxa-regs.h> -static void cache_flush(void); +/* Flush I/D-cache */ +static void cache_flush(void) +{ + unsigned long i = 0; -int cleanup_before_linux (void) + asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i)); +} + +int cleanup_before_linux(void) { /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux + * This function is called just before we call Linux. It prepares + * the processor for Linux by just disabling everything that can + * disturb booting Linux. */ - disable_interrupts (); - - /* turn off I-cache */ + disable_interrupts(); icache_disable(); dcache_disable(); - - /* flush I-cache */ cache_flush(); - return (0); -} - -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -#ifndef CONFIG_CPU_MONAHANS -void set_GPIO_mode(int gpio_mode) -{ - int gpio = gpio_mode & GPIO_MD_MASK_NR; - int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; - int val; - - /* This below changes direction setting of GPIO "gpio" */ - val = readl(GPDR(gpio)); - - if (gpio_mode & GPIO_MD_MASK_DIR) - val |= GPIO_bit(gpio); - else - val &= ~GPIO_bit(gpio); - - writel(val, GPDR(gpio)); - - /* This below updates only AF of GPIO "gpio" */ - val = readl(GAFR(gpio)); - val &= ~(0x3 << (((gpio) & 0xf) * 2)); - val |= fn << (((gpio) & 0xf) * 2); - writel(val, GAFR(gpio)); + return 0; } -#endif /* CONFIG_CPU_MONAHANS */ void pxa_wait_ticks(int ticks) { writel(0, OSCR); while (readl(OSCR) < ticks) - asm volatile("":::"memory"); + asm volatile("" : : : "memory"); } inline void writelrb(uint32_t val, uint32_t addr) { writel(val, addr); - asm volatile("":::"memory"); + asm volatile("" : : : "memory"); readl(addr); - asm volatile("":::"memory"); + asm volatile("" : : : "memory"); } -void pxa_dram_init(void) +void pxa2xx_dram_init(void) { uint32_t tmp; int i; @@ -201,7 +165,7 @@ void pxa_dram_init(void) */ for (i = 9; i >= 0; i--) { writel(i, 0xa0000000); - asm volatile("":::"memory"); + asm volatile("" : : : "memory"); } /* * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). @@ -234,21 +198,21 @@ void pxa_gpio_setup(void) writel(CONFIG_SYS_GPSR0_VAL, GPSR0); writel(CONFIG_SYS_GPSR1_VAL, GPSR1); writel(CONFIG_SYS_GPSR2_VAL, GPSR2); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) writel(CONFIG_SYS_GPSR3_VAL, GPSR3); #endif writel(CONFIG_SYS_GPCR0_VAL, GPCR0); writel(CONFIG_SYS_GPCR1_VAL, GPCR1); writel(CONFIG_SYS_GPCR2_VAL, GPCR2); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) writel(CONFIG_SYS_GPCR3_VAL, GPCR3); #endif writel(CONFIG_SYS_GPDR0_VAL, GPDR0); writel(CONFIG_SYS_GPDR1_VAL, GPDR1); writel(CONFIG_SYS_GPDR2_VAL, GPDR2); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) writel(CONFIG_SYS_GPDR3_VAL, GPDR3); #endif @@ -258,7 +222,7 @@ void pxa_gpio_setup(void) writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U); writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L); writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L); writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U); #endif @@ -270,7 +234,7 @@ void pxa_interrupt_setup(void) { writel(0, ICLR); writel(0, ICMR); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) writel(0, ICLR2); writel(0, ICMR2); #endif @@ -278,18 +242,14 @@ void pxa_interrupt_setup(void) void pxa_clock_setup(void) { -#ifndef CONFIG_CPU_MONAHANS writel(CONFIG_SYS_CKEN, CKEN); writel(CONFIG_SYS_CCCR, CCCR); - asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2)); -#else -/* Set CKENA/CKENB/ACCR for MH */ -#endif + asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2)); /* enable the 32Khz oscillator for RTC and PowerManager */ writel(OSCC_OON, OSCC); - while(!(readl(OSCC) & OSCC_OOK)) - asm volatile("":::"memory"); + while (!(readl(OSCC) & OSCC_OOK)) + asm volatile("" : : : "memory"); } void pxa_wakeup(void) @@ -302,17 +262,16 @@ void pxa_wakeup(void) /* Wakeup */ if (rcsr & RCSR_SMR) { writel(PSSR_PH, PSSR); - pxa_dram_init(); + pxa2xx_dram_init(); icache_disable(); dcache_disable(); - asm volatile("mov pc, %0"::"r"(readl(PSPR))); + asm volatile("mov pc, %0" : : "r"(readl(PSPR))); } } int arch_cpu_init(void) { pxa_gpio_setup(); -/* pxa_wait_ticks(0x8000); */ pxa_wakeup(); pxa_interrupt_setup(); pxa_clock_setup(); @@ -321,10 +280,22 @@ int arch_cpu_init(void) void i2c_clk_enable(void) { - /* set the global I2C clock on */ -#ifdef CONFIG_CPU_MONAHANS - writel(readl(CKENB) | (CKENB_4_I2C), CKENB); -#else + /* Set the global I2C clock on */ writel(readl(CKEN) | CKEN14_I2C, CKEN); -#endif +} + +void reset_cpu(ulong ignored) __attribute__((noreturn)); + +void reset_cpu(ulong ignored) +{ + uint32_t tmp; + + setbits_le32(OWER, OWER_WME); + + tmp = readl(OSCR); + tmp += 0x1000; + writel(tmp, OSMR3); + + for (;;) + ; } diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 6191a73a54..ba0de8f1db 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -1,14 +1,20 @@ /* - * armboot - Startup Code for XScale + * armboot - Startup Code for XScale CPU-core * * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> + * Copyright (C) 2001 Marius Groger <mag@sysgo.de> + * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> + * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> - * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> - * Copyright (c) 2010 Marek Vasut <marek.vasut@gmail.com> + * Copyright (C) 2003 Kshitij <kshitij@ti.com> + * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> + * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> + * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> * * See file CREDITS for list of people who contributed to this * project. @@ -32,14 +38,12 @@ #include <asm-offsets.h> #include <config.h> #include <version.h> -#include <asm/arch/pxa-regs.h> -/* takes care the CP15 update has taken place */ -.macro CPWAIT reg -mrc p15,0,\reg,c2,c0,0 -mov \reg,\reg -sub pc,pc,#4 -.endm +#ifdef CONFIG_CPU_PXA25X +#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) +#error "Init SP address must be set to 0xfffff800 for PXA250" +#endif +#endif .globl _start _start: b reset @@ -77,26 +81,38 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ #endif /* CONFIG_SPL_BUILD */ +.global _end_vect +_end_vect: .balignl 16,0xdeadbeef - - /* + ************************************************************************* + * * Startup Code (reset vector) * - * do important init only if we don't start from RAM! - * - relocate armboot to RAM - * - setup stack - * - jump to second stage + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* */ .globl _TEXT_BASE _TEXT_BASE: +#ifdef CONFIG_SPL_BUILD + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. */ .globl _bss_start_ofs _bss_start_ofs: @@ -120,9 +136,8 @@ IRQ_STACK_START: .globl FIQ_STACK_START FIQ_STACK_START: .word 0x0badc0de -#endif /* CONFIG_USE_IRQ */ +#endif -#ifndef CONFIG_SPL_BUILD /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN IRQ_STACK_START_IN: @@ -141,95 +156,23 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 - /* - * Enable MMU to use DCache as DRAM - */ - /* Domain access -- enable for all CPs */ - ldr r0, =0x0000ffff - mcr p15, 0, r0, c3, c0, 0 - - /* Point TTBR to MMU table */ - ldr r0, =mmu_table - adr r2, _start - orr r0, r2 - mcr p15, 0, r0, c2, c0, 0 - -/* !!! Hereby, check if the code is running from SRAM !!! */ -/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code - * is linked to 0x0 too, so this makes things easier. */ - cmp r2, #0x5c000000 - - ldreq r1, [r0] - orreq r1, r2 - streq r1, [r0] - - /* Kick in MMU, ICache, DCache, BTB */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, #0x1b00 - bic r0, #0x0087 - orr r0, #0x1800 - orr r0, #0x0005 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - /* Unlock Icache, Dcache */ - mcr p15, 0, r0, c9, c1, 1 - mcr p15, 0, r0, c9, c2, 1 - - /* Flush Icache, Dcache, BTB */ - mcr p15, 0, r0, c7, c7, 0 - - /* Unlock I-TLB, D-TLB */ - mcr p15, 0, r0, c10, c4, 1 - mcr p15, 0, r0, c10, c8, 1 - - /* Flush TLB */ - mcr p15, 0, r0, c8, c7, 0 - /* Allocate 4096 bytes of Dcache as RAM */ - - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - - mov r4, #0x00 - mov r5, #0x00 - mov r2, #0x01 - mcr p15, 0, r0, c9, c2, 0 - CPWAIT r0 - - /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ - mov r0, #128 - mov r1, #0xa0000000 -alloc: - mcr p15, 0, r1, c7, c2, 5 - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - strd r4, [r1], #8 - strd r4, [r1], #8 - strd r4, [r1], #8 - strd r4, [r1], #8 - subs r0, #0x01 - bne alloc - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - mov r2, #0x00 - mcr p15, 0, r2, c9, c2, 0 - CPWAIT r0 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif - /* Jump to 0x0 ( + offset) if running from SRAM */ - adr r0, zerojmp - bic r0, #0x5c000000 - mov pc, r0 -zerojmp: +#ifdef CONFIG_CPU_PXA25X + bl lock_cache_for_stack +#endif /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 + ldr r0, =0x00000000 bl board_init_f /*------------------------------------------------------------------------------*/ - +#ifndef CONFIG_SPL_BUILD /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -247,6 +190,11 @@ relocate_code: stack_setup: mov sp, r4 +/* Disable the Dcache RAM lock for stack now */ +#ifdef CONFIG_CPU_PXA25X + bl cpu_init_crit +#endif + adr r0, _start cmp r0, r6 beq clear_bss /* skip relocation */ @@ -254,13 +202,11 @@ stack_setup: ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ - stmfd sp!, {r0-r12} copy_loop: - ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */ - stmia r1!, {r3-r5, r7-r11} /* copy to target address [r1] */ + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r1!, {r9-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop - ldmfd sp!, {r0-r12} #ifndef CONFIG_SPL_BUILD /* @@ -275,13 +221,13 @@ copy_loop: ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ fixloop: - ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ - add r0, r9 /* r0 <- location to fix up in RAM */ + ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ + add r0, r0, r9 /* r0 <- location to fix up in RAM */ ldr r1, [r2, #4] and r7, r1, #0xff - cmp r7, #23 /* relative fixup? */ + cmp r7, #23 /* relative fixup? */ beq fixrel - cmp r7, #2 /* absolute fixup? */ + cmp r7, #2 /* absolute fixup? */ beq fixabs /* ignore unknown type of fixup */ b fixnext @@ -298,10 +244,10 @@ fixrel: add r1, r1, r9 fixnext: str r1, [r0] - add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ + add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop -#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif clear_bss: #ifndef CONFIG_SPL_BUILD @@ -322,15 +268,16 @@ clbss_l:str r2, [r0] /* clear loop... */ * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ -#ifdef CONFIG_ONENAND_IPL - ldr r0, _start_oneboot_ofs +#ifdef CONFIG_ONENAND_SPL + ldr r0, _onenand_boot_ofs mov pc, r0 -_start_oneboot_ofs - : .word start_oneboot +_onenand_boot_ofs: + .word onenand_boot #else +jump_2_ram: ldr r0, _board_init_r_ofs - adr r1, _start + ldr r1, _TEXT_BASE add lr, r0, r1 add lr, lr, r9 /* setup parameters for board_init_r */ @@ -341,7 +288,7 @@ _start_oneboot_ofs _board_init_r_ofs: .word board_init_r - _start -#endif /* CONFIG_ONENAND_IPL */ +#endif _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -349,43 +296,50 @@ _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start - -#else /* CONFIG_SPL_BUILD */ - -/****************************************************************************/ -/* */ -/* the actual reset code for OneNAND IPL */ -/* */ -/****************************************************************************/ - -#ifndef CONFIG_PXA27X -#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM #endif +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ -reset: - /* Set CPU to SVC32 mode */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0x13 - msr cpsr,r0 - - /* Point stack at the end of SRAM and leave 32 words for abort-stack */ - ldr sp, =0x5c03ff80 - - /* Start OneNAND IPL */ - ldr pc, =start_oneboot + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 -#endif /* CONFIG_SPL_BUILD */ + mov pc, lr /* back to my caller */ +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ #ifndef CONFIG_SPL_BUILD -/****************************************************************************/ -/* */ -/* Interrupt handling */ -/* */ -/****************************************************************************/ - -/* IRQ stack frame */ - +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ +@ +@ IRQ stack frame. +@ #define S_FRAME_SIZE 72 #define S_OLD_R0 68 @@ -409,37 +363,36 @@ reset: #define S_R0 0 #define MODE_SVC 0x13 +#define I_BIT 0x80 - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ + ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack add r5, sp, #S_SP mov r1, lr - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ - mov r0, sp + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) .endm - - /* use irq_save_user_regs / irq_restore_user_regs for */ - /* IRQ/FIQ handling */ - .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 mov r0, sp .endm @@ -452,16 +405,28 @@ reset: .endm .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_bad_stack_swi + sub r13, r13, #4 @ space on current stack for scratch reg. + str r0, [r13] @ save R0's value. + ldr r0, IRQ_STACK_START_IN @ get data regions start + str lr, [r0] @ save caller lr in position 0 of saved stack + mrs r0, spsr @ get the spsr + str lr, [r0, #4] @ save spsr in position 1 of saved stack + ldr r0, [r13] @ restore r0 + add r13, r13, #4 @ pop stack entry .endm .macro get_irq_stack @ setup IRQ stack @@ -471,21 +436,17 @@ reset: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm -#endif /* CONFIG_SPL_BUILD - - -/****************************************************************************/ -/* */ -/* exception handlers */ -/* */ -/****************************************************************************/ +#endif /* CONFIG_SPL_BUILD */ +/* + * exception handlers + */ #ifdef CONFIG_SPL_BUILD .align 5 do_hang: - ldr sp, _TEXT_BASE /* use 32 words abort stack */ + ldr sp, _TEXT_BASE /* use 32 words about stack */ bl hang /* hang and never return */ -#else +#else /* !CONFIG_SPL_BUILD */ .align 5 undefined_instruction: get_bad_stack @@ -494,7 +455,7 @@ undefined_instruction: .align 5 software_interrupt: - get_bad_stack + get_bad_stack_swi bad_save_user_regs bl do_software_interrupt @@ -528,11 +489,12 @@ irq: .align 5 fiq: get_fiq_stack - irq_save_user_regs /* someone ought to write a more */ - bl do_fiq /* effiction fiq_save_user_regs */ + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq irq_restore_user_regs -#else /* !CONFIG_USE_IRQ */ +#else .align 5 irq: @@ -545,63 +507,99 @@ fiq: get_bad_stack bad_save_user_regs bl do_fiq + +#endif + .align 5 #endif /* CONFIG_SPL_BUILD */ -#endif /* CONFIG_USE_IRQ */ -/****************************************************************************/ -/* */ -/* Reset function: the PXA250 doesn't have a reset function, so we have to */ -/* perform a watchdog timeout for a soft reset. */ -/* */ -/****************************************************************************/ -/* Operating System Timer */ -.align 5 -.globl reset_cpu - /* FIXME: this code is PXA250 specific. How is this handled on */ - /* other XScale processors? */ +/* + * Enable MMU to use DCache as DRAM. + * + * This is useful on PXA25x and PXA26x in early bootstages, where there is no + * other possible memory available to hold stack. + */ +#ifdef CONFIG_CPU_PXA25X +.macro CPWAIT reg + mrc p15, 0, \reg, c2, c0, 0 + mov \reg, \reg + sub pc, pc, #4 +.endm +lock_cache_for_stack: + /* Domain access -- enable for all CPs */ + ldr r0, =0x0000ffff + mcr p15, 0, r0, c3, c0, 0 -reset_cpu: + /* Point TTBR to MMU table */ + ldr r0, =mmutable + mcr p15, 0, r0, c2, c0, 0 - /* We set OWE:WME (watchdog enable) and wait until timeout happens */ + /* Kick in MMU, ICache, DCache, BTB */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, #0x1b00 + bic r0, #0x0087 + orr r0, #0x1800 + orr r0, #0x0005 + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 - ldr r0, =OWER - ldr r1, [r0] - orr r1, r1, #0x0001 /* bit0: WME */ - str r1, [r0] + /* Unlock Icache, Dcache */ + mcr p15, 0, r0, c9, c1, 1 + mcr p15, 0, r0, c9, c2, 1 - /* OS timer does only wrap every 1165 seconds, so we have to set */ - /* the match register as well. */ + /* Flush Icache, Dcache, BTB */ + mcr p15, 0, r0, c7, c7, 0 - ldr r0, =OSCR - ldr r1, [r0] /* read OS timer */ - add r1, r1, #0x800 /* let OSMR3 match after */ - add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ - ldr r0, =OSMR3 - str r1, [r0] + /* Unlock I-TLB, D-TLB */ + mcr p15, 0, r0, c10, c4, 1 + mcr p15, 0, r0, c10, c8, 1 -reset_endless: + /* Flush TLB */ + mcr p15, 0, r0, c8, c7, 0 - b reset_endless + /* Allocate 4096 bytes of Dcache as RAM */ -#ifndef CONFIG_SPL_BUILD -.section .mmudata, "a" + /* Drain pending loads and stores */ + mcr p15, 0, r0, c7, c10, 4 + + mov r4, #0x00 + mov r5, #0x00 + mov r2, #0x01 + mcr p15, 0, r0, c9, c2, 0 + CPWAIT r0 + + /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ + mov r0, #128 + ldr r1, =0xfffff000 + +alloc: + mcr p15, 0, r1, c7, c2, 5 + /* Drain pending loads and stores */ + mcr p15, 0, r0, c7, c10, 4 + strd r4, [r1], #8 + strd r4, [r1], #8 + strd r4, [r1], #8 + strd r4, [r1], #8 + subs r0, #0x01 + bne alloc + /* Drain pending loads and stores */ + mcr p15, 0, r0, c7, c10, 4 + mov r2, #0x00 + mcr p15, 0, r2, c9, c2, 0 + CPWAIT r0 + + mov pc, lr + +.section .mmutable, "a" +mmutable: .align 14 - .globl mmu_table -mmu_table: - /* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */ + /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ .set __base, 0 - .rept 0xa00 + .rept 0xfff .word (__base << 20) | 0xc12 .set __base, __base + 1 .endr - /* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */ - .word (0xa00 << 20) | 0x1c1e - - .set __base, 0xa01 - .rept 0x1000 - 0xa01 - .word (__base << 20) | 0xc12 - .set __base, __base + 1 - .endr -#endif /* CONFIG_SPL_BUILD */ + /* 0xfff00000 : 1:1, cached mapping */ + .word (0xfff << 20) | 0x1c1e +#endif /* CONFIG_CPU_PXA25X */ diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index 2866745472..b7b0da98a4 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -1,11 +1,7 @@ /* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> + * Marvell PXA2xx/3xx timer driver * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> * * See file CREDITS for list of people who contributed to this * project. @@ -31,55 +27,63 @@ #include <common.h> #include <div64.h> -#ifdef CONFIG_USE_IRQ -#error: interrupts not implemented yet -#endif +DECLARE_GLOBAL_DATA_PTR; + +#define TIMER_LOAD_VAL 0xffffffff + +#define timestamp (gd->tbl) +#define lastinc (gd->lastinc) -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define TIMER_FREQ_HZ 3250000 -#elif defined(CONFIG_PXA250) -#define TIMER_FREQ_HZ 3686400 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define TIMER_FREQ_HZ 3250000 +#elif defined(CONFIG_CPU_PXA25X) +#define TIMER_FREQ_HZ 3686400 #else #error "Timer frequency unknown - please config PXA CPU type" #endif -static inline unsigned long long tick_to_time(unsigned long long tick) +static unsigned long long tick_to_time(unsigned long long tick) { - tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ_HZ); - return tick; + return tick * CONFIG_SYS_HZ / TIMER_FREQ_HZ; } -static inline unsigned long long us_to_tick(unsigned long long us) +static unsigned long long us_to_tick(unsigned long long us) { - us = us * TIMER_FREQ_HZ + 999999; - do_div(us, 1000000); - return us; + return (us * TIMER_FREQ_HZ) / 1000000; } -int timer_init (void) +int timer_init(void) { writel(0, OSCR); - return 0; } -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void __udelay (unsigned long usec) +unsigned long long get_ticks(void) { - udelay_masked (usec); + /* Current tick value */ + uint32_t now = readl(OSCR); + + if (now >= lastinc) { + /* + * Normal mode (non roll) + * Move stamp forward with absolute diff ticks + */ + timestamp += (now - lastinc); + } else { + /* We have rollover of incrementer */ + timestamp += (TIMER_LOAD_VAL - lastinc) + now; + } + + lastinc = now; + return timestamp; } -ulong get_timer_masked (void) +ulong get_timer(ulong base) { - return tick_to_time(get_ticks()); + return tick_to_time(get_ticks()) - base; } -void udelay_masked (unsigned long usec) +void __udelay(unsigned long usec) { unsigned long long tmp; ulong tmo; @@ -89,25 +93,4 @@ void udelay_masked (unsigned long usec) while (get_ticks() < tmp) /* loop till event */ /*NOP*/; - -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return readl(OSCR); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = TIMER_FREQ_HZ; - return tbclk; } diff --git a/arch/arm/cpu/pxa/u-boot.lds b/arch/arm/cpu/pxa/u-boot.lds index e163369bc3..e86e7818e6 100644 --- a/arch/arm/cpu/pxa/u-boot.lds +++ b/arch/arm/cpu/pxa/u-boot.lds @@ -63,6 +63,12 @@ SECTIONS *(.dynsym) } + . = ALIGN(4096); + + .mmutable : { + *(.mmutable) + } + _end = .; .bss __rel_dyn_start (OVERLAY) : { diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c index 0311d5e997..83022e2e56 100644 --- a/arch/arm/cpu/pxa/usb.c +++ b/arch/arm/cpu/pxa/usb.c @@ -24,7 +24,7 @@ #include <common.h> #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) +# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) #include <asm/arch/pxa-regs.h> #include <asm/io.h> @@ -37,7 +37,7 @@ int usb_cpu_init(void) writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); udelay(100); #endif -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) /* Enable USB host clock. */ writel(readl(CKEN) | CKEN10_USBHOST, CKEN); #endif @@ -58,7 +58,7 @@ int usb_cpu_init(void) #if defined(CONFIG_CPU_MONAHANS) writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); #endif -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); #endif writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); @@ -78,7 +78,7 @@ int usb_cpu_stop(void) #if defined(CONFIG_CPU_MONAHANS) writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); #endif -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR); #endif writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR); @@ -88,7 +88,7 @@ int usb_cpu_stop(void) writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA); udelay(100); #endif -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) /* Disable USB host clock. */ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); #endif @@ -101,5 +101,5 @@ int usb_cpu_init_fail(void) return usb_cpu_stop(); } -# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */ +# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */ #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index 330edd83c5..8282f46199 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h index 5af6fdc251..7bf363ab16 100644 --- a/arch/arm/include/asm/arch-at91/at91cap9.h +++ b/arch/arm/include/asm/arch-at91/at91cap9.h @@ -1,7 +1,7 @@ /* * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h] * - * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> + * Copyright (C) 2007 Stelian Pop <stelian@popies.net> * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> * Copyright (C) 2007 Atmel Corporation. * diff --git a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h index 22b7e9b8f4..a9b5ae00a0 100644 --- a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h @@ -1,7 +1,7 @@ /* * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h] * - * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> + * Copyright (C) 2007 Stelian Pop <stelian@popies.net> * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> * Copyright (C) 2006 Atmel Corporation. * diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h index f6453275c4..1e8522b839 100644 --- a/arch/arm/include/asm/arch-at91/clk.h +++ b/arch/arm/include/asm/arch-at91/clk.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index 36af571a5b..85c2889e5c 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/include/asm/arch-davinci/aintc_defs.h index 8f37053209..38f814c018 100644 --- a/arch/arm/include/asm/arch-davinci/aintc_defs.h +++ b/arch/arm/include/asm/arch-davinci/aintc_defs.h @@ -47,4 +47,6 @@ struct dv_aintc_regs { #define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE) +#define DV_AINTC_INTCTL_IDMODE (1 << 2) + #endif /* _DV_AINTC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h index 0bc7f76f1c..e489c47475 100644 --- a/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h +++ b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h @@ -1,5 +1,5 @@ /* - * SoC-specific lowlevel code for AM1808 and similar chips + * SoC-specific lowlevel code for DA850 * * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. @@ -21,24 +21,24 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#ifndef __AM1808_LOWLEVEL_H -#define __AM1808_LOWLEVEL_H +#ifndef __DA850_LOWLEVEL_H +#define __DA850_LOWLEVEL_H /* NOR Boot Configuration Word Field Descriptions */ -#define AM1808_NORBOOT_COPY_XK(X) ((X - 1) << 8) -#define AM1808_NORBOOT_METHOD_DIRECT (1 << 4) -#define AM1808_NORBOOT_16BIT (1 << 0) +#define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8) +#define DA850_NORBOOT_METHOD_DIRECT (1 << 4) +#define DA850_NORBOOT_16BIT (1 << 0) #define dv_maskbits(addr, val) \ writel((readl(addr) & val), addr) -void am1808_waitloop(unsigned long loopcnt); -int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult); -void am1808_lpc_transition(unsigned char pscnum, unsigned char module, +void da850_waitloop(unsigned long loopcnt); +int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult); +void da850_lpc_transition(unsigned char pscnum, unsigned char module, unsigned char domain, unsigned char state); -int am1808_ddr_setup(unsigned int freq); -void am1808_psc_init(void); -void am1808_pinmux_ctl(unsigned long offset, unsigned long mask, +int da850_ddr_setup(void); +void da850_psc_init(void); +void da850_pinmux_ctl(unsigned long offset, unsigned long mask, unsigned long value); -#endif /* #ifndef __AM1808_LOWLEVEL_H */ +#endif /* #ifndef __DA850_LOWLEVEL_H */ diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h index 211b76920f..cbac8031b4 100644 --- a/arch/arm/include/asm/arch-davinci/davinci_misc.h +++ b/arch/arm/include/asm/arch-davinci/davinci_misc.h @@ -45,9 +45,6 @@ struct pinmux_resource { .n_pins = ARRAY_SIZE(item) \ } -#define HAWKBOARD_KICK0_UNLOCK 0x83e70b13 -#define HAWKBOARD_KICK1_UNLOCK 0x95a4f1e0 - struct lpsc_resource { const int lpsc_no; }; diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/include/asm/arch-davinci/ddr2_defs.h index 1b9430ce6b..4f943b81b3 100644 --- a/arch/arm/include/asm/arch-davinci/ddr2_defs.h +++ b/arch/arm/include/asm/arch-davinci/ddr2_defs.h @@ -63,6 +63,7 @@ struct dv_ddr2_regs_ctrl { #define DV_DDR_SDTMR2_RASMAX_SHIFT 27 #define DV_DDR_SDTMR2_XP_SHIFT 25 +#define DV_DDR_SDTMR2_ODT_SHIFT 23 #define DV_DDR_SDTMR2_XSNR_SHIFT 16 #define DV_DDR_SDTMR2_XSRD_SHIFT 8 #define DV_DDR_SDTMR2_RTP_SHIFT 5 @@ -84,6 +85,9 @@ struct dv_ddr2_regs_ctrl { #define DV_DDR_SDCR_IBANK_SHIFT 4 #define DV_DDR_SDCR_PAGESIZE_SHIFT 0 +#define DV_DDR_SDRCR_LPMODEN (1 << 31) +#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30) + #define DV_DDR_SRCR_LPMODEN_SHIFT 31 #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30 diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h index ea52888ff4..8a17de9054 100644 --- a/arch/arm/include/asm/arch-davinci/emac_defs.h +++ b/arch/arm/include/asm/arch-davinci/emac_defs.h @@ -84,295 +84,6 @@ #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ #endif -/* Ethernet Min/Max packet size */ -#define EMAC_MIN_ETHERNET_PKT_SIZE 60 -#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 -#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ - -/* Number of RX packet buffers - * NOTE: Only 1 buffer supported as of now - */ -#define EMAC_MAX_RX_BUFFERS 10 - - -/*********************************************** - ******** Internally used macros *************** - ***********************************************/ - -#define EMAC_CH_TX 1 -#define EMAC_CH_RX 0 - -/* Each descriptor occupies 4 words, lets start RX desc's at 0 and - * reserve space for 64 descriptors max - */ -#define EMAC_RX_DESC_BASE 0x0 -#define EMAC_TX_DESC_BASE 0x1000 - -/* EMAC Teardown value */ -#define EMAC_TEARDOWN_VALUE 0xfffffffc - -/* MII Status Register */ -#define MII_STATUS_REG 1 - -/* Number of statistics registers */ -#define EMAC_NUM_STATS 36 - - -/* EMAC Descriptor */ -typedef volatile struct _emac_desc -{ - u_int32_t next; /* Pointer to next descriptor in chain */ - u_int8_t *buffer; /* Pointer to data buffer */ - u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ - u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ -} emac_desc; - -/* CPPI bit positions */ -#define EMAC_CPPI_SOP_BIT (0x80000000) -#define EMAC_CPPI_EOP_BIT (0x40000000) -#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) -#define EMAC_CPPI_EOQ_BIT (0x10000000) -#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) -#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) - -#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) - -#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) -#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) -#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) -#define EMAC_MACCONTROL_GIGFORCE (1 << 17) -#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) - -#define EMAC_MAC_ADDR_MATCH (1 << 19) -#define EMAC_MAC_ADDR_IS_VALID (1 << 20) - -#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) -#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) - - -#define MDIO_CONTROL_IDLE (0x80000000) -#define MDIO_CONTROL_ENABLE (0x40000000) -#define MDIO_CONTROL_FAULT_ENABLE (0x40000) -#define MDIO_CONTROL_FAULT (0x80000) -#define MDIO_USERACCESS0_GO (0x80000000) -#define MDIO_USERACCESS0_WRITE_READ (0x0) -#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) -#define MDIO_USERACCESS0_ACK (0x20000000) - -/* Ethernet MAC Registers Structure */ -typedef struct { - dv_reg TXIDVER; - dv_reg TXCONTROL; - dv_reg TXTEARDOWN; - u_int8_t RSVD0[4]; - dv_reg RXIDVER; - dv_reg RXCONTROL; - dv_reg RXTEARDOWN; - u_int8_t RSVD1[100]; - dv_reg TXINTSTATRAW; - dv_reg TXINTSTATMASKED; - dv_reg TXINTMASKSET; - dv_reg TXINTMASKCLEAR; - dv_reg MACINVECTOR; - u_int8_t RSVD2[12]; - dv_reg RXINTSTATRAW; - dv_reg RXINTSTATMASKED; - dv_reg RXINTMASKSET; - dv_reg RXINTMASKCLEAR; - dv_reg MACINTSTATRAW; - dv_reg MACINTSTATMASKED; - dv_reg MACINTMASKSET; - dv_reg MACINTMASKCLEAR; - u_int8_t RSVD3[64]; - dv_reg RXMBPENABLE; - dv_reg RXUNICASTSET; - dv_reg RXUNICASTCLEAR; - dv_reg RXMAXLEN; - dv_reg RXBUFFEROFFSET; - dv_reg RXFILTERLOWTHRESH; - u_int8_t RSVD4[8]; - dv_reg RX0FLOWTHRESH; - dv_reg RX1FLOWTHRESH; - dv_reg RX2FLOWTHRESH; - dv_reg RX3FLOWTHRESH; - dv_reg RX4FLOWTHRESH; - dv_reg RX5FLOWTHRESH; - dv_reg RX6FLOWTHRESH; - dv_reg RX7FLOWTHRESH; - dv_reg RX0FREEBUFFER; - dv_reg RX1FREEBUFFER; - dv_reg RX2FREEBUFFER; - dv_reg RX3FREEBUFFER; - dv_reg RX4FREEBUFFER; - dv_reg RX5FREEBUFFER; - dv_reg RX6FREEBUFFER; - dv_reg RX7FREEBUFFER; - dv_reg MACCONTROL; - dv_reg MACSTATUS; - dv_reg EMCONTROL; - dv_reg FIFOCONTROL; - dv_reg MACCONFIG; - dv_reg SOFTRESET; - u_int8_t RSVD5[88]; - dv_reg MACSRCADDRLO; - dv_reg MACSRCADDRHI; - dv_reg MACHASH1; - dv_reg MACHASH2; - dv_reg BOFFTEST; - dv_reg TPACETEST; - dv_reg RXPAUSE; - dv_reg TXPAUSE; - u_int8_t RSVD6[16]; - dv_reg RXGOODFRAMES; - dv_reg RXBCASTFRAMES; - dv_reg RXMCASTFRAMES; - dv_reg RXPAUSEFRAMES; - dv_reg RXCRCERRORS; - dv_reg RXALIGNCODEERRORS; - dv_reg RXOVERSIZED; - dv_reg RXJABBER; - dv_reg RXUNDERSIZED; - dv_reg RXFRAGMENTS; - dv_reg RXFILTERED; - dv_reg RXQOSFILTERED; - dv_reg RXOCTETS; - dv_reg TXGOODFRAMES; - dv_reg TXBCASTFRAMES; - dv_reg TXMCASTFRAMES; - dv_reg TXPAUSEFRAMES; - dv_reg TXDEFERRED; - dv_reg TXCOLLISION; - dv_reg TXSINGLECOLL; - dv_reg TXMULTICOLL; - dv_reg TXEXCESSIVECOLL; - dv_reg TXLATECOLL; - dv_reg TXUNDERRUN; - dv_reg TXCARRIERSENSE; - dv_reg TXOCTETS; - dv_reg FRAME64; - dv_reg FRAME65T127; - dv_reg FRAME128T255; - dv_reg FRAME256T511; - dv_reg FRAME512T1023; - dv_reg FRAME1024TUP; - dv_reg NETOCTETS; - dv_reg RXSOFOVERRUNS; - dv_reg RXMOFOVERRUNS; - dv_reg RXDMAOVERRUNS; - u_int8_t RSVD7[624]; - dv_reg MACADDRLO; - dv_reg MACADDRHI; - dv_reg MACINDEX; - u_int8_t RSVD8[244]; - dv_reg TX0HDP; - dv_reg TX1HDP; - dv_reg TX2HDP; - dv_reg TX3HDP; - dv_reg TX4HDP; - dv_reg TX5HDP; - dv_reg TX6HDP; - dv_reg TX7HDP; - dv_reg RX0HDP; - dv_reg RX1HDP; - dv_reg RX2HDP; - dv_reg RX3HDP; - dv_reg RX4HDP; - dv_reg RX5HDP; - dv_reg RX6HDP; - dv_reg RX7HDP; - dv_reg TX0CP; - dv_reg TX1CP; - dv_reg TX2CP; - dv_reg TX3CP; - dv_reg TX4CP; - dv_reg TX5CP; - dv_reg TX6CP; - dv_reg TX7CP; - dv_reg RX0CP; - dv_reg RX1CP; - dv_reg RX2CP; - dv_reg RX3CP; - dv_reg RX4CP; - dv_reg RX5CP; - dv_reg RX6CP; - dv_reg RX7CP; -} emac_regs; - -/* EMAC Wrapper Registers Structure */ -typedef struct { -#ifdef DAVINCI_EMAC_VERSION2 - dv_reg idver; - dv_reg softrst; - dv_reg emctrl; - dv_reg c0rxthreshen; - dv_reg c0rxen; - dv_reg c0txen; - dv_reg c0miscen; - dv_reg c1rxthreshen; - dv_reg c1rxen; - dv_reg c1txen; - dv_reg c1miscen; - dv_reg c2rxthreshen; - dv_reg c2rxen; - dv_reg c2txen; - dv_reg c2miscen; - dv_reg c0rxthreshstat; - dv_reg c0rxstat; - dv_reg c0txstat; - dv_reg c0miscstat; - dv_reg c1rxthreshstat; - dv_reg c1rxstat; - dv_reg c1txstat; - dv_reg c1miscstat; - dv_reg c2rxthreshstat; - dv_reg c2rxstat; - dv_reg c2txstat; - dv_reg c2miscstat; - dv_reg c0rximax; - dv_reg c0tximax; - dv_reg c1rximax; - dv_reg c1tximax; - dv_reg c2rximax; - dv_reg c2tximax; -#else - u_int8_t RSVD0[4100]; - dv_reg EWCTL; - dv_reg EWINTTCNT; -#endif -} ewrap_regs; - -/* EMAC MDIO Registers Structure */ -typedef struct { - dv_reg VERSION; - dv_reg CONTROL; - dv_reg ALIVE; - dv_reg LINK; - dv_reg LINKINTRAW; - dv_reg LINKINTMASKED; - u_int8_t RSVD0[8]; - dv_reg USERINTRAW; - dv_reg USERINTMASKED; - dv_reg USERINTMASKSET; - dv_reg USERINTMASKCLEAR; - u_int8_t RSVD1[80]; - dv_reg USERACCESS0; - dv_reg USERPHYSEL0; - dv_reg USERACCESS1; - dv_reg USERPHYSEL1; -} mdio_regs; - -int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); -int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); - -typedef struct -{ - char name[64]; - int (*init)(int phy_addr); - int (*is_phy_connected)(int phy_addr); - int (*get_link_speed)(int phy_addr); - int (*auto_negotiate)(int phy_addr); -} phy_t; - #define PHY_KSZ8873 (0x00221450) int ksz8873_is_phy_connected(int phy_addr); int ksz8873_get_link_speed(int phy_addr); diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h index b48ec17e97..b9e78a5dbd 100644 --- a/arch/arm/include/asm/arch-davinci/emif_defs.h +++ b/arch/arm/include/asm/arch-davinci/emif_defs.h @@ -70,6 +70,7 @@ struct davinci_emif_regs { #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) +#define DAVINCI_NANDFCR_CS2NAND (1 << 0) /* Chip Select setup */ #define DAVINCI_ABCR_STROBE_SELECT (1 << 31) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index bea14993e6..dd89e84413 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -230,6 +230,9 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_LPSC_CFG5 38 #define DAVINCI_LPSC_GEM 39 #define DAVINCI_LPSC_IMCOP 40 +#define DAVINCI_LPSC_VPSSMASTER 47 +#define DAVINCI_LPSC_MJCP 50 +#define DAVINCI_LPSC_HDVICP 51 #define DAVINCI_DM646X_LPSC_EMAC 14 #define DAVINCI_DM646X_LPSC_UART0 26 @@ -385,6 +388,20 @@ struct davinci_psc_regs { #define PINMUX3 0x01c4000c #define PINMUX4 0x01c40010 +struct davinci_uart_ctrl_regs { + dv_reg revid1; + dv_reg res; + dv_reg pwremu_mgmt; + dv_reg mdr; +}; + +#define DAVINCI_UART_CTRL_BASE 0x28 + +/* UART PWREMU_MGMT definitions */ +#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) +#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) +#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) + #else /* CONFIG_SOC_DA8XX */ struct davinci_pllc_regs { @@ -431,6 +448,7 @@ struct davinci_pllc_regs { enum davinci_clk_ids { DAVINCI_SPI0_CLKID = 2, DAVINCI_UART2_CLKID = 2, + DAVINCI_MMC_CLKID = 2, DAVINCI_MDIO_CLKID = 4, DAVINCI_ARM_CLKID = 6, DAVINCI_PLLM_CLKID = 0xff, @@ -462,12 +480,15 @@ struct davinci_syscfg_regs { #define davinci_syscfg_regs \ ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE) +#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) + /* Emulation suspend bits */ #define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5) #define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) #define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) #define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22) #define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18) +#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) struct davinci_syscfg1_regs { @@ -491,6 +512,9 @@ struct davinci_syscfg1_regs { #define VTP_READY (1 << 15) #define VTP_IOPWRDWN (1 << 14) +#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13 +#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0 + /* Interrupt controller */ struct davinci_aintc_regs { dv_reg revid; @@ -564,4 +588,43 @@ static inline int get_async3_src(void) #include <asm/arch/syscfg_defs.h> #include <asm/arch/timer_defs.h> #endif + +struct davinci_rtc { + dv_reg second; + dv_reg minutes; + dv_reg hours; + dv_reg day; + dv_reg month; /* 0x10 */ + dv_reg year; + dv_reg dotw; + dv_reg resv1; + dv_reg alarmsecond; /* 0x20 */ + dv_reg alarmminute; + dv_reg alarmhour; + dv_reg alarmday; + dv_reg alarmmonth; /* 0x30 */ + dv_reg alarmyear; + dv_reg resv2[2]; + dv_reg ctrl; /* 0x40 */ + dv_reg status; + dv_reg irq; + dv_reg complsb; + dv_reg compmsb; /* 0x50 */ + dv_reg osc; + dv_reg resv3[2]; + dv_reg scratch0; /* 0x60 */ + dv_reg scratch1; + dv_reg scratch2; + dv_reg kick0r; + dv_reg kick1r; /* 0x70 */ +}; + +#define RTC_STATE_BUSY 0x01 +#define RTC_STATE_RUN 0x02 + +#define RTC_KICK0R_WE 0x130be783 +#define RTC_KICK1R_WE 0xe0f1a495 + +#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h new file mode 100644 index 0000000000..07aceaab03 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -0,0 +1,51 @@ +/* + * Pinmux configurations for the DAxxx SoCs + * + * Copyright (C) 2011 OMICRON electronics GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_PINMUX_DEFS_H +#define __ASM_ARCH_PINMUX_DEFS_H + +#include <asm/arch/davinci_misc.h> + +/* SPI pin muxer settings */ +extern const struct pinmux_config spi1_pins_base[3]; +extern const struct pinmux_config spi1_pins_scs0[1]; + +/* UART pin muxer settings */ +extern const struct pinmux_config uart1_pins_txrx[2]; +extern const struct pinmux_config uart2_pins_txrx[2]; +extern const struct pinmux_config uart2_pins_rtscts[2]; + +/* EMAC pin muxer settings*/ +extern const struct pinmux_config emac_pins_rmii[7]; +extern const struct pinmux_config emac_pins_mii[15]; +extern const struct pinmux_config emac_pins_mdio[2]; + +/* I2C pin muxer settings */ +extern const struct pinmux_config i2c0_pins[2]; +extern const struct pinmux_config i2c1_pins[2]; + +/* EMIFA pin muxer settings */ +extern const struct pinmux_config emifa_pins_cs2[1]; +extern const struct pinmux_config emifa_pins_cs3[1]; +extern const struct pinmux_config emifa_pins_cs4[1]; +extern const struct pinmux_config emifa_pins_nand[12]; +extern const struct pinmux_config emifa_pins_nor[43]; + +#endif diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h index 5c309533a2..f1396e3194 100644 --- a/arch/arm/include/asm/arch-davinci/pll_defs.h +++ b/arch/arm/include/asm/arch-davinci/pll_defs.h @@ -57,11 +57,24 @@ struct dv_pll_regs { unsigned int plldiv9; /* 0x174 */ }; +#define PLL_MASTER_LOCK (1 << 4) + +#define PLLCTL_CLOCK_MODE_SHIFT 8 #define PLLCTL_PLLEN (1 << 0) #define PLLCTL_PLLPWRDN (1 << 1) #define PLLCTL_PLLRST (1 << 3) +#define PLLCTL_PLLDIS (1 << 4) #define PLLCTL_PLLENSRC (1 << 5) #define PLLCTL_RES_9 (1 << 8) +#define PLLCTL_EXTCLKSRC (1 << 9) + +#define PLL_POSTDEN (1 << 15) + +#define PLL_SCSCFG3_DIV45PENA (1 << 2) +#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1) + +#define PLL_RSTYPE_POR (1 << 0) +#define PLL_RSTYPE_XWRST (1 << 1) #define PLLSECCTL_TINITZ (1 << 16) #define PLLSECCTL_TENABLE (1 << 17) @@ -69,6 +82,7 @@ struct dv_pll_regs { #define PLLSECCTL_STOPMODE (1 << 22) #define PLLCMD_GOSET (1 << 0) +#define PLLCMD_GOSTAT (1 << 0) #define PLL0_LOCK 0x07000000 #define PLL1_LOCK 0x07000000 diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index eece138b45..7f9449b2d0 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -180,8 +180,8 @@ struct aips_regs { #define IMX_I2C3_BASE (0x43F84000) #define IMX_CAN1_BASE (0x43F88000) #define IMX_CAN2_BASE (0x43F8C000) -#define IMX_UART1_BASE (0x43F90000) -#define IMX_UART2_BASE (0x43F94000) +#define UART1_BASE (0x43F90000) +#define UART2_BASE (0x43F94000) #define IMX_I2C2_BASE (0x43F98000) #define IMX_OWIRE_BASE (0x43F9C000) #define IMX_CSPI1_BASE (0x43FA4000) @@ -197,15 +197,15 @@ struct aips_regs { /* SPBA */ #define IMX_SPBA_BASE (0x50000000) #define IMX_CSPI3_BASE (0x50004000) -#define IMX_UART4_BASE (0x50008000) -#define IMX_UART3_BASE (0x5000C000) +#define UART4_BASE (0x50008000) +#define UART3_BASE (0x5000C000) #define IMX_CSPI2_BASE (0x50010000) #define IMX_SSI2_BASE (0x50014000) #define IMX_ESAI_BASE (0x50018000) #define IMX_ATA_DMA_BASE (0x50020000) #define IMX_SIM1_BASE (0x50024000) #define IMX_SIM2_BASE (0x50028000) -#define IMX_UART5_BASE (0x5002C000) +#define UART5_BASE (0x5002C000) #define IMX_TSC_BASE (0x50030000) #define IMX_SSI1_BASE (0x50034000) #define IMX_FEC_BASE (0x50038000) diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 83ab216665..ced5b2a38c 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -224,10 +224,10 @@ struct fuse_bank0_regs { #define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) #define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) #define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) -#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) -#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) +#define UART1_BASE (0x0a000 + IMX_IO_BASE) +#define UART2_BASE (0x0b000 + IMX_IO_BASE) +#define UART3_BASE (0x0c000 + IMX_IO_BASE) +#define UART4_BASE (0x0d000 + IMX_IO_BASE) #define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) diff --git a/arch/arm/include/asm/arch-mx28/clock.h b/arch/arm/include/asm/arch-mx28/clock.h new file mode 100644 index 0000000000..1700fe3915 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/clock.h @@ -0,0 +1,61 @@ +/* + * Freescale i.MX28 Clock + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_EMI_CLK, + MXC_GPMI_CLK, + MXC_IO0_CLK, + MXC_IO1_CLK, + MXC_SSP0_CLK, + MXC_SSP1_CLK, + MXC_SSP2_CLK, + MXC_SSP3_CLK, +}; + +enum mxs_ioclock { + MXC_IOCLK0 = 0, + MXC_IOCLK1, +}; + +enum mxs_sspclock { + MXC_SSPCLK0 = 0, + MXC_SSPCLK1, + MXC_SSPCLK2, + MXC_SSPCLK3, +}; + +uint32_t mxc_get_clock(enum mxc_clock clk); + +void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq); +void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); +void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq); + +/* Compatibility with the FEC Ethernet driver */ +#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) + +#endif /* __CLOCK_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/dma.h b/arch/arm/include/asm/arch-mx28/dma.h new file mode 100644 index 0000000000..52747e2fbf --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/dma.h @@ -0,0 +1,145 @@ +/* + * Freescale i.MX28 APBH DMA + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __DMA_H__ +#define __DMA_H__ + +#include <linux/list.h> + +#ifndef CONFIG_ARCH_DMA_PIO_WORDS +#define DMA_PIO_WORDS 15 +#else +#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS +#endif + +#define MXS_DMA_ALIGNMENT 32 + +/* + * MXS DMA channels + */ +enum { + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_SSP, + MXS_MAX_DMA_CHANNELS, +}; + +/* + * MXS DMA hardware command. + * + * This structure describes the in-memory layout of an entire DMA command, + * including space for the maximum number of PIO accesses. See the appropriate + * reference manual for a detailed description of what these fields mean to the + * DMA hardware. + */ +#define MXS_DMA_DESC_COMMAND_MASK 0x3 +#define MXS_DMA_DESC_COMMAND_OFFSET 0 +#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0 +#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 +#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 +#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 +#define MXS_DMA_DESC_CHAIN (1 << 2) +#define MXS_DMA_DESC_IRQ (1 << 3) +#define MXS_DMA_DESC_NAND_LOCK (1 << 4) +#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) +#define MXS_DMA_DESC_DEC_SEM (1 << 6) +#define MXS_DMA_DESC_WAIT4END (1 << 7) +#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) +#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9) +#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12) +#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 +#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16) +#define MXS_DMA_DESC_BYTES_OFFSET 16 + +struct mxs_dma_cmd { + unsigned long next; + unsigned long data; + union { + dma_addr_t address; + unsigned long alternate; + }; + unsigned long pio_words[DMA_PIO_WORDS]; +}; + +/* + * MXS DMA command descriptor. + * + * This structure incorporates an MXS DMA hardware command structure, along + * with metadata. + */ +#define MXS_DMA_DESC_FIRST (1 << 0) +#define MXS_DMA_DESC_LAST (1 << 1) +#define MXS_DMA_DESC_READY (1 << 31) + +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; + dma_addr_t address; + void *buffer; + struct list_head node; +}; + +/** + * MXS DMA channel + * + * This structure represents a single DMA channel. The MXS platform code + * maintains an array of these structures to represent every DMA channel in the + * system (see mxs_dma_channels). + */ +#define MXS_DMA_FLAGS_IDLE 0 +#define MXS_DMA_FLAGS_BUSY (1 << 0) +#define MXS_DMA_FLAGS_FREE 0 +#define MXS_DMA_FLAGS_ALLOCATED (1 << 16) +#define MXS_DMA_FLAGS_VALID (1 << 31) + +struct mxs_dma_chan { + const char *name; + unsigned long dev; + struct mxs_dma_device *dma; + unsigned int flags; + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +struct mxs_dma_desc *mxs_dma_desc_alloc(void); +void mxs_dma_desc_free(struct mxs_dma_desc *); +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); + +int mxs_dma_go(int chan); +int mxs_dma_init(void); + +#endif /* __DMA_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/gpio.h b/arch/arm/include/asm/arch-mx28/gpio.h new file mode 100644 index 0000000000..be1c944eb7 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/gpio.h @@ -0,0 +1,32 @@ +/* + * Freescale i.MX28 GPIO + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_GPIO_H__ +#define __MX28_GPIO_H__ + +#ifdef CONFIG_MXS_GPIO +void mxs_gpio_init(void); +#else +inline void mxs_gpio_init(void) {} +#endif + +#endif /* __MX28_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h new file mode 100644 index 0000000000..9561b5e485 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/imx-regs.h @@ -0,0 +1,39 @@ +/* + * Freescale i.MX28 Registers + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __IMX_REGS_H__ +#define __IMX_REGS_H__ + +#include <asm/arch/regs-apbh.h> +#include <asm/arch/regs-base.h> +#include <asm/arch/regs-bch.h> +#include <asm/arch/regs-clkctrl.h> +#include <asm/arch/regs-gpmi.h> +#include <asm/arch/regs-i2c.h> +#include <asm/arch/regs-ocotp.h> +#include <asm/arch/regs-pinctrl.h> +#include <asm/arch/regs-power.h> +#include <asm/arch/regs-rtc.h> +#include <asm/arch/regs-ssp.h> +#include <asm/arch/regs-timrot.h> + +#endif /* __IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/iomux-mx28.h b/arch/arm/include/asm/arch-mx28/iomux-mx28.h new file mode 100644 index 0000000000..b42820de74 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/iomux-mx28.h @@ -0,0 +1,537 @@ +/* + * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_IOMUX_MX28_H__ +#define __MACH_IOMUX_MX28_H__ + +#include <asm/arch/iomux.h> + +/* + * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> + * See also iomux.h + * + * BANK PIN MUX + */ +/* MUXSEL_0 */ +#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) + +#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) +#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) +#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) +#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) +#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) +#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) + +#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) + +#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) +#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) +#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) +#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) +#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) +#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) +#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) +#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) + +#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) +#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) +#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) + +/* MUXSEL_1 */ +#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) + +#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) +#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) +#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) +#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) +#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) + +#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) + +#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) +#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) +#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) +#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) +#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) + +#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) + +/* MUXSEL_2 */ +#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) + +#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) +#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) +#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) +#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) +#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) + +#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) + +#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) +#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) +#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) +#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) +#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) +#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) + +#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) + +/* MUXSEL_GPIO */ +#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) + +#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) + +#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) + +#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) + +#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) + +#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/iomux.h b/arch/arm/include/asm/arch-mx28/iomux.h new file mode 100644 index 0000000000..7abdf58b8b --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/iomux.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MXS_IOMUX_H__ +#define __MACH_MXS_IOMUX_H__ + +/* + * IOMUX/PAD Bit field definitions + * + * PAD_BANK: 0..2 (3) + * PAD_PIN: 3..7 (5) + * PAD_MUXSEL: 8..9 (2) + * PAD_MA: 10..11 (2) + * PAD_MA_VALID: 12 (1) + * PAD_VOL: 13 (1) + * PAD_VOL_VALID: 14 (1) + * PAD_PULL: 15 (1) + * PAD_PULL_VALID: 16 (1) + * RESERVED: 17..31 (15) + */ +typedef u32 iomux_cfg_t; + +#define MXS_PAD_BANK_SHIFT 0 +#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) +#define MXS_PAD_PIN_SHIFT 3 +#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) +#define MXS_PAD_MUXSEL_SHIFT 8 +#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) +#define MXS_PAD_MA_SHIFT 10 +#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) +#define MXS_PAD_MA_VALID_SHIFT 12 +#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) +#define MXS_PAD_VOL_SHIFT 13 +#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) +#define MXS_PAD_VOL_VALID_SHIFT 14 +#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) +#define MXS_PAD_PULL_SHIFT 15 +#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) +#define MXS_PAD_PULL_VALID_SHIFT 16 +#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) + +#define PAD_MUXSEL_0 0 +#define PAD_MUXSEL_1 1 +#define PAD_MUXSEL_2 2 +#define PAD_MUXSEL_GPIO 3 + +#define PAD_4MA 0 +#define PAD_8MA 1 +#define PAD_12MA 2 +#define PAD_16MA 3 + +#define PAD_1V8 0 +#define PAD_3V3 1 + +#define PAD_NOPULL 0 +#define PAD_PULLUP 1 + +#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) + +#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) +#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) + +#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) +#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) + +/* generic pad control used in most cases */ +#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) + +#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ + (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ + ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ + ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ + ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ + ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ + ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) + +/* + * A pad becomes naked, when none of mA, vol or pull + * validity bits is set. + */ +#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ + MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) + +static inline unsigned int PAD_BANK(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; +} + +static inline unsigned int PAD_PIN(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; +} + +static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; +} + +static inline unsigned int PAD_MA(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; +} + +static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; +} + +static inline unsigned int PAD_VOL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; +} + +static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; +} + +static inline unsigned int PAD_PULL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; +} + +static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; +} + +/* + * configures a single pad in the iomuxer + */ +int mxs_iomux_setup_pad(iomux_cfg_t pad); + +/* + * configures multiple pads + * convenient way to call the above function with tables + */ +int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); + +#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/arch/arm/include/asm/arch-mx28/regs-apbh.h b/arch/arm/include/asm/arch-mx28/regs-apbh.h new file mode 100644 index 0000000000..a7fa1ec1ca --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-apbh.h @@ -0,0 +1,466 @@ +/* + * Freescale i.MX28 APBH Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __REGS_APBH_H__ +#define __REGS_APBH_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_apbh_regs { + mx28_reg(hw_apbh_ctrl0) + mx28_reg(hw_apbh_ctrl1) + mx28_reg(hw_apbh_ctrl2) + mx28_reg(hw_apbh_channel_ctrl) + mx28_reg(hw_apbh_devsel) + mx28_reg(hw_apbh_dma_burst_size) + mx28_reg(hw_apbh_debug) + + uint32_t reserved[36]; + + union { + struct { + mx28_reg(hw_apbh_ch_curcmdar) + mx28_reg(hw_apbh_ch_nxtcmdar) + mx28_reg(hw_apbh_ch_cmd) + mx28_reg(hw_apbh_ch_bar) + mx28_reg(hw_apbh_ch_sema) + mx28_reg(hw_apbh_ch_debug1) + mx28_reg(hw_apbh_ch_debug2) + } ch[16]; + struct { + mx28_reg(hw_apbh_ch0_curcmdar) + mx28_reg(hw_apbh_ch0_nxtcmdar) + mx28_reg(hw_apbh_ch0_cmd) + mx28_reg(hw_apbh_ch0_bar) + mx28_reg(hw_apbh_ch0_sema) + mx28_reg(hw_apbh_ch0_debug1) + mx28_reg(hw_apbh_ch0_debug2) + mx28_reg(hw_apbh_ch1_curcmdar) + mx28_reg(hw_apbh_ch1_nxtcmdar) + mx28_reg(hw_apbh_ch1_cmd) + mx28_reg(hw_apbh_ch1_bar) + mx28_reg(hw_apbh_ch1_sema) + mx28_reg(hw_apbh_ch1_debug1) + mx28_reg(hw_apbh_ch1_debug2) + mx28_reg(hw_apbh_ch2_curcmdar) + mx28_reg(hw_apbh_ch2_nxtcmdar) + mx28_reg(hw_apbh_ch2_cmd) + mx28_reg(hw_apbh_ch2_bar) + mx28_reg(hw_apbh_ch2_sema) + mx28_reg(hw_apbh_ch2_debug1) + mx28_reg(hw_apbh_ch2_debug2) + mx28_reg(hw_apbh_ch3_curcmdar) + mx28_reg(hw_apbh_ch3_nxtcmdar) + mx28_reg(hw_apbh_ch3_cmd) + mx28_reg(hw_apbh_ch3_bar) + mx28_reg(hw_apbh_ch3_sema) + mx28_reg(hw_apbh_ch3_debug1) + mx28_reg(hw_apbh_ch3_debug2) + mx28_reg(hw_apbh_ch4_curcmdar) + mx28_reg(hw_apbh_ch4_nxtcmdar) + mx28_reg(hw_apbh_ch4_cmd) + mx28_reg(hw_apbh_ch4_bar) + mx28_reg(hw_apbh_ch4_sema) + mx28_reg(hw_apbh_ch4_debug1) + mx28_reg(hw_apbh_ch4_debug2) + mx28_reg(hw_apbh_ch5_curcmdar) + mx28_reg(hw_apbh_ch5_nxtcmdar) + mx28_reg(hw_apbh_ch5_cmd) + mx28_reg(hw_apbh_ch5_bar) + mx28_reg(hw_apbh_ch5_sema) + mx28_reg(hw_apbh_ch5_debug1) + mx28_reg(hw_apbh_ch5_debug2) + mx28_reg(hw_apbh_ch6_curcmdar) + mx28_reg(hw_apbh_ch6_nxtcmdar) + mx28_reg(hw_apbh_ch6_cmd) + mx28_reg(hw_apbh_ch6_bar) + mx28_reg(hw_apbh_ch6_sema) + mx28_reg(hw_apbh_ch6_debug1) + mx28_reg(hw_apbh_ch6_debug2) + mx28_reg(hw_apbh_ch7_curcmdar) + mx28_reg(hw_apbh_ch7_nxtcmdar) + mx28_reg(hw_apbh_ch7_cmd) + mx28_reg(hw_apbh_ch7_bar) + mx28_reg(hw_apbh_ch7_sema) + mx28_reg(hw_apbh_ch7_debug1) + mx28_reg(hw_apbh_ch7_debug2) + mx28_reg(hw_apbh_ch8_curcmdar) + mx28_reg(hw_apbh_ch8_nxtcmdar) + mx28_reg(hw_apbh_ch8_cmd) + mx28_reg(hw_apbh_ch8_bar) + mx28_reg(hw_apbh_ch8_sema) + mx28_reg(hw_apbh_ch8_debug1) + mx28_reg(hw_apbh_ch8_debug2) + mx28_reg(hw_apbh_ch9_curcmdar) + mx28_reg(hw_apbh_ch9_nxtcmdar) + mx28_reg(hw_apbh_ch9_cmd) + mx28_reg(hw_apbh_ch9_bar) + mx28_reg(hw_apbh_ch9_sema) + mx28_reg(hw_apbh_ch9_debug1) + mx28_reg(hw_apbh_ch9_debug2) + mx28_reg(hw_apbh_ch10_curcmdar) + mx28_reg(hw_apbh_ch10_nxtcmdar) + mx28_reg(hw_apbh_ch10_cmd) + mx28_reg(hw_apbh_ch10_bar) + mx28_reg(hw_apbh_ch10_sema) + mx28_reg(hw_apbh_ch10_debug1) + mx28_reg(hw_apbh_ch10_debug2) + mx28_reg(hw_apbh_ch11_curcmdar) + mx28_reg(hw_apbh_ch11_nxtcmdar) + mx28_reg(hw_apbh_ch11_cmd) + mx28_reg(hw_apbh_ch11_bar) + mx28_reg(hw_apbh_ch11_sema) + mx28_reg(hw_apbh_ch11_debug1) + mx28_reg(hw_apbh_ch11_debug2) + mx28_reg(hw_apbh_ch12_curcmdar) + mx28_reg(hw_apbh_ch12_nxtcmdar) + mx28_reg(hw_apbh_ch12_cmd) + mx28_reg(hw_apbh_ch12_bar) + mx28_reg(hw_apbh_ch12_sema) + mx28_reg(hw_apbh_ch12_debug1) + mx28_reg(hw_apbh_ch12_debug2) + mx28_reg(hw_apbh_ch13_curcmdar) + mx28_reg(hw_apbh_ch13_nxtcmdar) + mx28_reg(hw_apbh_ch13_cmd) + mx28_reg(hw_apbh_ch13_bar) + mx28_reg(hw_apbh_ch13_sema) + mx28_reg(hw_apbh_ch13_debug1) + mx28_reg(hw_apbh_ch13_debug2) + mx28_reg(hw_apbh_ch14_curcmdar) + mx28_reg(hw_apbh_ch14_nxtcmdar) + mx28_reg(hw_apbh_ch14_cmd) + mx28_reg(hw_apbh_ch14_bar) + mx28_reg(hw_apbh_ch14_sema) + mx28_reg(hw_apbh_ch14_debug1) + mx28_reg(hw_apbh_ch14_debug2) + mx28_reg(hw_apbh_ch15_curcmdar) + mx28_reg(hw_apbh_ch15_nxtcmdar) + mx28_reg(hw_apbh_ch15_cmd) + mx28_reg(hw_apbh_ch15_bar) + mx28_reg(hw_apbh_ch15_sema) + mx28_reg(hw_apbh_ch15_debug1) + mx28_reg(hw_apbh_ch15_debug2) + }; + }; + mx28_reg(hw_apbh_version) +}; +#endif + +#define APBH_CTRL0_SFTRST (1 << 31) +#define APBH_CTRL0_CLKGATE (1 << 30) +#define APBH_CTRL0_AHB_BURST8_EN (1 << 29) +#define APBH_CTRL0_APB_BURST_EN (1 << 28) +#define APBH_CTRL0_RSVD0_MASK (0xfff << 16) +#define APBH_CTRL0_RSVD0_OFFSET 16 +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff +#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 +#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 +#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 + +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) + +#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) +#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) +#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) +#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) +#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) +#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) +#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) +#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) +#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) +#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) +#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) +#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) +#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) +#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) +#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) +#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) +#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) +#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) +#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) +#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) +#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) +#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) +#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) +#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) +#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) +#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) +#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) +#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) +#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) +#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) +#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) +#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) + +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 + +#define APBH_DEVSEL_CH15_MASK (0x3 << 30) +#define APBH_DEVSEL_CH15_OFFSET 30 +#define APBH_DEVSEL_CH14_MASK (0x3 << 28) +#define APBH_DEVSEL_CH14_OFFSET 28 +#define APBH_DEVSEL_CH13_MASK (0x3 << 26) +#define APBH_DEVSEL_CH13_OFFSET 26 +#define APBH_DEVSEL_CH12_MASK (0x3 << 24) +#define APBH_DEVSEL_CH12_OFFSET 24 +#define APBH_DEVSEL_CH11_MASK (0x3 << 22) +#define APBH_DEVSEL_CH11_OFFSET 22 +#define APBH_DEVSEL_CH10_MASK (0x3 << 20) +#define APBH_DEVSEL_CH10_OFFSET 20 +#define APBH_DEVSEL_CH9_MASK (0x3 << 18) +#define APBH_DEVSEL_CH9_OFFSET 18 +#define APBH_DEVSEL_CH8_MASK (0x3 << 16) +#define APBH_DEVSEL_CH8_OFFSET 16 +#define APBH_DEVSEL_CH7_MASK (0x3 << 14) +#define APBH_DEVSEL_CH7_OFFSET 14 +#define APBH_DEVSEL_CH6_MASK (0x3 << 12) +#define APBH_DEVSEL_CH6_OFFSET 12 +#define APBH_DEVSEL_CH5_MASK (0x3 << 10) +#define APBH_DEVSEL_CH5_OFFSET 10 +#define APBH_DEVSEL_CH4_MASK (0x3 << 8) +#define APBH_DEVSEL_CH4_OFFSET 8 +#define APBH_DEVSEL_CH3_MASK (0x3 << 6) +#define APBH_DEVSEL_CH3_OFFSET 6 +#define APBH_DEVSEL_CH2_MASK (0x3 << 4) +#define APBH_DEVSEL_CH2_OFFSET 4 +#define APBH_DEVSEL_CH1_MASK (0x3 << 2) +#define APBH_DEVSEL_CH1_OFFSET 2 +#define APBH_DEVSEL_CH0_MASK (0x3 << 0) +#define APBH_DEVSEL_CH0_OFFSET 0 + +#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) +#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) +#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28 +#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26) +#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26 +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24) +#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24 +#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22) +#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22 +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20) +#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20 +#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18) +#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18 +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16) +#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16 +#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16) +#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16) +#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16) +#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14) +#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14 +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12) +#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12 +#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10) +#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10 +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8) +#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8 +#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6) +#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6 +#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6) +#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6) +#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6) + +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4) +#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4 +#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4) +#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4) +#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4) +#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2) +#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2 +#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2) +#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2) +#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2) + +#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3 +#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0 +#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0 +#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 +#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 + +#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) + +#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff +#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0 + +#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff +#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0 + +#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16) +#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 +#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) +#define APBH_CHn_CMD_CMDWORDS_OFFSET 12 +#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) +#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) +#define APBH_CHn_CMD_SEMAPHORE (1 << 6) +#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) +#define APBH_CHn_CMD_NANDLOCK (1 << 4) +#define APBH_CHn_CMD_IRQONCMPLT (1 << 3) +#define APBH_CHn_CMD_CHAIN (1 << 2) +#define APBH_CHn_CMD_COMMAND_MASK 0x3 +#define APBH_CHn_CMD_COMMAND_OFFSET 0 +#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 +#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1 +#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2 +#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3 + +#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff +#define APBH_CHn_BAR_ADDRESS_OFFSET 0 + +#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24) +#define APBH_CHn_SEMA_RSVD2_OFFSET 24 +#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16) +#define APBH_CHn_SEMA_PHORE_OFFSET 16 +#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8) +#define APBH_CHn_SEMA_RSVD1_OFFSET 8 +#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) +#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 + +#define APBH_CHn_DEBUG1_REQ (1 << 31) +#define APBH_CHn_DEBUG1_BURST (1 << 30) +#define APBH_CHn_DEBUG1_KICK (1 << 29) +#define APBH_CHn_DEBUG1_END (1 << 28) +#define APBH_CHn_DEBUG1_SENSE (1 << 27) +#define APBH_CHn_DEBUG1_READY (1 << 26) +#define APBH_CHn_DEBUG1_LOCK (1 << 25) +#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) +#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) +#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) +#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) +#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) +#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) +#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 +#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f +#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0 +#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03 +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06 +#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07 +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08 +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09 +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f +#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14 +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15 +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c +#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f + +#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16) +#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16 +#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff +#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0 + +#define APBH_VERSION_MAJOR_MASK (0xff << 24) +#define APBH_VERSION_MAJOR_OFFSET 24 +#define APBH_VERSION_MINOR_MASK (0xff << 16) +#define APBH_VERSION_MINOR_OFFSET 16 +#define APBH_VERSION_STEP_MASK 0xffff +#define APBH_VERSION_STEP_OFFSET 0 + +#endif /* __REGS_APBH_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-base.h b/arch/arm/include/asm/arch-mx28/regs-base.h new file mode 100644 index 0000000000..dbdcc2b5bd --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-base.h @@ -0,0 +1,88 @@ +/* + * Freescale i.MX28 Peripheral Base Addresses + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_BASE_H__ +#define __MX28_REGS_BASE_H__ + +/* + * Register base address + */ +#define MXS_ICOL_BASE 0x80000000 +#define MXS_HSADC_BASE 0x80002000 +#define MXS_APBH_BASE 0x80004000 +#define MXS_PERFMON_BASE 0x80006000 +#define MXS_BCH_BASE 0x8000A000 +#define MXS_GPMI_BASE 0x8000C000 +#define MXS_SSP0_BASE 0x80010000 +#define MXS_SSP1_BASE 0x80012000 +#define MXS_SSP2_BASE 0x80014000 +#define MXS_SSP3_BASE 0x80016000 +#define MXS_PINCTRL_BASE 0x80018000 +#define MXS_DIGCTL_BASE 0x8001C000 +#define MXS_ETM_BASE 0x80022000 +#define MXS_APBX_BASE 0x80024000 +#define MXS_DCP_BASE 0x80028000 +#define MXS_PXP_BASE 0x8002A000 +#define MXS_OCOTP_BASE 0x8002C000 +#define MXS_AXI_AHB0_BASE 0x8002E000 +#define MXS_LCDIF_BASE 0x80030000 +#define MXS_CAN0_BASE 0x80032000 +#define MXS_CAN1_BASE 0x80034000 +#define MXS_SIMDBG_BASE 0x8003C000 +#define MXS_SIMGPMISEL_BASE 0x8003C200 +#define MXS_SIMSSPSEL_BASE 0x8003C300 +#define MXS_SIMMEMSEL_BASE 0x8003C400 +#define MXS_GPIOMON_BASE 0x8003C500 +#define MXS_SIMENET_BASE 0x8003C700 +#define MXS_ARMJTAG_BASE 0x8003C800 +#define MXS_CLKCTRL_BASE 0x80040000 +#define MXS_SAIF0_BASE 0x80042000 +#define MXS_POWER_BASE 0x80044000 +#define MXS_SAIF1_BASE 0x80046000 +#define MXS_LRADC_BASE 0x80050000 +#define MXS_SPDIF_BASE 0x80054000 +#define MXS_RTC_BASE 0x80056000 +#define MXS_I2C0_BASE 0x80058000 +#define MXS_I2C1_BASE 0x8005A000 +#define MXS_PWM_BASE 0x80064000 +#define MXS_TIMROT_BASE 0x80068000 +#define MXS_UARTAPP0_BASE 0x8006A000 +#define MXS_UARTAPP1_BASE 0x8006C000 +#define MXS_UARTAPP2_BASE 0x8006E000 +#define MXS_UARTAPP3_BASE 0x80070000 +#define MXS_UARTAPP4_BASE 0x80072000 +#define MXS_UARTDBG_BASE 0x80074000 +#define MXS_USBPHY0_BASE 0x8007C000 +#define MXS_USBPHY1_BASE 0x8007E000 +#define MXS_USBCTRL0_BASE 0x80080000 +#define MXS_USBCTRL1_BASE 0x80090000 +#define MXS_DFLPT_BASE 0x800C0000 +#define MXS_DRAM_BASE 0x800E0000 +#define MXS_ENET0_BASE 0x800F0000 +#define MXS_ENET1_BASE 0x800F4000 + +#endif /* __MX28_REGS_BASE_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-bch.h b/arch/arm/include/asm/arch-mx28/regs-bch.h new file mode 100644 index 0000000000..cac04709da --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-bch.h @@ -0,0 +1,230 @@ +/* + * Freescale i.MX28 BCH Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_BCH_H__ +#define __MX28_REGS_BCH_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_bch_regs { + mx28_reg(hw_bch_ctrl) + mx28_reg(hw_bch_status0) + mx28_reg(hw_bch_mode) + mx28_reg(hw_bch_encodeptr) + mx28_reg(hw_bch_dataptr) + mx28_reg(hw_bch_metaptr) + + uint32_t reserved[4]; + + mx28_reg(hw_bch_layoutselect) + mx28_reg(hw_bch_flash0layout0) + mx28_reg(hw_bch_flash0layout1) + mx28_reg(hw_bch_flash1layout0) + mx28_reg(hw_bch_flash1layout1) + mx28_reg(hw_bch_flash2layout0) + mx28_reg(hw_bch_flash2layout1) + mx28_reg(hw_bch_flash3layout0) + mx28_reg(hw_bch_flash3layout1) + mx28_reg(hw_bch_dbgkesread) + mx28_reg(hw_bch_dbgcsferead) + mx28_reg(hw_bch_dbgsyndegread) + mx28_reg(hw_bch_dbgahbmread) + mx28_reg(hw_bch_blockname) + mx28_reg(hw_bch_version) +}; +#endif + +#define BCH_CTRL_SFTRST (1 << 31) +#define BCH_CTRL_CLKGATE (1 << 30) +#define BCH_CTRL_DEBUGSYNDROME (1 << 22) +#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) +#define BCH_CTRL_M2M_LAYOUT_OFFSET 18 +#define BCH_CTRL_M2M_ENCODE (1 << 17) +#define BCH_CTRL_M2M_ENABLE (1 << 16) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) +#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) +#define BCH_CTRL_BM_ERROR_IRQ (1 << 3) +#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) +#define BCH_CTRL_COMPLETE_IRQ (1 << 0) + +#define BCH_STATUS0_HANDLE_MASK (0xfff << 20) +#define BCH_STATUS0_HANDLE_OFFSET 20 +#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16) +#define BCH_STATUS0_COMPLETED_CE_OFFSET 16 +#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8) +#define BCH_STATUS0_STATUS_BLK0_OFFSET 8 +#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) +#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) +#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) +#define BCH_STATUS0_ALLONES (1 << 4) +#define BCH_STATUS0_CORRECTED (1 << 3) +#define BCH_STATUS0_UNCORRECTABLE (1 << 2) + +#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff +#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 + +#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff +#define BCH_ENCODEPTR_ADDR_OFFSET 0 + +#define BCH_DATAPTR_ADDR_MASK 0xffffffff +#define BCH_DATAPTR_ADDR_OFFSET 0 + +#define BCH_METAPTR_ADDR_MASK 0xffffffff +#define BCH_METAPTR_ADDR_OFFSET 0 + +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30) +#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30 +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28) +#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28 +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26) +#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26 +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24) +#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24 +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22) +#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22 +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20) +#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20 +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18) +#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18 +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16) +#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16 +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14) +#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14 +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12) +#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12 +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10) +#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10 +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8) +#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8 +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6) +#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6 +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4) +#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4 +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2) +#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2 +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0) +#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0 + +#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24) +#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 +#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) +#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 +#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) +#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12 +#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 + +#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) +#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 +#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) +#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12 +#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 + +#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) +#define BCH_DEBUG0_RSVD1_OFFSET 27 +#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) +#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) +#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) +#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) +#define BCH_DEBUG0_KES_STANDALONE (1 << 11) +#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) +#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) +#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) +#define BCH_DEBUG0_RSVD0_OFFSET 6 +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f +#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0 + +#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff +#define BCH_DBGKESREAD_VALUES_OFFSET 0 + +#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff +#define BCH_DBGCSFEREAD_VALUES_OFFSET 0 + +#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff +#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0 + +#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff +#define BCH_DBGAHBMREAD_VALUES_OFFSET 0 + +#define BCH_BLOCKNAME_NAME_MASK 0xffffffff +#define BCH_BLOCKNAME_NAME_OFFSET 0 + +#define BCH_VERSION_MAJOR_MASK (0xff << 24) +#define BCH_VERSION_MAJOR_OFFSET 24 +#define BCH_VERSION_MINOR_MASK (0xff << 16) +#define BCH_VERSION_MINOR_OFFSET 16 +#define BCH_VERSION_STEP_MASK 0xffff +#define BCH_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_BCH_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h new file mode 100644 index 0000000000..93d0397ef7 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h @@ -0,0 +1,312 @@ +/* + * Freescale i.MX28 CLKCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_CLKCTRL_H__ +#define __MX28_REGS_CLKCTRL_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_clkctrl_regs { + mx28_reg(hw_clkctrl_pll0ctrl0) /* 0x00 */ + mx28_reg(hw_clkctrl_pll0ctrl1) /* 0x10 */ + mx28_reg(hw_clkctrl_pll1ctrl0) /* 0x20 */ + mx28_reg(hw_clkctrl_pll1ctrl1) /* 0x30 */ + mx28_reg(hw_clkctrl_pll2ctrl0) /* 0x40 */ + mx28_reg(hw_clkctrl_cpu) /* 0x50 */ + mx28_reg(hw_clkctrl_hbus) /* 0x60 */ + mx28_reg(hw_clkctrl_xbus) /* 0x70 */ + mx28_reg(hw_clkctrl_xtal) /* 0x80 */ + mx28_reg(hw_clkctrl_ssp0) /* 0x90 */ + mx28_reg(hw_clkctrl_ssp1) /* 0xa0 */ + mx28_reg(hw_clkctrl_ssp2) /* 0xb0 */ + mx28_reg(hw_clkctrl_ssp3) /* 0xc0 */ + mx28_reg(hw_clkctrl_gpmi) /* 0xd0 */ + mx28_reg(hw_clkctrl_spdif) /* 0xe0 */ + mx28_reg(hw_clkctrl_emi) /* 0xf0 */ + mx28_reg(hw_clkctrl_saif0) /* 0x100 */ + mx28_reg(hw_clkctrl_saif1) /* 0x110 */ + mx28_reg(hw_clkctrl_lcdif) /* 0x120 */ + mx28_reg(hw_clkctrl_etm) /* 0x130 */ + mx28_reg(hw_clkctrl_enet) /* 0x140 */ + mx28_reg(hw_clkctrl_hsadc) /* 0x150 */ + mx28_reg(hw_clkctrl_flexcan) /* 0x160 */ + + uint32_t reserved[16]; + + mx28_reg(hw_clkctrl_frac0) /* 0x1b0 */ + mx28_reg(hw_clkctrl_frac1) /* 0x1c0 */ + mx28_reg(hw_clkctrl_clkseq) /* 0x1d0 */ + mx28_reg(hw_clkctrl_reset) /* 0x1e0 */ + mx28_reg(hw_clkctrl_status) /* 0x1f0 */ + mx28_reg(hw_clkctrl_version) /* 0x200 */ +}; +#endif + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) +#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) + +#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) +#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 +#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f +#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 + +#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) +#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) +#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) +#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) +#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) +#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) +#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 +#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) +#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_MASK 0x1f +#define CLKCTRL_HBUS_DIV_OFFSET 0 + +#define CLKCTRL_XBUS_BUSY (1 << 31) +#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) +#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_DIV_MASK 0x3ff +#define CLKCTRL_XBUS_DIV_OFFSET 0 + +#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 +#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 + +#define CLKCTRL_SSP_CLKGATE (1 << 31) +#define CLKCTRL_SSP_BUSY (1 << 29) +#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_DIV_MASK 0x1ff +#define CLKCTRL_SSP_DIV_OFFSET 0 + +#define CLKCTRL_GPMI_CLKGATE (1 << 31) +#define CLKCTRL_GPMI_BUSY (1 << 29) +#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_DIV_MASK 0x3ff +#define CLKCTRL_GPMI_DIV_OFFSET 0 + +#define CLKCTRL_SPDIF_CLKGATE (1 << 31) + +#define CLKCTRL_EMI_CLKGATE (1 << 31) +#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) +#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) +#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) +#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 +#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f +#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 + +#define CLKCTRL_SAIF0_CLKGATE (1 << 31) +#define CLKCTRL_SAIF0_BUSY (1 << 29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_DIV_MASK 0xffff +#define CLKCTRL_SAIF0_DIV_OFFSET 0 + +#define CLKCTRL_SAIF1_CLKGATE (1 << 31) +#define CLKCTRL_SAIF1_BUSY (1 << 29) +#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF1_DIV_MASK 0xffff +#define CLKCTRL_SAIF1_DIV_OFFSET 0 + +#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) +#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) +#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) +#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff +#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 + +#define CLKCTRL_ETM_CLKGATE (1 << 31) +#define CLKCTRL_ETM_BUSY (1 << 29) +#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) +#define CLKCTRL_ETM_DIV_MASK 0x7f +#define CLKCTRL_ETM_DIV_OFFSET 0 + +#define CLKCTRL_ENET_SLEEP (1 << 31) +#define CLKCTRL_ENET_DISABLE (1 << 30) +#define CLKCTRL_ENET_STATUS (1 << 29) +#define CLKCTRL_ENET_BUSY_TIME (1 << 27) +#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) +#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 +#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) +#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 +#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) +#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) +#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) +#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) +#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) +#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) +#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) + +#define CLKCTRL_HSADC_RESETB (1 << 30) +#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) +#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 + +#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) +#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) +#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) +#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) + +#define CLKCTRL_FRAC0_CLKGATEIO0 (1 << 31) +#define CLKCTRL_FRAC0_IO0_STABLE (1 << 30) +#define CLKCTRL_FRAC0_IO0FRAC_MASK (0x3f << 24) +#define CLKCTRL_FRAC0_IO0FRAC_OFFSET 24 +#define CLKCTRL_FRAC0_CLKGATEIO1 (1 << 23) +#define CLKCTRL_FRAC0_IO1_STABLE (1 << 22) +#define CLKCTRL_FRAC0_IO1FRAC_MASK (0x3f << 16) +#define CLKCTRL_FRAC0_IO1FRAC_OFFSET 16 +#define CLKCTRL_FRAC0_CLKGATEEMI (1 << 15) +#define CLKCTRL_FRAC0_EMI_STABLE (1 << 14) +#define CLKCTRL_FRAC0_EMIFRAC_MASK (0x3f << 8) +#define CLKCTRL_FRAC0_EMIFRAC_OFFSET 8 +#define CLKCTRL_FRAC0_CLKGATECPU (1 << 7) +#define CLKCTRL_FRAC0_CPU_STABLE (1 << 6) +#define CLKCTRL_FRAC0_CPUFRAC_MASK 0x3f +#define CLKCTRL_FRAC0_CPUFRAC_OFFSET 0 + +#define CLKCTRL_FRAC1_CLKGATEGPMI (1 << 23) +#define CLKCTRL_FRAC1_GPMI_STABLE (1 << 22) +#define CLKCTRL_FRAC1_GPMIFRAC_MASK (0x3f << 16) +#define CLKCTRL_FRAC1_GPMIFRAC_OFFSET 16 +#define CLKCTRL_FRAC1_CLKGATEHSADC (1 << 15) +#define CLKCTRL_FRAC1_HSADC_STABLE (1 << 14) +#define CLKCTRL_FRAC1_HSADCFRAC_MASK (0x3f << 8) +#define CLKCTRL_FRAC1_HSADCFRAC_OFFSET 8 +#define CLKCTRL_FRAC1_CLKGATEPIX (1 << 7) +#define CLKCTRL_FRAC1_PIX_STABLE (1 << 6) +#define CLKCTRL_FRAC1_PIXFRAC_MASK 0x3f +#define CLKCTRL_FRAC1_PIXFRAC_OFFSET 0 + +#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) +#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) +#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) + +#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) +#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) +#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) +#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) +#define CLKCTRL_RESET_CHIP (1 << 1) +#define CLKCTRL_RESET_DIG (1 << 0) + +#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) +#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 + +#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) +#define CLKCTRL_VERSION_MAJOR_OFFSET 24 +#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) +#define CLKCTRL_VERSION_MINOR_OFFSET 16 +#define CLKCTRL_VERSION_STEP_MASK 0xffff +#define CLKCTRL_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h new file mode 100644 index 0000000000..efe975b4bb --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -0,0 +1,66 @@ +/* + * Freescale i.MX28 Register Accessors + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_COMMON_H__ +#define __MX28_REGS_COMMON_H__ + +/* + * The i.MX28 has interesting feature when it comes to register access. There + * are four kinds of access to one particular register. Those are: + * + * 1) Common read/write access. To use this mode, just write to the address of + * the register. + * 2) Set bits only access. To set bits, write which bits you want to set to the + * address of the register + 0x4. + * 3) Clear bits only access. To clear bits, write which bits you want to clear + * to the address of the register + 0x8. + * 4) Toggle bits only access. To toggle bits, write which bits you want to + * toggle to the address of the register + 0xc. + * + * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits + * can be set/cleared by pure write as in access type 1, some need to be + * explicitly set/cleared by using access type 2-3. + * + * The following macros and structures allow the user to either access the + * register in all aforementioned modes (by accessing reg_name, reg_name_set, + * reg_name_clr, reg_name_tog) or pass the register structure further into + * various functions with correct type information (by accessing reg_name_reg). + * + */ + +#define __mx28_reg(name) \ + uint32_t name; \ + uint32_t name##_set; \ + uint32_t name##_clr; \ + uint32_t name##_tog; + +struct mx28_register { + __mx28_reg(reg) +}; + +#define mx28_reg(name) \ + union { \ + struct { __mx28_reg(name) }; \ + struct mx28_register name##_reg; \ + }; + +#endif /* __MX28_REGS_COMMON_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-gpmi.h b/arch/arm/include/asm/arch-mx28/regs-gpmi.h new file mode 100644 index 0000000000..00967938f5 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-gpmi.h @@ -0,0 +1,222 @@ +/* + * Freescale i.MX28 GPMI Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_GPMI_H__ +#define __MX28_REGS_GPMI_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_gpmi_regs { + mx28_reg(hw_gpmi_ctrl0) + mx28_reg(hw_gpmi_compare) + mx28_reg(hw_gpmi_eccctrl) + mx28_reg(hw_gpmi_ecccount) + mx28_reg(hw_gpmi_payload) + mx28_reg(hw_gpmi_auxiliary) + mx28_reg(hw_gpmi_ctrl1) + mx28_reg(hw_gpmi_timing0) + mx28_reg(hw_gpmi_timing1) + + uint32_t reserved[4]; + + mx28_reg(hw_gpmi_data) + mx28_reg(hw_gpmi_stat) + mx28_reg(hw_gpmi_debug) + mx28_reg(hw_gpmi_version) +}; +#endif + +#define GPMI_CTRL0_SFTRST (1 << 31) +#define GPMI_CTRL0_CLKGATE (1 << 30) +#define GPMI_CTRL0_RUN (1 << 29) +#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28) +#define GPMI_CTRL0_LOCK_CS (1 << 27) +#define GPMI_CTRL0_UDMA (1 << 26) +#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24) +#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24 +#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) +#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) +#define GPMI_CTRL0_WORD_LENGTH (1 << 23) +#define GPMI_CTRL0_CS_MASK (0x7 << 20) +#define GPMI_CTRL0_CS_OFFSET 20 +#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17) +#define GPMI_CTRL0_ADDRESS_OFFSET 17 +#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) +#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) +#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff +#define GPMI_CTRL0_XFER_COUNT_OFFSET 0 + +#define GPMI_COMPARE_MASK_MASK (0xffff << 16) +#define GPMI_COMPARE_MASK_OFFSET 16 +#define GPMI_COMPARE_REFERENCE_MASK 0xffff +#define GPMI_COMPARE_REFERENCE_OFFSET 0 + +#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16) +#define GPMI_ECCCTRL_HANDLE_OFFSET 16 +#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13) +#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13 +#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) +#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) +#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12) +#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff +#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0 +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff + +#define GPMI_ECCCOUNT_COUNT_MASK 0xffff +#define GPMI_ECCCOUNT_COUNT_OFFSET 0 + +#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2) +#define GPMI_PAYLOAD_ADDRESS_OFFSET 2 + +#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2) +#define GPMI_AUXILIARY_ADDRESS_OFFSET 2 + +#define GPMI_CTRL1_DECOUPLE_CS (1 << 24) +#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) +#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 +#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) +#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) +#define GPMI_CTRL1_BCH_MODE (1 << 18) +#define GPMI_CTRL1_DLL_ENABLE (1 << 17) +#define GPMI_CTRL1_HALF_PERIOD (1 << 16) +#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12) +#define GPMI_CTRL1_RDN_DELAY_OFFSET 12 +#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11) +#define GPMI_CTRL1_DEV_IRQ (1 << 10) +#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) +#define GPMI_CTRL1_BURST_EN (1 << 8) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4 +#define GPMI_CTRL1_DEV_RESET (1 << 3) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) +#define GPMI_CTRL1_CAMERA_MODE (1 << 1) +#define GPMI_CTRL1_GPMI_MODE (1 << 0) + +#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) +#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 +#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8) +#define GPMI_TIMING0_DATA_HOLD_OFFSET 8 +#define GPMI_TIMING0_DATA_SETUP_MASK 0xff +#define GPMI_TIMING0_DATA_SETUP_OFFSET 0 + +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16 + +#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24) +#define GPMI_TIMING2_UDMA_TRP_OFFSET 24 +#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16) +#define GPMI_TIMING2_UDMA_ENV_OFFSET 16 +#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8) +#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8 +#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff +#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0 + +#define GPMI_DATA_DATA_MASK 0xffffffff +#define GPMI_DATA_DATA_OFFSET 0 + +#define GPMI_STAT_READY_BUSY_MASK (0xff << 24) +#define GPMI_STAT_READY_BUSY_OFFSET 24 +#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16) +#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16 +#define GPMI_STAT_DEV7_ERROR (1 << 15) +#define GPMI_STAT_DEV6_ERROR (1 << 14) +#define GPMI_STAT_DEV5_ERROR (1 << 13) +#define GPMI_STAT_DEV4_ERROR (1 << 12) +#define GPMI_STAT_DEV3_ERROR (1 << 11) +#define GPMI_STAT_DEV2_ERROR (1 << 10) +#define GPMI_STAT_DEV1_ERROR (1 << 9) +#define GPMI_STAT_DEV0_ERROR (1 << 8) +#define GPMI_STAT_ATA_IRQ (1 << 4) +#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3) +#define GPMI_STAT_FIFO_EMPTY (1 << 2) +#define GPMI_STAT_FIFO_FULL (1 << 1) +#define GPMI_STAT_PRESENT (1 << 0) + +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24) +#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24 +#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16) +#define GPMI_DEBUG_DMA_SENSE_OFFSET 16 +#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8) +#define GPMI_DEBUG_DMAREQ_OFFSET 8 +#define GPMI_DEBUG_CMD_END_MASK 0xff +#define GPMI_DEBUG_CMD_END_OFFSET 0 + +#define GPMI_VERSION_MAJOR_MASK (0xff << 24) +#define GPMI_VERSION_MAJOR_OFFSET 24 +#define GPMI_VERSION_MINOR_MASK (0xff << 16) +#define GPMI_VERSION_MINOR_OFFSET 16 +#define GPMI_VERSION_STEP_MASK 0xffff +#define GPMI_VERSION_STEP_OFFSET 0 + +#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24) +#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24 +#define GPMI_DEBUG2_BUSY (1 << 23) +#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20) +#define GPMI_DEBUG2_PIN_STATE_OFFSET 20 +#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20) +#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16) +#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16 +#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16) +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12) +#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12 +#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) +#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) +#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) +#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) +#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) +#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f +#define GPMI_DEBUG2_RDN_TAP_OFFSET 0 + +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16) +#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16 +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff +#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0 + +#endif /* __MX28_REGS_GPMI_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-i2c.h b/arch/arm/include/asm/arch-mx28/regs-i2c.h new file mode 100644 index 0000000000..30e0ed7433 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-i2c.h @@ -0,0 +1,207 @@ +/* + * Freescale i.MX28 I2C Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_I2C_H__ +#define __MX28_REGS_I2C_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_i2c_regs { + mx28_reg(hw_i2c_ctrl0) + mx28_reg(hw_i2c_timing0) + mx28_reg(hw_i2c_timing1) + mx28_reg(hw_i2c_timing2) + mx28_reg(hw_i2c_ctrl1) + mx28_reg(hw_i2c_stat) + mx28_reg(hw_i2c_queuectrl) + mx28_reg(hw_i2c_queuestat) + mx28_reg(hw_i2c_queuecmd) + mx28_reg(hw_i2c_queuedata) + mx28_reg(hw_i2c_data) + mx28_reg(hw_i2c_debug0) + mx28_reg(hw_i2c_debug1) + mx28_reg(hw_i2c_version) +}; +#endif + +#define I2C_CTRL_SFTRST (1 << 31) +#define I2C_CTRL_CLKGATE (1 << 30) +#define I2C_CTRL_RUN (1 << 29) +#define I2C_CTRL_PREACK (1 << 27) +#define I2C_CTRL_ACKNOWLEDGE (1 << 26) +#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) +#define I2C_CTRL_MULTI_MASTER (1 << 23) +#define I2C_CTRL_CLOCK_HELD (1 << 22) +#define I2C_CTRL_RETAIN_CLOCK (1 << 21) +#define I2C_CTRL_POST_SEND_STOP (1 << 20) +#define I2C_CTRL_PRE_SEND_START (1 << 19) +#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) +#define I2C_CTRL_MASTER_MODE (1 << 17) +#define I2C_CTRL_DIRECTION (1 << 16) +#define I2C_CTRL_XFER_COUNT_MASK 0xffff +#define I2C_CTRL_XFER_COUNT_OFFSET 0 + +#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16) +#define I2C_TIMING0_HIGH_COUNT_OFFSET 16 +#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff +#define I2C_TIMING0_RCV_COUNT_OFFSET 0 + +#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16) +#define I2C_TIMING1_LOW_COUNT_OFFSET 16 +#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff +#define I2C_TIMING1_XMIT_COUNT_OFFSET 0 + +#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16) +#define I2C_TIMING2_BUS_FREE_OFFSET 16 +#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff +#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 + +#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) +#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) +#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) +#define I2C_CTRL1_ACK_MODE (1 << 27) +#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) +#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) +#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) +#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) +#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 +#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) +#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) +#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) +#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) +#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) +#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) +#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) +#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) +#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) +#define I2C_CTRL1_SLAVE_IRQ (1 << 0) + +#define I2C_STAT_MASTER_PRESENT (1 << 31) +#define I2C_STAT_SLAVE_PRESENT (1 << 30) +#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) +#define I2C_STAT_GOT_A_NAK (1 << 28) +#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) +#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 +#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) +#define I2C_STAT_SLAVE_FOUND (1 << 14) +#define I2C_STAT_SLAVE_SEARCHING (1 << 13) +#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) +#define I2C_STAT_BUS_BUSY (1 << 11) +#define I2C_STAT_CLK_GEN_BUSY (1 << 10) +#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) +#define I2C_STAT_SLAVE_BUSY (1 << 8) +#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) +#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) +#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) +#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) +#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) +#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) +#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) +#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) + +#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) +#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 +#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) +#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 +#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) +#define I2C_QUEUECTRL_RD_CLEAR (1 << 4) +#define I2C_QUEUECTRL_WR_CLEAR (1 << 3) +#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) +#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) +#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) + +#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) +#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) +#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) +#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 +#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) +#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) +#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f +#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 + +#define I2C_QUEUECMD_PREACK (1 << 27) +#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) +#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) +#define I2C_QUEUECMD_MULTI_MASTER (1 << 23) +#define I2C_QUEUECMD_CLOCK_HELD (1 << 22) +#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) +#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) +#define I2C_QUEUECMD_PRE_SEND_START (1 << 19) +#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) +#define I2C_QUEUECMD_MASTER_MODE (1 << 17) +#define I2C_QUEUECMD_DIRECTION (1 << 16) +#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff +#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 + +#define I2C_QUEUEDATA_DATA_MASK 0xffffffff +#define I2C_QUEUEDATA_DATA_OFFSET 0 + +#define I2C_DATA_DATA_MASK 0xffffffff +#define I2C_DATA_DATA_OFFSET 0 + +#define I2C_DEBUG0_DMAREQ (1 << 31) +#define I2C_DEBUG0_DMAENDCMD (1 << 30) +#define I2C_DEBUG0_DMAKICK (1 << 29) +#define I2C_DEBUG0_DMATERMINATE (1 << 28) +#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) +#define I2C_DEBUG0_STATE_VALUE_OFFSET 26 +#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) +#define I2C_DEBUG0_DMA_STATE_OFFSET 16 +#define I2C_DEBUG0_START_TOGGLE (1 << 15) +#define I2C_DEBUG0_STOP_TOGGLE (1 << 14) +#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) +#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) +#define I2C_DEBUG0_STATE_LATCH (1 << 11) +#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) +#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff +#define I2C_DEBUG0_STATE_STATE_OFFSET 0 + +#define I2C_DEBUG1_I2C_CLK_IN (1 << 31) +#define I2C_DEBUG1_I2C_DATA_IN (1 << 30) +#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) +#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 +#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) +#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 +#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) +#define I2C_DEBUG1_LST_MODE_OFFSET 9 +#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) +#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) +#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) +#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) +#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) +#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) + +#define I2C_VERSION_MAJOR_MASK (0xff << 24) +#define I2C_VERSION_MAJOR_OFFSET 24 +#define I2C_VERSION_MINOR_MASK (0xff << 16) +#define I2C_VERSION_MINOR_OFFSET 16 +#define I2C_VERSION_STEP_MASK 0xffff +#define I2C_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_I2C_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-ocotp.h b/arch/arm/include/asm/arch-mx28/regs-ocotp.h new file mode 100644 index 0000000000..ea2fd7b167 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-ocotp.h @@ -0,0 +1,173 @@ +/* + * Freescale i.MX28 OCOTP Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_OCOTP_H__ +#define __MX28_REGS_OCOTP_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_ocotp_regs { + mx28_reg(hw_ocotp_ctrl) /* 0x0 */ + mx28_reg(hw_ocotp_data) /* 0x10 */ + mx28_reg(hw_ocotp_cust0) /* 0x20 */ + mx28_reg(hw_ocotp_cust1) /* 0x30 */ + mx28_reg(hw_ocotp_cust2) /* 0x40 */ + mx28_reg(hw_ocotp_cust3) /* 0x50 */ + mx28_reg(hw_ocotp_crypto0) /* 0x60 */ + mx28_reg(hw_ocotp_crypto1) /* 0x70 */ + mx28_reg(hw_ocotp_crypto2) /* 0x80 */ + mx28_reg(hw_ocotp_crypto3) /* 0x90 */ + mx28_reg(hw_ocotp_hwcap0) /* 0xa0 */ + mx28_reg(hw_ocotp_hwcap1) /* 0xb0 */ + mx28_reg(hw_ocotp_hwcap2) /* 0xc0 */ + mx28_reg(hw_ocotp_hwcap3) /* 0xd0 */ + mx28_reg(hw_ocotp_hwcap4) /* 0xe0 */ + mx28_reg(hw_ocotp_hwcap5) /* 0xf0 */ + mx28_reg(hw_ocotp_swcap) /* 0x100 */ + mx28_reg(hw_ocotp_custcap) /* 0x110 */ + mx28_reg(hw_ocotp_lock) /* 0x120 */ + mx28_reg(hw_ocotp_ops0) /* 0x130 */ + mx28_reg(hw_ocotp_ops1) /* 0x140 */ + mx28_reg(hw_ocotp_ops2) /* 0x150 */ + mx28_reg(hw_ocotp_ops3) /* 0x160 */ + mx28_reg(hw_ocotp_un0) /* 0x170 */ + mx28_reg(hw_ocotp_un1) /* 0x180 */ + mx28_reg(hw_ocotp_un2) /* 0x190 */ + mx28_reg(hw_ocotp_rom0) /* 0x1a0 */ + mx28_reg(hw_ocotp_rom1) /* 0x1b0 */ + mx28_reg(hw_ocotp_rom2) /* 0x1c0 */ + mx28_reg(hw_ocotp_rom3) /* 0x1d0 */ + mx28_reg(hw_ocotp_rom4) /* 0x1e0 */ + mx28_reg(hw_ocotp_rom5) /* 0x1f0 */ + mx28_reg(hw_ocotp_rom6) /* 0x200 */ + mx28_reg(hw_ocotp_rom7) /* 0x210 */ + mx28_reg(hw_ocotp_srk0) /* 0x220 */ + mx28_reg(hw_ocotp_srk1) /* 0x230 */ + mx28_reg(hw_ocotp_srk2) /* 0x240 */ + mx28_reg(hw_ocotp_srk3) /* 0x250 */ + mx28_reg(hw_ocotp_srk4) /* 0x260 */ + mx28_reg(hw_ocotp_srk5) /* 0x270 */ + mx28_reg(hw_ocotp_srk6) /* 0x280 */ + mx28_reg(hw_ocotp_srk7) /* 0x290 */ + mx28_reg(hw_ocotp_version) /* 0x2a0 */ +}; +#endif + +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) +#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 +#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) +#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) +#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) +#define OCOTP_CTRL_ERROR (1 << 9) +#define OCOTP_CTRL_BUSY (1 << 8) +#define OCOTP_CTRL_ADDR_MASK 0x3f +#define OCOTP_CTRL_ADDR_OFFSET 0 + +#define OCOTP_DATA_DATA_MASK 0xffffffff +#define OCOTP_DATA_DATA_OFFSET 0 + +#define OCOTP_CUST_BITS_MASK 0xffffffff +#define OCOTP_CUST_BITS_OFFSET 0 + +#define OCOTP_CRYPTO_BITS_MASK 0xffffffff +#define OCOTP_CRYPTO_BITS_OFFSET 0 + +#define OCOTP_HWCAP_BITS_MASK 0xffffffff +#define OCOTP_HWCAP_BITS_OFFSET 0 + +#define OCOTP_SWCAP_BITS_MASK 0xffffffff +#define OCOTP_SWCAP_BITS_OFFSET 0 + +#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) +#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) + +#define OCOTP_LOCK_ROM7 (1 << 31) +#define OCOTP_LOCK_ROM6 (1 << 30) +#define OCOTP_LOCK_ROM5 (1 << 29) +#define OCOTP_LOCK_ROM4 (1 << 28) +#define OCOTP_LOCK_ROM3 (1 << 27) +#define OCOTP_LOCK_ROM2 (1 << 26) +#define OCOTP_LOCK_ROM1 (1 << 25) +#define OCOTP_LOCK_ROM0 (1 << 24) +#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) +#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) +#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) +#define OCOTP_LOCK_PIN (1 << 20) +#define OCOTP_LOCK_OPS (1 << 19) +#define OCOTP_LOCK_UN2 (1 << 18) +#define OCOTP_LOCK_UN1 (1 << 17) +#define OCOTP_LOCK_UN0 (1 << 16) +#define OCOTP_LOCK_SRK (1 << 15) +#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) +#define OCOTP_LOCK_UNALLOCATED_OFFSET 12 +#define OCOTP_LOCK_SRK_SHADOW (1 << 11) +#define OCOTP_LOCK_ROM_SHADOW (1 << 10) +#define OCOTP_LOCK_CUSTCAP (1 << 9) +#define OCOTP_LOCK_HWSW (1 << 8) +#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) +#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) +#define OCOTP_LOCK_CRYPTODCP (1 << 5) +#define OCOTP_LOCK_CRYPTOKEY (1 << 4) +#define OCOTP_LOCK_CUST3 (1 << 3) +#define OCOTP_LOCK_CUST2 (1 << 2) +#define OCOTP_LOCK_CUST1 (1 << 1) +#define OCOTP_LOCK_CUST0 (1 << 0) + +#define OCOTP_OPS_BITS_MASK 0xffffffff +#define OCOTP_OPS_BITS_OFFSET 0 + +#define OCOTP_UN_BITS_MASK 0xffffffff +#define OCOTP_UN_BITS_OFFSET 0 + +#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) +#define OCOTP_ROM_BOOT_MODE_OFFSET 24 +#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) +#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 +#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) +#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 +#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) +#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 +#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) +#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 +#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) +#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 +#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) +#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) +#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) +#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) +#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) + +#define OCOTP_SRK_BITS_MASK 0xffffffff +#define OCOTP_SRK_BITS_OFFSET 0 + +#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) +#define OCOTP_VERSION_MAJOR_OFFSET 24 +#define OCOTP_VERSION_MINOR_MASK (0xff << 16) +#define OCOTP_VERSION_MINOR_OFFSET 16 +#define OCOTP_VERSION_STEP_MASK 0xffff +#define OCOTP_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_OCOTP_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h new file mode 100644 index 0000000000..73739cad54 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h @@ -0,0 +1,1284 @@ +/* + * Freescale i.MX28 PINCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_PINCTRL_H__ +#define __MX28_REGS_PINCTRL_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_pinctrl_regs { + mx28_reg(hw_pinctrl_ctrl) /* 0x0 */ + + uint32_t reserved1[60]; + + mx28_reg(hw_pinctrl_muxsel0) /* 0x100 */ + mx28_reg(hw_pinctrl_muxsel1) /* 0x110 */ + mx28_reg(hw_pinctrl_muxsel2) /* 0x120 */ + mx28_reg(hw_pinctrl_muxsel3) /* 0x130 */ + mx28_reg(hw_pinctrl_muxsel4) /* 0x140 */ + mx28_reg(hw_pinctrl_muxsel5) /* 0x150 */ + mx28_reg(hw_pinctrl_muxsel6) /* 0x160 */ + mx28_reg(hw_pinctrl_muxsel7) /* 0x170 */ + mx28_reg(hw_pinctrl_muxsel8) /* 0x180 */ + mx28_reg(hw_pinctrl_muxsel9) /* 0x190 */ + mx28_reg(hw_pinctrl_muxsel10) /* 0x1a0 */ + mx28_reg(hw_pinctrl_muxsel11) /* 0x1b0 */ + mx28_reg(hw_pinctrl_muxsel12) /* 0x1c0 */ + mx28_reg(hw_pinctrl_muxsel13) /* 0x1d0 */ + + uint32_t reserved2[72]; + + mx28_reg(hw_pinctrl_drive0) /* 0x300 */ + mx28_reg(hw_pinctrl_drive1) /* 0x310 */ + mx28_reg(hw_pinctrl_drive2) /* 0x320 */ + mx28_reg(hw_pinctrl_drive3) /* 0x330 */ + mx28_reg(hw_pinctrl_drive4) /* 0x340 */ + mx28_reg(hw_pinctrl_drive5) /* 0x350 */ + mx28_reg(hw_pinctrl_drive6) /* 0x360 */ + mx28_reg(hw_pinctrl_drive7) /* 0x370 */ + mx28_reg(hw_pinctrl_drive8) /* 0x380 */ + mx28_reg(hw_pinctrl_drive9) /* 0x390 */ + mx28_reg(hw_pinctrl_drive10) /* 0x3a0 */ + mx28_reg(hw_pinctrl_drive11) /* 0x3b0 */ + mx28_reg(hw_pinctrl_drive12) /* 0x3c0 */ + mx28_reg(hw_pinctrl_drive13) /* 0x3d0 */ + mx28_reg(hw_pinctrl_drive14) /* 0x3e0 */ + mx28_reg(hw_pinctrl_drive15) /* 0x3f0 */ + mx28_reg(hw_pinctrl_drive16) /* 0x400 */ + mx28_reg(hw_pinctrl_drive17) /* 0x410 */ + mx28_reg(hw_pinctrl_drive18) /* 0x420 */ + mx28_reg(hw_pinctrl_drive19) /* 0x430 */ + + uint32_t reserved3[112]; + + mx28_reg(hw_pinctrl_pull0) /* 0x600 */ + mx28_reg(hw_pinctrl_pull1) /* 0x610 */ + mx28_reg(hw_pinctrl_pull2) /* 0x620 */ + mx28_reg(hw_pinctrl_pull3) /* 0x630 */ + mx28_reg(hw_pinctrl_pull4) /* 0x640 */ + mx28_reg(hw_pinctrl_pull5) /* 0x650 */ + mx28_reg(hw_pinctrl_pull6) /* 0x660 */ + + uint32_t reserved4[36]; + + mx28_reg(hw_pinctrl_dout0) /* 0x700 */ + mx28_reg(hw_pinctrl_dout1) /* 0x710 */ + mx28_reg(hw_pinctrl_dout2) /* 0x720 */ + mx28_reg(hw_pinctrl_dout3) /* 0x730 */ + mx28_reg(hw_pinctrl_dout4) /* 0x740 */ + + uint32_t reserved5[108]; + + mx28_reg(hw_pinctrl_din0) /* 0x900 */ + mx28_reg(hw_pinctrl_din1) /* 0x910 */ + mx28_reg(hw_pinctrl_din2) /* 0x920 */ + mx28_reg(hw_pinctrl_din3) /* 0x930 */ + mx28_reg(hw_pinctrl_din4) /* 0x940 */ + + uint32_t reserved6[108]; + + mx28_reg(hw_pinctrl_doe0) /* 0xb00 */ + mx28_reg(hw_pinctrl_doe1) /* 0xb10 */ + mx28_reg(hw_pinctrl_doe2) /* 0xb20 */ + mx28_reg(hw_pinctrl_doe3) /* 0xb30 */ + mx28_reg(hw_pinctrl_doe4) /* 0xb40 */ + + uint32_t reserved7[300]; + + mx28_reg(hw_pinctrl_pin2irq0) /* 0x1000 */ + mx28_reg(hw_pinctrl_pin2irq1) /* 0x1010 */ + mx28_reg(hw_pinctrl_pin2irq2) /* 0x1020 */ + mx28_reg(hw_pinctrl_pin2irq3) /* 0x1030 */ + mx28_reg(hw_pinctrl_pin2irq4) /* 0x1040 */ + + uint32_t reserved8[44]; + + mx28_reg(hw_pinctrl_irqen0) /* 0x1100 */ + mx28_reg(hw_pinctrl_irqen1) /* 0x1110 */ + mx28_reg(hw_pinctrl_irqen2) /* 0x1120 */ + mx28_reg(hw_pinctrl_irqen3) /* 0x1130 */ + mx28_reg(hw_pinctrl_irqen4) /* 0x1140 */ + + uint32_t reserved9[44]; + + mx28_reg(hw_pinctrl_irqlevel0) /* 0x1200 */ + mx28_reg(hw_pinctrl_irqlevel1) /* 0x1210 */ + mx28_reg(hw_pinctrl_irqlevel2) /* 0x1220 */ + mx28_reg(hw_pinctrl_irqlevel3) /* 0x1230 */ + mx28_reg(hw_pinctrl_irqlevel4) /* 0x1240 */ + + uint32_t reserved10[44]; + + mx28_reg(hw_pinctrl_irqpol0) /* 0x1300 */ + mx28_reg(hw_pinctrl_irqpol1) /* 0x1310 */ + mx28_reg(hw_pinctrl_irqpol2) /* 0x1320 */ + mx28_reg(hw_pinctrl_irqpol3) /* 0x1330 */ + mx28_reg(hw_pinctrl_irqpol4) /* 0x1340 */ + + uint32_t reserved11[44]; + + mx28_reg(hw_pinctrl_irqstat0) /* 0x1400 */ + mx28_reg(hw_pinctrl_irqstat1) /* 0x1410 */ + mx28_reg(hw_pinctrl_irqstat2) /* 0x1420 */ + mx28_reg(hw_pinctrl_irqstat3) /* 0x1430 */ + mx28_reg(hw_pinctrl_irqstat4) /* 0x1440 */ + + uint32_t reserved12[380]; + + mx28_reg(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ + + uint32_t reserved13[76]; + + mx28_reg(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ +}; +#endif + +#define PINCTRL_CTRL_SFTRST (1 << 31) +#define PINCTRL_CTRL_CLKGATE (1 << 30) +#define PINCTRL_CTRL_PRESENT4 (1 << 24) +#define PINCTRL_CTRL_PRESENT3 (1 << 23) +#define PINCTRL_CTRL_PRESENT2 (1 << 22) +#define PINCTRL_CTRL_PRESENT1 (1 << 21) +#define PINCTRL_CTRL_PRESENT0 (1 << 20) +#define PINCTRL_CTRL_IRQOUT4 (1 << 4) +#define PINCTRL_CTRL_IRQOUT3 (1 << 3) +#define PINCTRL_CTRL_IRQOUT2 (1 << 2) +#define PINCTRL_CTRL_IRQOUT1 (1 << 1) +#define PINCTRL_CTRL_IRQOUT0 (1 << 0) + +#define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) +#define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 +#define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) +#define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 +#define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) +#define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 +#define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) +#define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 +#define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) +#define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 +#define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 + +#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) +#define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) +#define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) +#define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) +#define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) +#define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) +#define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) +#define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) +#define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) +#define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) +#define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) +#define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) +#define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) +#define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) +#define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) +#define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) +#define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) +#define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) +#define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) +#define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) +#define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) +#define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) +#define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) +#define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) +#define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) +#define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) +#define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) +#define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) +#define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) +#define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) +#define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) +#define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) +#define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) +#define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) +#define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) +#define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) +#define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) +#define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) +#define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) +#define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) +#define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) +#define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) +#define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) +#define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) +#define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) +#define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) +#define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 +#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) +#define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 +#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) +#define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 +#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) +#define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) +#define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) +#define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) +#define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) +#define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) +#define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) +#define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) +#define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) +#define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) +#define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) +#define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) +#define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) +#define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) +#define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) +#define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) +#define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) +#define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) +#define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) +#define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) +#define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) +#define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) +#define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) +#define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) +#define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) +#define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) +#define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) +#define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) +#define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) +#define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) +#define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) +#define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) +#define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) +#define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) +#define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) +#define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) +#define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) +#define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) +#define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) +#define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) +#define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) +#define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) +#define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) +#define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) +#define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) +#define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) +#define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) +#define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) +#define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) +#define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) +#define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) +#define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) +#define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) +#define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) +#define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 +#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) +#define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 +#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) +#define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) +#define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) +#define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) +#define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) +#define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) +#define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) +#define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) +#define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) +#define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) +#define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) +#define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) +#define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) +#define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) +#define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) +#define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) +#define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) +#define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) +#define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) +#define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) +#define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) +#define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) +#define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) +#define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 + +#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) +#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) +#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) +#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) +#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) +#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) +#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) +#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) +#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) +#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) +#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) +#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) +#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) +#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) +#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) +#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) +#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) +#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) +#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) +#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) +#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) + +#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) +#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) +#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) +#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) +#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) +#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) +#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) +#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) +#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) +#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) +#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) +#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) +#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) +#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) +#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) +#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) +#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) +#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) +#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) +#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) +#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) +#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) +#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) +#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) +#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) +#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) +#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) +#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) +#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) +#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) +#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) +#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) + +#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) +#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) +#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) +#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) +#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) +#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) +#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) +#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) +#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) +#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) +#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) +#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) +#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) +#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) +#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) +#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) +#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) +#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) +#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) +#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) +#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) +#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) +#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) +#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) +#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) + +#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) +#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) +#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) +#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) +#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) +#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) +#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) +#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) +#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) +#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) +#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) +#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) +#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) +#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) +#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) +#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) +#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) +#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) +#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) +#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) +#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) +#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) +#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) +#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) +#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) +#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) +#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) +#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) +#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) +#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) + +#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) +#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) +#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) +#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) +#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) +#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) +#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) +#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) +#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) +#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) +#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) +#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) +#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) +#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) +#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) +#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) +#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) +#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) + +#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) +#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) +#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) +#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) +#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) +#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) +#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) +#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) +#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) +#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) +#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) +#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) +#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) +#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) +#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) +#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) +#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) +#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) +#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) +#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) +#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) +#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) +#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) +#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) +#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) + +#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) +#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) +#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) +#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) +#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) +#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) +#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) +#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) +#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) +#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) +#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) +#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) +#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) +#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) +#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) +#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) +#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) +#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) +#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) +#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) +#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) +#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) +#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) +#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) + +#define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff +#define PINCTRL_DOUT0_DOUT_OFFSET 0 + +#define PINCTRL_DOUT1_DOUT_MASK 0xffffffff +#define PINCTRL_DOUT1_DOUT_OFFSET 0 + +#define PINCTRL_DOUT2_DOUT_MASK 0xfffffff +#define PINCTRL_DOUT2_DOUT_OFFSET 0 + +#define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff +#define PINCTRL_DOUT3_DOUT_OFFSET 0 + +#define PINCTRL_DOUT4_DOUT_MASK 0x1fffff +#define PINCTRL_DOUT4_DOUT_OFFSET 0 + +#define PINCTRL_DIN0_DIN_MASK 0x1fffffff +#define PINCTRL_DIN0_DIN_OFFSET 0 + +#define PINCTRL_DIN1_DIN_MASK 0xffffffff +#define PINCTRL_DIN1_DIN_OFFSET 0 + +#define PINCTRL_DIN2_DIN_MASK 0xfffffff +#define PINCTRL_DIN2_DIN_OFFSET 0 + +#define PINCTRL_DIN3_DIN_MASK 0x7fffffff +#define PINCTRL_DIN3_DIN_OFFSET 0 + +#define PINCTRL_DIN4_DIN_MASK 0x1fffff +#define PINCTRL_DIN4_DIN_OFFSET 0 + +#define PINCTRL_DOE0_DOE_MASK 0x1fffffff +#define PINCTRL_DOE0_DOE_OFFSET 0 + +#define PINCTRL_DOE1_DOE_MASK 0xffffffff +#define PINCTRL_DOE1_DOE_OFFSET 0 + +#define PINCTRL_DOE2_DOE_MASK 0xfffffff +#define PINCTRL_DOE2_DOE_OFFSET 0 + +#define PINCTRL_DOE3_DOE_MASK 0x7fffffff +#define PINCTRL_DOE3_DOE_OFFSET 0 + +#define PINCTRL_DOE4_DOE_MASK 0x1fffff +#define PINCTRL_DOE4_DOE_OFFSET 0 + +#define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff +#define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff +#define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff +#define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff +#define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff +#define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 + +#define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff +#define PINCTRL_IRQEN0_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff +#define PINCTRL_IRQEN1_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff +#define PINCTRL_IRQEN2_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff +#define PINCTRL_IRQEN3_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff +#define PINCTRL_IRQEN4_IRQEN_OFFSET 0 + +#define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff +#define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff +#define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff +#define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff +#define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff +#define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff +#define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff +#define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff +#define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff +#define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff +#define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff +#define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff +#define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff +#define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff +#define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff +#define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 + +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 +#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) +#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 +#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) +#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 +#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) +#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 +#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) +#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 +#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) +#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 +#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) +#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 +#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) +#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 +#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) +#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 +#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) +#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 +#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) +#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 + +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) +#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) +#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 +#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) +#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 +#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) +#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 +#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) +#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 +#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) +#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 +#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) +#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 +#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) +#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 + +#endif /* __MX28_REGS_PINCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-power.h b/arch/arm/include/asm/arch-mx28/regs-power.h new file mode 100644 index 0000000000..9da63adc2e --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-power.h @@ -0,0 +1,413 @@ +/* + * Freescale i.MX28 Power Controller Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_POWER_H__ +#define __MX28_REGS_POWER_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_power_regs { + mx28_reg(hw_power_ctrl) + mx28_reg(hw_power_5vctrl) + mx28_reg(hw_power_minpwr) + mx28_reg(hw_power_charge) + uint32_t hw_power_vdddctrl; + uint32_t reserved_vddd[3]; + uint32_t hw_power_vddactrl; + uint32_t reserved_vdda[3]; + uint32_t hw_power_vddioctrl; + uint32_t reserved_vddio[3]; + uint32_t hw_power_vddmemctrl; + uint32_t reserved_vddmem[3]; + uint32_t hw_power_dcdc4p2; + uint32_t reserved_dcdc4p2[3]; + uint32_t hw_power_misc; + uint32_t reserved_misc[3]; + uint32_t hw_power_dclimits; + uint32_t reserved_dclimits[3]; + mx28_reg(hw_power_loopctrl) + uint32_t hw_power_sts; + uint32_t reserved_sts[3]; + mx28_reg(hw_power_speed) + uint32_t hw_power_battmonitor; + uint32_t reserved_battmonitor[3]; + + uint32_t reserved[4]; + + mx28_reg(hw_power_reset) + mx28_reg(hw_power_debug) + mx28_reg(hw_power_thermal) + mx28_reg(hw_power_usb1ctrl) + mx28_reg(hw_power_special) + mx28_reg(hw_power_version) + mx28_reg(hw_power_anaclkctrl) + mx28_reg(hw_power_refctrl) +}; +#endif + +#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) +#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) +#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) +#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) +#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) +#define POWER_CTRL_PSWITCH_IRQ (1 << 20) +#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) +#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) +#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) +#define POWER_CTRL_POLARITY_DC_OK (1 << 16) +#define POWER_CTRL_DC_OK_IRQ (1 << 15) +#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) +#define POWER_CTRL_BATT_BO_IRQ (1 << 13) +#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) +#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) +#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) +#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) +#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) +#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) +#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) +#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) +#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) +#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) +#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) +#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) +#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) + +#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) +#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) +#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 +#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) +#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 +#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 +#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) +#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) +#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) +#define POWER_5VCTRL_DCDC_XFER (1 << 5) +#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) +#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) +#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) +#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) +#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) + +#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) +#define POWER_MINPWR_PWD_BO (1 << 12) +#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) +#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) +#define POWER_MINPWR_ENABLE_OSC (1 << 9) +#define POWER_MINPWR_SELECT_OSC (1 << 8) +#define POWER_MINPWR_FBG_OFF (1 << 7) +#define POWER_MINPWR_DOUBLE_FETS (1 << 6) +#define POWER_MINPWR_HALFFETS (1 << 5) +#define POWER_MINPWR_LESSANA_I (1 << 4) +#define POWER_MINPWR_PWD_XTAL24 (1 << 3) +#define POWER_MINPWR_DC_STOPCLK (1 << 2) +#define POWER_MINPWR_EN_DC_PFM (1 << 1) +#define POWER_MINPWR_DC_HALFCLK (1 << 0) + +#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) +#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 +#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) +#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) +#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) +#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) +#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) +#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) +#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) +#define POWER_CHARGE_ENABLE_LOAD (1 << 22) +#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) +#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) +#define POWER_CHARGE_LIION_4P1 (1 << 18) +#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) +#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) +#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) +#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) +#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 +#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) +#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) +#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) +#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) +#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f +#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 +#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 +#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 +#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 +#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 +#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 +#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 + +#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) +#define POWER_VDDDCTRL_ADJTN_OFFSET 28 +#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) +#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) +#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) +#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) +#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 +#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) +#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDDCTRL_TRG_MASK 0x1f +#define POWER_VDDDCTRL_TRG_OFFSET 0 + +#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) +#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) +#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) +#define POWER_VDDACTRL_DISABLE_FET (1 << 16) +#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDACTRL_TRG_MASK 0x1f +#define POWER_VDDACTRL_TRG_OFFSET 0 + +#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) +#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 +#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) +#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) +#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) +#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDIOCTRL_TRG_MASK 0x1f +#define POWER_VDDIOCTRL_TRG_OFFSET 0 + +#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) +#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) +#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) +#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) +#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 +#define POWER_VDDMEMCTRL_TRG_MASK 0x1f +#define POWER_VDDMEMCTRL_TRG_OFFSET 0 + +#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 +#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) +#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) +#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 +#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) +#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) +#define POWER_DCDC4P2_HYST_DIR (1 << 21) +#define POWER_DCDC4P2_HYST_THRESH (1 << 20) +#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) +#define POWER_DCDC4P2_TRG_OFFSET 16 +#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) +#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) +#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) +#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) +#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) +#define POWER_DCDC4P2_BO_MASK (0x1f << 8) +#define POWER_DCDC4P2_BO_OFFSET 8 +#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f +#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 + +#define POWER_MISC_FREQSEL_MASK (0x7 << 4) +#define POWER_MISC_FREQSEL_OFFSET 4 +#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) +#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) +#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) +#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) +#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) +#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) +#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) +#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) +#define POWER_MISC_DELAY_TIMING (1 << 2) +#define POWER_MISC_TEST (1 << 1) +#define POWER_MISC_SEL_PLLCLK (1 << 0) + +#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) +#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 +#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f +#define POWER_DCLIMITS_NETLIMIT_OFFSET 0 + +#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) +#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) +#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) +#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) +#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) +#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) +#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) +#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 +#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) +#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) +#define POWER_LOOPCTRL_DC_FF_OFFSET 8 +#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) +#define POWER_LOOPCTRL_DC_R_OFFSET 4 +#define POWER_LOOPCTRL_DC_C_MASK 0x3 +#define POWER_LOOPCTRL_DC_C_OFFSET 0 +#define POWER_LOOPCTRL_DC_C_MAX 0x0 +#define POWER_LOOPCTRL_DC_C_2X 0x1 +#define POWER_LOOPCTRL_DC_C_4X 0x2 +#define POWER_LOOPCTRL_DC_C_MIN 0x3 + +#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) +#define POWER_STS_PWRUP_SOURCE_OFFSET 24 +#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) +#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) +#define POWER_STS_PSWITCH_MASK (0x3 << 20) +#define POWER_STS_PSWITCH_OFFSET 20 +#define POWER_STS_THERMAL_WARNING (1 << 19) +#define POWER_STS_VDDMEM_BO (1 << 18) +#define POWER_STS_AVALID0_STATUS (1 << 17) +#define POWER_STS_BVALID0_STATUS (1 << 16) +#define POWER_STS_VBUSVALID0_STATUS (1 << 15) +#define POWER_STS_SESSEND0_STATUS (1 << 14) +#define POWER_STS_BATT_BO (1 << 13) +#define POWER_STS_VDD5V_FAULT (1 << 12) +#define POWER_STS_CHRGSTS (1 << 11) +#define POWER_STS_DCDC_4P2_BO (1 << 10) +#define POWER_STS_DC_OK (1 << 9) +#define POWER_STS_VDDIO_BO (1 << 8) +#define POWER_STS_VDDA_BO (1 << 7) +#define POWER_STS_VDDD_BO (1 << 6) +#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) +#define POWER_STS_VDD5V_DROOP (1 << 4) +#define POWER_STS_AVALID0 (1 << 3) +#define POWER_STS_BVALID0 (1 << 2) +#define POWER_STS_VBUSVALID0 (1 << 1) +#define POWER_STS_SESSEND0 (1 << 0) + +#define POWER_SPEED_STATUS_MASK (0xffff << 8) +#define POWER_SPEED_STATUS_OFFSET 8 +#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) +#define POWER_SPEED_STATUS_SEL_OFFSET 6 +#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) +#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) +#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) +#define POWER_SPEED_CTRL_MASK 0x3 +#define POWER_SPEED_CTRL_OFFSET 0 +#define POWER_SPEED_CTRL_SS_OFF 0x0 +#define POWER_SPEED_CTRL_SS_ON 0x1 +#define POWER_SPEED_CTRL_SS_ENABLE 0x3 + +#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) +#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) +#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) +#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) +#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f +#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 + +#define POWER_RESET_UNLOCK_MASK (0xffff << 16) +#define POWER_RESET_UNLOCK_OFFSET 16 +#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) +#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) +#define POWER_RESET_PWD_OFF (1 << 1) +#define POWER_RESET_PWD (1 << 0) + +#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) +#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) +#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) +#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) + +#define POWER_THERMAL_TEST (1 << 8) +#define POWER_THERMAL_PWD (1 << 7) +#define POWER_THERMAL_LOW_POWER (1 << 6) +#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) +#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 +#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) +#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 +#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 + +#define POWER_USB1CTRL_AVALID1 (1 << 3) +#define POWER_USB1CTRL_BVALID1 (1 << 2) +#define POWER_USB1CTRL_VBUSVALID1 (1 << 1) +#define POWER_USB1CTRL_SESSEND1 (1 << 0) + +#define POWER_SPECIAL_TEST_MASK 0xffffffff +#define POWER_SPECIAL_TEST_OFFSET 0 + +#define POWER_VERSION_MAJOR_MASK (0xff << 24) +#define POWER_VERSION_MAJOR_OFFSET 24 +#define POWER_VERSION_MINOR_MASK (0xff << 16) +#define POWER_VERSION_MINOR_OFFSET 16 +#define POWER_VERSION_STEP_MASK 0xffff +#define POWER_VERSION_STEP_OFFSET 0 + +#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) +#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) +#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 +#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) +#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) +#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) +#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) +#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) +#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) +#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 +#define POWER_ANACLKCTRL_INDIV_MASK 0x7 +#define POWER_ANACLKCTRL_INDIV_OFFSET 0 + +#define POWER_REFCTRL_FASTSETTLING (1 << 26) +#define POWER_REFCTRL_RAISE_REF (1 << 25) +#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) +#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) +#define POWER_REFCTRL_VBG_ADJ_OFFSET 20 +#define POWER_REFCTRL_LOW_PWR (1 << 19) +#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) +#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 +#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) +#define POWER_REFCTRL_ADJ_ANA (1 << 13) +#define POWER_REFCTRL_ADJ_VAG (1 << 12) +#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) +#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 +#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) +#define POWER_REFCTRL_VAG_VAL_OFFSET 4 + +#endif /* __MX28_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-rtc.h b/arch/arm/include/asm/arch-mx28/regs-rtc.h new file mode 100644 index 0000000000..fe2fda9655 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-rtc.h @@ -0,0 +1,147 @@ +/* + * Freescale i.MX28 RTC Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_RTC_H__ +#define __MX28_REGS_RTC_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_rtc_regs { + mx28_reg(hw_rtc_ctrl) + mx28_reg(hw_rtc_stat) + mx28_reg(hw_rtc_milliseconds) + mx28_reg(hw_rtc_seconds) + mx28_reg(hw_rtc_rtc_alarm) + mx28_reg(hw_rtc_watchdog) + mx28_reg(hw_rtc_persistent0) + mx28_reg(hw_rtc_persistent1) + mx28_reg(hw_rtc_persistent2) + mx28_reg(hw_rtc_persistent3) + mx28_reg(hw_rtc_persistent4) + mx28_reg(hw_rtc_persistent5) + mx28_reg(hw_rtc_debug) + mx28_reg(hw_rtc_version) +}; +#endif + +#define RTC_CTRL_SFTRST (1 << 31) +#define RTC_CTRL_CLKGATE (1 << 30) +#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) +#define RTC_CTRL_FORCE_UPDATE (1 << 5) +#define RTC_CTRL_WATCHDOGEN (1 << 4) +#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) +#define RTC_CTRL_ALARM_IRQ (1 << 2) +#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) +#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) + +#define RTC_STAT_RTC_PRESENT (1 << 31) +#define RTC_STAT_ALARM_PRESENT (1 << 30) +#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) +#define RTC_STAT_XTAL32000_PRESENT (1 << 28) +#define RTC_STAT_XTAL32768_PRESENT (1 << 27) +#define RTC_STAT_STALE_REGS_MASK (0xff << 16) +#define RTC_STAT_STALE_REGS_OFFSET 16 +#define RTC_STAT_NEW_REGS_MASK (0xff << 8) +#define RTC_STAT_NEW_REGS_OFFSET 8 + +#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff +#define RTC_MILLISECONDS_COUNT_OFFSET 0 + +#define RTC_SECONDS_COUNT_MASK 0xffffffff +#define RTC_SECONDS_COUNT_OFFSET 0 + +#define RTC_ALARM_VALUE_MASK 0xffffffff +#define RTC_ALARM_VALUE_OFFSET 0 + +#define RTC_WATCHDOG_COUNT_MASK 0xffffffff +#define RTC_WATCHDOG_COUNT_OFFSET 0 + +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) +#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) +#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) +#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) +#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) +#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) +#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) +#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 +#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) +#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) +#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) +#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 +#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) +#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) +#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) +#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) +#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) +#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) +#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) +#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) +#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) +#define RTC_PERSISTENT0_LCK_SECS (1 << 3) +#define RTC_PERSISTENT0_ALARM_EN (1 << 2) +#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) +#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) + +#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT1_GENERAL_OFFSET 0 +#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 +#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 +#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 +#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 +#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 +#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 + +#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT2_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT3_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT4_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT5_GENERAL_OFFSET 0 + +#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) +#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) + +#define RTC_VERSION_MAJOR_MASK (0xff << 24) +#define RTC_VERSION_MAJOR_OFFSET 24 +#define RTC_VERSION_MINOR_MASK (0xff << 16) +#define RTC_VERSION_MINOR_OFFSET 16 +#define RTC_VERSION_STEP_MASK 0xffff +#define RTC_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_RTC_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-ssp.h b/arch/arm/include/asm/arch-mx28/regs-ssp.h new file mode 100644 index 0000000000..ab3870c149 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-ssp.h @@ -0,0 +1,349 @@ +/* + * Freescale i.MX28 SSP Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_SSP_H__ +#define __MX28_REGS_SSP_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_ssp_regs { + mx28_reg(hw_ssp_ctrl0) + mx28_reg(hw_ssp_cmd0) + mx28_reg(hw_ssp_cmd1) + mx28_reg(hw_ssp_xfer_size) + mx28_reg(hw_ssp_block_size) + mx28_reg(hw_ssp_compref) + mx28_reg(hw_ssp_compmask) + mx28_reg(hw_ssp_timing) + mx28_reg(hw_ssp_ctrl1) + mx28_reg(hw_ssp_data) + mx28_reg(hw_ssp_sdresp0) + mx28_reg(hw_ssp_sdresp1) + mx28_reg(hw_ssp_sdresp2) + mx28_reg(hw_ssp_sdresp3) + mx28_reg(hw_ssp_ddr_ctrl) + mx28_reg(hw_ssp_dll_ctrl) + mx28_reg(hw_ssp_status) + mx28_reg(hw_ssp_dll_sts) + mx28_reg(hw_ssp_debug) + mx28_reg(hw_ssp_version) +}; +#endif + +#define SSP_CTRL0_SFTRST (1 << 31) +#define SSP_CTRL0_CLKGATE (1 << 30) +#define SSP_CTRL0_RUN (1 << 29) +#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) +#define SSP_CTRL0_LOCK_CS (1 << 27) +#define SSP_CTRL0_IGNORE_CRC (1 << 26) +#define SSP_CTRL0_READ (1 << 25) +#define SSP_CTRL0_DATA_XFER (1 << 24) +#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) +#define SSP_CTRL0_BUS_WIDTH_OFFSET 22 +#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) +#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) +#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) +#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) +#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) +#define SSP_CTRL0_LONG_RESP (1 << 19) +#define SSP_CTRL0_CHECK_RESP (1 << 18) +#define SSP_CTRL0_GET_RESP (1 << 17) +#define SSP_CTRL0_ENABLE (1 << 16) + +#define SSP_CMD0_SOFT_TERMINATE (1 << 26) +#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) +#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) +#define SSP_CMD0_BOOT_ACK_EN (1 << 23) +#define SSP_CMD0_SLOW_CLKING_EN (1 << 22) +#define SSP_CMD0_CONT_CLKING_EN (1 << 21) +#define SSP_CMD0_APPEND_8CYC (1 << 20) +#define SSP_CMD0_CMD_MASK 0xff +#define SSP_CMD0_CMD_OFFSET 0 +#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 +#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 +#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 +#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 +#define SSP_CMD0_CMD_MMC_SET_DSR 0x04 +#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 +#define SSP_CMD0_CMD_MMC_SWITCH 0x06 +#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 +#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 +#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 +#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a +#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b +#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c +#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d +#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e +#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f +#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 +#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 +#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 +#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 +#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 +#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 +#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a +#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b +#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c +#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d +#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e +#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 +#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 +#define SSP_CMD0_CMD_MMC_ERASE 0x26 +#define SSP_CMD0_CMD_MMC_FAST_IO 0x27 +#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 +#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a +#define SSP_CMD0_CMD_MMC_APP_CMD 0x37 +#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 +#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 +#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 +#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 +#define SSP_CMD0_CMD_SD_SET_DSR 0x04 +#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 +#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 +#define SSP_CMD0_CMD_SD_SEND_CSD 0x09 +#define SSP_CMD0_CMD_SD_SEND_CID 0x0a +#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c +#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d +#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f +#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 +#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 +#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 +#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 +#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 +#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b +#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c +#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d +#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e +#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 +#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 +#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 +#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 +#define SSP_CMD0_CMD_SD_ERASE 0x26 +#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a +#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 +#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 +#define SSP_CMD0_CMD_SD_APP_CMD 0x37 +#define SSP_CMD0_CMD_SD_GEN_CMD 0x38 + +#define SSP_CMD1_CMD_ARG_MASK 0xffffffff +#define SSP_CMD1_CMD_ARG_OFFSET 0 + +#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff +#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 + +#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) +#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 +#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf +#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 + +#define SSP_COMPREF_REFERENCE_MASK 0xffffffff +#define SSP_COMPREF_REFERENCE_OFFSET 0 + +#define SSP_COMPMASK_MASK_MASK 0xffffffff +#define SSP_COMPMASK_MASK_OFFSET 0 + +#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) +#define SSP_TIMING_TIMEOUT_OFFSET 16 +#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) +#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 +#define SSP_TIMING_CLOCK_RATE_MASK 0xff +#define SSP_TIMING_CLOCK_RATE_OFFSET 0 + +#define SSP_CTRL1_SDIO_IRQ (1 << 31) +#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) +#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) +#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) +#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) +#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) +#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) +#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) +#define SSP_CTRL1_DMA_ENABLE (1 << 13) +#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) +#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) +#define SSP_CTRL1_PHASE (1 << 10) +#define SSP_CTRL1_POLARITY (1 << 9) +#define SSP_CTRL1_SLAVE_MODE (1 << 8) +#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) +#define SSP_CTRL1_WORD_LENGTH_OFFSET 4 +#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) +#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) +#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) +#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) +#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) +#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) +#define SSP_CTRL1_SSP_MODE_MASK 0xf +#define SSP_CTRL1_SSP_MODE_OFFSET 0 +#define SSP_CTRL1_SSP_MODE_SPI 0x0 +#define SSP_CTRL1_SSP_MODE_SSI 0x1 +#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 +#define SSP_CTRL1_SSP_MODE_MS 0x4 + +#define SSP_DATA_DATA_MASK 0xffffffff +#define SSP_DATA_DATA_OFFSET 0 + +#define SSP_SDRESP0_RESP0_MASK 0xffffffff +#define SSP_SDRESP0_RESP0_OFFSET 0 + +#define SSP_SDRESP1_RESP1_MASK 0xffffffff +#define SSP_SDRESP1_RESP1_OFFSET 0 + +#define SSP_SDRESP2_RESP2_MASK 0xffffffff +#define SSP_SDRESP2_RESP2_OFFSET 0 + +#define SSP_SDRESP3_RESP3_MASK 0xffffffff +#define SSP_SDRESP3_RESP3_OFFSET 0 + +#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) +#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 +#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) +#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) + +#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) +#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 +#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) +#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 +#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) +#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 +#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) +#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) +#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) +#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 +#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) +#define SSP_DLL_CTRL_RESET (1 << 1) +#define SSP_DLL_CTRL_ENABLE (1 << 0) + +#define SSP_STATUS_PRESENT (1 << 31) +#define SSP_STATUS_MS_PRESENT (1 << 30) +#define SSP_STATUS_SD_PRESENT (1 << 29) +#define SSP_STATUS_CARD_DETECT (1 << 28) +#define SSP_STATUS_DMABURST (1 << 22) +#define SSP_STATUS_DMASENSE (1 << 21) +#define SSP_STATUS_DMATERM (1 << 20) +#define SSP_STATUS_DMAREQ (1 << 19) +#define SSP_STATUS_DMAEND (1 << 18) +#define SSP_STATUS_SDIO_IRQ (1 << 17) +#define SSP_STATUS_RESP_CRC_ERR (1 << 16) +#define SSP_STATUS_RESP_ERR (1 << 15) +#define SSP_STATUS_RESP_TIMEOUT (1 << 14) +#define SSP_STATUS_DATA_CRC_ERR (1 << 13) +#define SSP_STATUS_TIMEOUT (1 << 12) +#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) +#define SSP_STATUS_CEATA_CCS_ERR (1 << 10) +#define SSP_STATUS_FIFO_OVRFLW (1 << 9) +#define SSP_STATUS_FIFO_FULL (1 << 8) +#define SSP_STATUS_FIFO_EMPTY (1 << 5) +#define SSP_STATUS_FIFO_UNDRFLW (1 << 4) +#define SSP_STATUS_CMD_BUSY (1 << 3) +#define SSP_STATUS_DATA_BUSY (1 << 2) +#define SSP_STATUS_BUSY (1 << 0) + +#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) +#define SSP_DLL_STS_REF_SEL_OFFSET 8 +#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) +#define SSP_DLL_STS_SLV_SEL_OFFSET 2 +#define SSP_DLL_STS_REF_LOCK (1 << 1) +#define SSP_DLL_STS_SLV_LOCK (1 << 0) + +#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) +#define SSP_DEBUG_DATACRC_ERR_OFFSET 28 +#define SSP_DEBUG_DATA_STALL (1 << 27) +#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) +#define SSP_DEBUG_DAT_SM_OFFSET 24 +#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) +#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) +#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) +#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) +#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) +#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) +#define SSP_DEBUG_MSTK_SM_OFFSET 20 +#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) +#define SSP_DEBUG_CMD_OE (1 << 19) +#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) +#define SSP_DEBUG_DMA_SM_OFFSET 16 +#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) +#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) +#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) +#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) +#define SSP_DEBUG_MMC_SM_MASK (0xf << 12) +#define SSP_DEBUG_MMC_SM_OFFSET 12 +#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) +#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) +#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) +#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) +#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) +#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) +#define SSP_DEBUG_CMD_SM_OFFSET 10 +#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) +#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) +#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) +#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) +#define SSP_DEBUG_SSP_CMD (1 << 9) +#define SSP_DEBUG_SSP_RESP (1 << 8) +#define SSP_DEBUG_SSP_RXD_MASK 0xff +#define SSP_DEBUG_SSP_RXD_OFFSET 0 + +#define SSP_VERSION_MAJOR_MASK (0xff << 24) +#define SSP_VERSION_MAJOR_OFFSET 24 +#define SSP_VERSION_MINOR_MASK (0xff << 16) +#define SSP_VERSION_MINOR_OFFSET 16 +#define SSP_VERSION_STEP_MASK 0xffff +#define SSP_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_SSP_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-timrot.h b/arch/arm/include/asm/arch-mx28/regs-timrot.h new file mode 100644 index 0000000000..1b941cf289 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-timrot.h @@ -0,0 +1,171 @@ +/* + * Freescale i.MX28 TIMROT Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_TIMROT_H__ +#define __MX28_REGS_TIMROT_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_timrot_regs { + mx28_reg(hw_timrot_rotctrl) + mx28_reg(hw_timrot_rotcount) + mx28_reg(hw_timrot_timctrl0) + mx28_reg(hw_timrot_running_count0) + mx28_reg(hw_timrot_fixed_count0) + mx28_reg(hw_timrot_match_count0) + mx28_reg(hw_timrot_timctrl1) + mx28_reg(hw_timrot_running_count1) + mx28_reg(hw_timrot_fixed_count1) + mx28_reg(hw_timrot_match_count1) + mx28_reg(hw_timrot_timctrl2) + mx28_reg(hw_timrot_running_count2) + mx28_reg(hw_timrot_fixed_count2) + mx28_reg(hw_timrot_match_count2) + mx28_reg(hw_timrot_timctrl3) + mx28_reg(hw_timrot_running_count3) + mx28_reg(hw_timrot_fixed_count3) + mx28_reg(hw_timrot_match_count3) + mx28_reg(hw_timrot_version) +}; +#endif + +#define TIMROT_ROTCTRL_SFTRST (1 << 31) +#define TIMROT_ROTCTRL_CLKGATE (1 << 30) +#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) +#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) +#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) +#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) +#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) +#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) +#define TIMROT_ROTCTRL_STATE_OFFSET 22 +#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) +#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 +#define TIMROT_ROTCTRL_RELATIVE (1 << 12) +#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 +#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) +#define TIMROT_ROTCTRL_POLARITY_B (1 << 9) +#define TIMROT_ROTCTRL_POLARITY_A (1 << 8) +#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) +#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 +#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) +#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf +#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 +#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 +#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 +#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 +#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 +#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 +#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 +#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 +#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 +#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa + +#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff +#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 + +#define TIMROT_TIMCTRLn_IRQ (1 << 15) +#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) +#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) +#define TIMROT_TIMCTRLn_POLARITY (1 << 8) +#define TIMROT_TIMCTRLn_UPDATE (1 << 7) +#define TIMROT_TIMCTRLn_RELOAD (1 << 6) +#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) +#define TIMROT_TIMCTRLn_SELECT_MASK 0xf +#define TIMROT_TIMCTRLn_SELECT_OFFSET 0 +#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 +#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 +#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 +#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 +#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 +#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 +#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 +#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 +#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 +#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 +#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa +#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb +#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc +#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd +#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe +#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf + +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 + +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 + +#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff +#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 + +#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 +#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) +#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) + +#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) +#define TIMROT_VERSION_MAJOR_OFFSET 24 +#define TIMROT_VERSION_MINOR_MASK (0xff << 16) +#define TIMROT_VERSION_MINOR_OFFSET 16 +#define TIMROT_VERSION_STEP_MASK 0xffff +#define TIMROT_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_TIMROT_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-usb.h b/arch/arm/include/asm/arch-mx28/regs-usb.h new file mode 100644 index 0000000000..ea61de80d8 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-usb.h @@ -0,0 +1,178 @@ +/* + * Freescale i.MX28 USB OTG Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __REGS_USB_H__ +#define __REGS_USB_H__ + +struct mx28_usb_regs { + uint32_t hw_usbctrl_id; /* 0x000 */ + uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ + uint32_t hw_usbctrl_hwhost; /* 0x008 */ + uint32_t hw_usbctrl_hwdevice; /* 0x00c */ + uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ + uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ + + uint32_t reserved1[26]; + + uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ + uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ + uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ + uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ + uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ + + uint32_t reserved2[27]; + + uint32_t hw_usbctrl_caplength; /* 0x100 */ + uint32_t hw_usbctrl_hcsparams; /* 0x104 */ + uint32_t hw_usbctrl_hccparams; /* 0x108 */ + + uint32_t reserved3[5]; + + uint32_t hw_usbctrl_dciversion; /* 0x120 */ + uint32_t hw_usbctrl_dccparams; /* 0x124 */ + + uint32_t reserved4[6]; + + uint32_t hw_usbctrl_usbcmd; /* 0x140 */ + uint32_t hw_usbctrl_usbsts; /* 0x144 */ + uint32_t hw_usbctrl_usbintr; /* 0x148 */ + uint32_t hw_usbctrl_frindex; /* 0x14c */ + + uint32_t reserved5; + + union { + uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ + uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ + }; + union { + uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ + uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ + }; + + uint32_t hw_usbctrl_ttctrl; /* 0x15c */ + uint32_t hw_usbctrl_burstsize; /* 0x160 */ + uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ + + uint32_t reserved6; + + uint32_t hw_usbctrl_ic_usb; /* 0x16c */ + uint32_t hw_usbctrl_ulpi; /* 0x170 */ + + uint32_t reserved7; + + uint32_t hw_usbctrl_endptnak; /* 0x178 */ + uint32_t hw_usbctrl_endptnaken; /* 0x17c */ + + uint32_t reserved8; + + uint32_t hw_usbctrl_portsc1; /* 0x184 */ + + uint32_t reserved9[7]; + + uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ + uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ + uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ + uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ + uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ + uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ + uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ + uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ + uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ + uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ + uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ + uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ + uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ + uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ + uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ +}; + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) + +#define HW_USBCTRL_ID_CIVERSION_OFFSET 29 +#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) +#define HW_USBCTRL_ID_VERSION_OFFSET 25 +#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) +#define HW_USBCTRL_ID_REVISION_OFFSET 21 +#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) +#define HW_USBCTRL_ID_TAG_OFFSET 16 +#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) +#define HW_USBCTRL_ID_NID_OFFSET 8 +#define HW_USBCTRL_ID_NID_MASK (0x3f << 8) +#define HW_USBCTRL_ID_ID_OFFSET 0 +#define HW_USBCTRL_ID_ID_MASK (0x3f << 0) + +#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 +#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) +#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 +#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) +#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 +#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) +#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) +#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 +#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) +#define HW_USBCTRL_HWGENERAL_RT (1 << 0) + +#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 +#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) +#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 +#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) +#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 +#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) +#define HW_USBCTRL_HWHOST_HC (1 << 0) + +#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 +#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) +#define HW_USBCTRL_HWDEVICE_DC (1 << 0) + +#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) +#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 +#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) +#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 +#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) +#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 +#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff + +#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 +#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) +#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 +#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff + +#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 +#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff + +#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) +#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) +#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) +#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 +#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff + +#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 +#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 + +#endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-usbphy.h b/arch/arm/include/asm/arch-mx28/regs-usbphy.h new file mode 100644 index 0000000000..e823e1997d --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-usbphy.h @@ -0,0 +1,151 @@ +/* + * Freescale i.MX28 USB PHY Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __REGS_USBPHY_H__ +#define __REGS_USBPHY_H__ + +struct mx28_usbphy_regs { + mx28_reg(hw_usbphy_pwd) + mx28_reg(hw_usbphy_tx) + mx28_reg(hw_usbphy_rx) + mx28_reg(hw_usbphy_ctrl) + mx28_reg(hw_usbphy_status) + mx28_reg(hw_usbphy_debug) + mx28_reg(hw_usbphy_debug0_status) + mx28_reg(hw_usbphy_debug1) + mx28_reg(hw_usbphy_version) + mx28_reg(hw_usbphy_ip) +}; + +#define USBPHY_PWD_RXPWDRX (1 << 20) +#define USBPHY_PWD_RXPWDDIFF (1 << 19) +#define USBPHY_PWD_RXPWD1PT1 (1 << 18) +#define USBPHY_PWD_RXPWDENV (1 << 17) +#define USBPHY_PWD_TXPWDV2I (1 << 12) +#define USBPHY_PWD_TXPWDIBIAS (1 << 11) +#define USBPHY_PWD_TXPWDFS (1 << 10) + +#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) +#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) +#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) +#define USBPHY_TX_TXENCAL45DP (1 << 21) +#define USBPHY_TX_TXCAL45DP_OFFSET 16 +#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) +#define USBPHY_TX_TXENCAL45DM (1 << 13) +#define USBPHY_TX_TXCAL45DM_OFFSET 8 +#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) +#define USBPHY_TX_D_CAL_OFFSET 0 +#define USBPHY_TX_D_CAL_MASK 0xf + +#define USBPHY_RX_RXDBYPASS (1 << 22) +#define USBPHY_RX_DISCONADJ_OFFSET 4 +#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) +#define USBPHY_RX_ENVADJ_OFFSET 0 +#define USBPHY_RX_ENVADJ_MASK 0x7 + +#define USBPHY_CTRL_SFTRST (1 << 31) +#define USBPHY_CTRL_CLKGATE (1 << 30) +#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) +#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) +#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) +#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) +#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) +#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) +#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) +#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) +#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) +#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) +#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) +#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) +#define USBPHY_CTRL_RESUME_IRQ (1 << 10) +#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) +#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) +#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) +#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) +#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) +#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) + +#define USBPHY_STATUS_RESUME_STATUS (1 << 10) +#define USBPHY_STATUS_OTGID_STATUS (1 << 8) +#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) + +#define USBPHY_DEBUG_CLKGATE (1 << 30) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) +#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) +#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) +#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) +#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) +#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) +#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) + +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff + +#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) +#define USBPHY_DEBUG1_ENTX2TX (1 << 12) +#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 +#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf + +#define USBPHY_VERSION_MAJOR_MASK (0xff << 24) +#define USBPHY_VERSION_MAJOR_OFFSET 24 +#define USBPHY_VERSION_MINOR_MASK (0xff << 16) +#define USBPHY_VERSION_MINOR_OFFSET 16 +#define USBPHY_VERSION_STEP_MASK 0xffff +#define USBPHY_VERSION_STEP_OFFSET 0 + +#define USBPHY_IP_DIV_SEL_OFFSET 23 +#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) +#define USBPHY_IP_LFR_SEL_OFFSET 21 +#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) +#define USBPHY_IP_CP_SEL_OFFSET 19 +#define USBPHY_IP_CP_SEL_MASK (0x3 << 19) +#define USBPHY_IP_TSTI_TX_DP (1 << 18) +#define USBPHY_IP_TSTI_TX_DM (1 << 17) +#define USBPHY_IP_ANALOG_TESTMODE (1 << 16) +#define USBPHY_IP_EN_USB_CLKS (1 << 2) +#define USBPHY_IP_PLL_LOCKED (1 << 1) +#define USBPHY_IP_PLL_POWER (1 << 0) + +#endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h new file mode 100644 index 0000000000..a226ea4840 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/sys_proto.h @@ -0,0 +1,32 @@ +/* + * Freescale i.MX28 MX28 specific functions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_H__ +#define __MX28_H__ + +int mx28_reset_block(struct mx28_register *reg); +int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout); +int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout); + +int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)); + +#endif /* __MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index afdaa1ce6c..6a517ddd93 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -98,6 +98,12 @@ struct iim_regs { u32 iim_scs3; }; +struct iomuxc_regs { + u32 unused1; + u32 unused2; + u32 gpr; +}; + struct mx3_cpu_type { u8 srev; u32 v; @@ -594,6 +600,12 @@ struct esdc_regs { #define WEIM_ESDCFG1 0xB800100C #define WEIM_ESDMISC 0xB8001010 +#define UART1_BASE 0x43F90000 +#define UART2_BASE 0x43F94000 +#define UART3_BASE 0x5000C000 +#define UART4_BASE 0x43FB0000 +#define UART5_BASE 0x43FB4000 + #define ESDCTL_SDE (1 << 31) #define ESDCTL_CMD_RW (0 << 28) #define ESDCTL_CMD_PRECHARGE (1 << 28) @@ -636,7 +648,6 @@ struct esdc_regs { #define WEIM_BASE 0xb8002000 #define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_GPR (IOMUXC_BASE + 0x8) #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index 25c324eb36..df74508a93 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -42,8 +42,8 @@ #define I2C_BASE_ADDR 0x43F80000 #define I2C3_BASE_ADDR 0x43F84000 #define ATA_BASE_ADDR 0x43F8C000 -#define UART1_BASE_ADDR 0x43F90000 -#define UART2_BASE_ADDR 0x43F94000 +#define UART1_BASE 0x43F90000 +#define UART2_BASE 0x43F94000 #define I2C2_BASE_ADDR 0x43F98000 #define CSPI1_BASE_ADDR 0x43FA4000 #define IOMUXC_BASE_ADDR 0x43FAC000 @@ -52,7 +52,7 @@ * SPBA */ #define SPBA_BASE_ADDR 0x50000000 -#define UART3_BASE_ADDR 0x5000C000 +#define UART3_BASE 0x5000C000 #define CSPI2_BASE_ADDR 0x50010000 #define ATA_DMA_BASE_ADDR 0x50020000 #define FEC_BASE_ADDR 0x50038000 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index d069209b58..0ee88d25b7 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -54,7 +54,7 @@ */ #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) -#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) @@ -83,8 +83,8 @@ #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) -#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) -#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h index 81942a8063..bbaf1bc97b 100644 --- a/arch/arm/include/asm/arch-omap3/am35x_def.h +++ b/arch/arm/include/asm/arch-omap3/am35x_def.h @@ -32,6 +32,9 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ +/* IP_SW_RESET bits */ +#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ + /* General register mappings of system control module */ #define AM35X_SCM_GEN_BASE 0x48002270 struct am35x_scm_general { diff --git a/arch/arm/include/asm/arch-omap3/emac_defs.h b/arch/arm/include/asm/arch-omap3/emac_defs.h new file mode 100644 index 0000000000..8506c555d5 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/emac_defs.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. + * + */ + +#ifndef _AM3517_EMAC_H_ +#define _AM3517_EMAC_H_ + +#define EMAC_BASE_ADDR 0x5C010000 +#define EMAC_WRAPPER_BASE_ADDR 0x5C000000 +#define EMAC_WRAPPER_RAM_ADDR 0x5C020000 +#define EMAC_MDIO_BASE_ADDR 0x5C030000 +#define EMAC_HW_RAM_ADDR 0x01E20000 + +#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */ +#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */ + +/* SOFTRESET macro definition interferes with emac_regs structure definition */ +#undef SOFTRESET + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#define DAVINCI_EMAC_VERSION2 + +#endif /* _AM3517_EMAC_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index db6a696f49..5fd02d4dfc 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -39,10 +39,26 @@ enum { #define EARLY_INIT 1 +/* + * For a full explanation of these registers and values please see + * the Technical Reference Manual (TRM) for any of the processors in + * this family. + */ + /* Slower full frequency range default timings for x32 operation*/ #define SDRC_SHARING 0x00000100 #define SDRC_MR_0_SDR 0x00000031 +/* + * SDRC autorefresh control values. This register consists of autorefresh + * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The + * counter is a result of ( tREFI / tCK ) - 50. + */ +#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ + #define DLL_OFFSET 0 #define DLL_WRITEDDRCLKX2DIS 1 #define DLL_ENADLL 1 @@ -86,6 +102,53 @@ enum { ACTIM_CTRLB_TXP(b) | \ ACTIM_CTRLB_TXSR(d) +/* + * Values used in the MCFG register. Only values we use today + * are defined and the rest can be found in the TRM. Unless otherwise + * noted all fields are one bit. + */ +#define V_MCFG_RAMTYPE_DDR (0x1) +#define V_MCFG_DEEPPD_EN (0x1 << 3) +#define V_MCFG_B32NOT16_32 (0x1 << 4) +#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ +#define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */ +#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) +#define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */ +#define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */ + +/* Macro to construct MCFG */ +#define MCFG(a, b) \ + V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \ + V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \ + V_MCFG_BANKALLOCATION_RBC | \ + V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR + +/* Hynix part of AM/DM37xEVM (200MHz optimized) */ +#define HYNIX_TDAL_200 6 +#define HYNIX_TDPL_200 3 +#define HYNIX_TRRD_200 2 +#define HYNIX_TRCD_200 4 +#define HYNIX_TRP_200 3 +#define HYNIX_TRAS_200 8 +#define HYNIX_TRC_200 11 +#define HYNIX_TRFC_200 18 +#define HYNIX_V_ACTIMA_200 \ + ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ + HYNIX_TRAS_200, HYNIX_TRP_200, \ + HYNIX_TRCD_200, HYNIX_TRRD_200, \ + HYNIX_TDPL_200, HYNIX_TDAL_200) + +#define HYNIX_TWTR_200 2 +#define HYNIX_TCKE_200 1 +#define HYNIX_TXP_200 1 +#define HYNIX_XSR_200 28 +#define HYNIX_V_ACTIMB_200 \ + ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ + HYNIX_TXP_200, HYNIX_XSR_200) + +#define HYNIX_RASWIDTH_200 0x3 +#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) + /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ @@ -138,32 +201,42 @@ enum { ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ MICRON_TXP_165, MICRON_XSR_165) -#define MICRON_RAMTYPE 0x1 -#define MICRON_DDRTYPE 0x0 -#define MICRON_DEEPPD 0x1 -#define MICRON_B32NOT16 0x1 -#define MICRON_BANKALLOCATION 0x2 -#define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) -#define MICRON_ADDRMUXLEGACY 0x1 -#define MICRON_CASWIDTH 0x5 -#define MICRON_RASWIDTH 0x2 -#define MICRON_LOCKSTATUS 0x0 -#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \ - (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \ - (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \ - (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ - (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE)) - -#define MICRON_ARCV 2030 -#define MICRON_ARE 0x1 -#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) - -#define MICRON_BL 0x2 -#define MICRON_SIL 0x0 -#define MICRON_CASL 0x3 -#define MICRON_WBST 0x0 -#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ - (MICRON_SIL << 3) | (MICRON_BL)) +#define MICRON_RASWIDTH_165 0x2 +#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) + +#define MICRON_BL_165 0x2 +#define MICRON_SIL_165 0x0 +#define MICRON_CASL_165 0x3 +#define MICRON_WBST_165 0x0 +#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ + (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ + (MICRON_BL_165)) + +/* Micron part (200MHz optimized) 5 ns */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 \ + ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ + MICRON_TRAS_200, MICRON_TRP_200, \ + MICRON_TRCD_200, MICRON_TRRD_200, \ + MICRON_TDPL_200, MICRON_TDAL_200) + +#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 4 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 \ + ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ + MICRON_TXP_200, MICRON_XSR_200) + +#define MICRON_RASWIDTH_200 0x3 +#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ @@ -191,31 +264,8 @@ enum { ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ NUMONYX_TXP_165, NUMONYX_XSR_165) -#ifdef CONFIG_OMAP3_INFINEON_DDR -#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 -#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 -#endif - -#ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG -#define V_RFR_CTRL MICRON_V_RFR_CTRL -#define V_MR MICRON_V_MR -#endif - -#ifdef CONFIG_OMAP3_NUMONYX_DDR -#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 -#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 -#endif - -#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) -#error "Please choose the right DDR type in config header" -#endif - -#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) -#error "Please choose the right DDR type in config header" -#endif +#define NUMONYX_RASWIDTH_165 0x4 +#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) /* * GPMC settings - @@ -259,6 +309,10 @@ enum { #define GPMC_SIZE_32M 0xE #define GPMC_SIZE_16M 0xF +#define GPMC_BASEADDR_MASK 0x3F + +#define GPMC_CS_ENABLE 0x1 + #define SMNAND_GPMC_CONFIG1 0x00000800 #define SMNAND_GPMC_CONFIG2 0x00141400 #define SMNAND_GPMC_CONFIG3 0x00141400 diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h index ba1c2ffc06..296367948f 100644 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -55,7 +55,7 @@ typedef struct t2 { #define OMAP_HSMMC2_BASE 0x480B4000 #define OMAP_HSMMC3_BASE 0x480AD000 -typedef struct hsmmc { +struct hsmmc { unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned int sysstatus; /* 0x14 */ @@ -77,7 +77,7 @@ typedef struct hsmmc { unsigned int ie; /* 0x134 */ unsigned char res4[0x8]; unsigned int capa; /* 0x140 */ -} hsmmc_t; +}; /* * OMAP HS MMC Bit definitions @@ -182,13 +182,6 @@ typedef struct hsmmc { #define CLK_400KHZ 1 #define CLK_MISC 2 -typedef struct { - unsigned int card_type; - unsigned int version; - unsigned int mode; - unsigned int size; - unsigned int RCA; -} mmc_card_data; #define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 0c01c73165..6daef49e97 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -404,6 +404,47 @@ #define CONTROL_PADCONF_SDRC_CKE0 0x0262 #define CONTROL_PADCONF_SDRC_CKE1 0x0264 +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 + +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 + #define MUX_VAL(OFFSET,VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 02eb865dc1..2b5e9aeae1 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -153,6 +153,7 @@ struct gpio { #define SRAM_OFFSET2 0x0000F800 #define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ SRAM_OFFSET2) +#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) #define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */ #define OMAP3_PUBLIC_SRAM_END 0x40210000 diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 995e7cb57e..e5031d5022 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -38,6 +38,9 @@ void per_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr); +void identify_nand_chip(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, @@ -49,7 +52,6 @@ void set_muxconf_regs(void); u32 get_cpu_family(void); u32 get_cpu_rev(void); u32 get_sku_id(void); -u32 get_mem_type(void); u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 45c947d648..c2a9b46cfd 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -687,4 +687,27 @@ struct dpll_params { s8 m7; }; +extern struct omap4_prcm_regs *const prcm; +extern const u32 sys_clk_array[8]; + +void scale_vcores(void); +void do_scale_tps62361(u32 reg, u32 volt_mv); +u32 omap_ddr_clk(void); +void do_scale_vcore(u32 vcore_reg, u32 volt_mv); +void setup_sri2c(void); +void setup_post_dividers(u32 *const base, const struct dpll_params *params); +u32 get_sys_clk_index(void); +void enable_basic_clocks(void); +void enable_basic_uboot_clocks(void); +void enable_non_essential_clocks(void); +void do_enable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_hw_auto, + u32 *const *clk_modules_explicit_en, + u8 wait_for_enable); +const struct dpll_params *get_mpu_dpll_params(void); +const struct dpll_params *get_core_dpll_params(void); +const struct dpll_params *get_per_dpll_params(void); +const struct dpll_params *get_iva_dpll_params(void); +const struct dpll_params *get_usb_dpll_params(void); +const struct dpll_params *get_abe_dpll_params(void); #endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h deleted file mode 100644 index 3a549bad5e..0000000000 --- a/arch/arm/include/asm/arch-omap4/emif.h +++ /dev/null @@ -1,1021 +0,0 @@ -/* - * OMAP44xx EMIF header - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Aneesh V <aneesh@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _EMIF_H_ -#define _EMIF_H_ -#include <asm/types.h> -#include <common.h> - -/* Base address */ -#define OMAP44XX_EMIF1 0x4c000000 -#define OMAP44XX_EMIF2 0x4d000000 - -/* Registers shifts and masks */ - -/* EMIF_MOD_ID_REV */ -#define OMAP44XX_REG_SCHEME_SHIFT 30 -#define OMAP44XX_REG_SCHEME_MASK (0x3 << 30) -#define OMAP44XX_REG_MODULE_ID_SHIFT 16 -#define OMAP44XX_REG_MODULE_ID_MASK (0xfff << 16) -#define OMAP44XX_REG_RTL_VERSION_SHIFT 11 -#define OMAP44XX_REG_RTL_VERSION_MASK (0x1f << 11) -#define OMAP44XX_REG_MAJOR_REVISION_SHIFT 8 -#define OMAP44XX_REG_MAJOR_REVISION_MASK (0x7 << 8) -#define OMAP44XX_REG_MINOR_REVISION_SHIFT 0 -#define OMAP44XX_REG_MINOR_REVISION_MASK (0x3f << 0) - -/* STATUS */ -#define OMAP44XX_REG_BE_SHIFT 31 -#define OMAP44XX_REG_BE_MASK (1 << 31) -#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT 30 -#define OMAP44XX_REG_DUAL_CLK_MODE_MASK (1 << 30) -#define OMAP44XX_REG_FAST_INIT_SHIFT 29 -#define OMAP44XX_REG_FAST_INIT_MASK (1 << 29) -#define OMAP44XX_REG_PHY_DLL_READY_SHIFT 2 -#define OMAP44XX_REG_PHY_DLL_READY_MASK (1 << 2) - -/* SDRAM_CONFIG */ -#define OMAP44XX_REG_SDRAM_TYPE_SHIFT 29 -#define OMAP44XX_REG_SDRAM_TYPE_MASK (0x7 << 29) -#define OMAP44XX_REG_IBANK_POS_SHIFT 27 -#define OMAP44XX_REG_IBANK_POS_MASK (0x3 << 27) -#define OMAP44XX_REG_DDR_TERM_SHIFT 24 -#define OMAP44XX_REG_DDR_TERM_MASK (0x7 << 24) -#define OMAP44XX_REG_DDR2_DDQS_SHIFT 23 -#define OMAP44XX_REG_DDR2_DDQS_MASK (1 << 23) -#define OMAP44XX_REG_DYN_ODT_SHIFT 21 -#define OMAP44XX_REG_DYN_ODT_MASK (0x3 << 21) -#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT 20 -#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK (1 << 20) -#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT 18 -#define OMAP44XX_REG_SDRAM_DRIVE_MASK (0x3 << 18) -#define OMAP44XX_REG_CWL_SHIFT 16 -#define OMAP44XX_REG_CWL_MASK (0x3 << 16) -#define OMAP44XX_REG_NARROW_MODE_SHIFT 14 -#define OMAP44XX_REG_NARROW_MODE_MASK (0x3 << 14) -#define OMAP44XX_REG_CL_SHIFT 10 -#define OMAP44XX_REG_CL_MASK (0xf << 10) -#define OMAP44XX_REG_ROWSIZE_SHIFT 7 -#define OMAP44XX_REG_ROWSIZE_MASK (0x7 << 7) -#define OMAP44XX_REG_IBANK_SHIFT 4 -#define OMAP44XX_REG_IBANK_MASK (0x7 << 4) -#define OMAP44XX_REG_EBANK_SHIFT 3 -#define OMAP44XX_REG_EBANK_MASK (1 << 3) -#define OMAP44XX_REG_PAGESIZE_SHIFT 0 -#define OMAP44XX_REG_PAGESIZE_MASK (0x7 << 0) - -/* SDRAM_CONFIG_2 */ -#define OMAP44XX_REG_CS1NVMEN_SHIFT 30 -#define OMAP44XX_REG_CS1NVMEN_MASK (1 << 30) -#define OMAP44XX_REG_EBANK_POS_SHIFT 27 -#define OMAP44XX_REG_EBANK_POS_MASK (1 << 27) -#define OMAP44XX_REG_RDBNUM_SHIFT 4 -#define OMAP44XX_REG_RDBNUM_MASK (0x3 << 4) -#define OMAP44XX_REG_RDBSIZE_SHIFT 0 -#define OMAP44XX_REG_RDBSIZE_MASK (0x7 << 0) - -/* SDRAM_REF_CTRL */ -#define OMAP44XX_REG_INITREF_DIS_SHIFT 31 -#define OMAP44XX_REG_INITREF_DIS_MASK (1 << 31) -#define OMAP44XX_REG_SRT_SHIFT 29 -#define OMAP44XX_REG_SRT_MASK (1 << 29) -#define OMAP44XX_REG_ASR_SHIFT 28 -#define OMAP44XX_REG_ASR_MASK (1 << 28) -#define OMAP44XX_REG_PASR_SHIFT 24 -#define OMAP44XX_REG_PASR_MASK (0x7 << 24) -#define OMAP44XX_REG_REFRESH_RATE_SHIFT 0 -#define OMAP44XX_REG_REFRESH_RATE_MASK (0xffff << 0) - -/* SDRAM_REF_CTRL_SHDW */ -#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT 0 -#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) - -/* SDRAM_TIM_1 */ -#define OMAP44XX_REG_T_RP_SHIFT 25 -#define OMAP44XX_REG_T_RP_MASK (0xf << 25) -#define OMAP44XX_REG_T_RCD_SHIFT 21 -#define OMAP44XX_REG_T_RCD_MASK (0xf << 21) -#define OMAP44XX_REG_T_WR_SHIFT 17 -#define OMAP44XX_REG_T_WR_MASK (0xf << 17) -#define OMAP44XX_REG_T_RAS_SHIFT 12 -#define OMAP44XX_REG_T_RAS_MASK (0x1f << 12) -#define OMAP44XX_REG_T_RC_SHIFT 6 -#define OMAP44XX_REG_T_RC_MASK (0x3f << 6) -#define OMAP44XX_REG_T_RRD_SHIFT 3 -#define OMAP44XX_REG_T_RRD_MASK (0x7 << 3) -#define OMAP44XX_REG_T_WTR_SHIFT 0 -#define OMAP44XX_REG_T_WTR_MASK (0x7 << 0) - -/* SDRAM_TIM_1_SHDW */ -#define OMAP44XX_REG_T_RP_SHDW_SHIFT 25 -#define OMAP44XX_REG_T_RP_SHDW_MASK (0xf << 25) -#define OMAP44XX_REG_T_RCD_SHDW_SHIFT 21 -#define OMAP44XX_REG_T_RCD_SHDW_MASK (0xf << 21) -#define OMAP44XX_REG_T_WR_SHDW_SHIFT 17 -#define OMAP44XX_REG_T_WR_SHDW_MASK (0xf << 17) -#define OMAP44XX_REG_T_RAS_SHDW_SHIFT 12 -#define OMAP44XX_REG_T_RAS_SHDW_MASK (0x1f << 12) -#define OMAP44XX_REG_T_RC_SHDW_SHIFT 6 -#define OMAP44XX_REG_T_RC_SHDW_MASK (0x3f << 6) -#define OMAP44XX_REG_T_RRD_SHDW_SHIFT 3 -#define OMAP44XX_REG_T_RRD_SHDW_MASK (0x7 << 3) -#define OMAP44XX_REG_T_WTR_SHDW_SHIFT 0 -#define OMAP44XX_REG_T_WTR_SHDW_MASK (0x7 << 0) - -/* SDRAM_TIM_2 */ -#define OMAP44XX_REG_T_XP_SHIFT 28 -#define OMAP44XX_REG_T_XP_MASK (0x7 << 28) -#define OMAP44XX_REG_T_ODT_SHIFT 25 -#define OMAP44XX_REG_T_ODT_MASK (0x7 << 25) -#define OMAP44XX_REG_T_XSNR_SHIFT 16 -#define OMAP44XX_REG_T_XSNR_MASK (0x1ff << 16) -#define OMAP44XX_REG_T_XSRD_SHIFT 6 -#define OMAP44XX_REG_T_XSRD_MASK (0x3ff << 6) -#define OMAP44XX_REG_T_RTP_SHIFT 3 -#define OMAP44XX_REG_T_RTP_MASK (0x7 << 3) -#define OMAP44XX_REG_T_CKE_SHIFT 0 -#define OMAP44XX_REG_T_CKE_MASK (0x7 << 0) - -/* SDRAM_TIM_2_SHDW */ -#define OMAP44XX_REG_T_XP_SHDW_SHIFT 28 -#define OMAP44XX_REG_T_XP_SHDW_MASK (0x7 << 28) -#define OMAP44XX_REG_T_ODT_SHDW_SHIFT 25 -#define OMAP44XX_REG_T_ODT_SHDW_MASK (0x7 << 25) -#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT 16 -#define OMAP44XX_REG_T_XSNR_SHDW_MASK (0x1ff << 16) -#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT 6 -#define OMAP44XX_REG_T_XSRD_SHDW_MASK (0x3ff << 6) -#define OMAP44XX_REG_T_RTP_SHDW_SHIFT 3 -#define OMAP44XX_REG_T_RTP_SHDW_MASK (0x7 << 3) -#define OMAP44XX_REG_T_CKE_SHDW_SHIFT 0 -#define OMAP44XX_REG_T_CKE_SHDW_MASK (0x7 << 0) - -/* SDRAM_TIM_3 */ -#define OMAP44XX_REG_T_CKESR_SHIFT 21 -#define OMAP44XX_REG_T_CKESR_MASK (0x7 << 21) -#define OMAP44XX_REG_ZQ_ZQCS_SHIFT 15 -#define OMAP44XX_REG_ZQ_ZQCS_MASK (0x3f << 15) -#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT 13 -#define OMAP44XX_REG_T_TDQSCKMAX_MASK (0x3 << 13) -#define OMAP44XX_REG_T_RFC_SHIFT 4 -#define OMAP44XX_REG_T_RFC_MASK (0x1ff << 4) -#define OMAP44XX_REG_T_RAS_MAX_SHIFT 0 -#define OMAP44XX_REG_T_RAS_MAX_MASK (0xf << 0) - -/* SDRAM_TIM_3_SHDW */ -#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT 21 -#define OMAP44XX_REG_T_CKESR_SHDW_MASK (0x7 << 21) -#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT 15 -#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) -#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT 13 -#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) -#define OMAP44XX_REG_T_RFC_SHDW_SHIFT 4 -#define OMAP44XX_REG_T_RFC_SHDW_MASK (0x1ff << 4) -#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT 0 -#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) - -/* LPDDR2_NVM_TIM */ -#define OMAP44XX_REG_NVM_T_XP_SHIFT 28 -#define OMAP44XX_REG_NVM_T_XP_MASK (0x7 << 28) -#define OMAP44XX_REG_NVM_T_WTR_SHIFT 24 -#define OMAP44XX_REG_NVM_T_WTR_MASK (0x7 << 24) -#define OMAP44XX_REG_NVM_T_RP_SHIFT 20 -#define OMAP44XX_REG_NVM_T_RP_MASK (0xf << 20) -#define OMAP44XX_REG_NVM_T_WRA_SHIFT 16 -#define OMAP44XX_REG_NVM_T_WRA_MASK (0xf << 16) -#define OMAP44XX_REG_NVM_T_RRD_SHIFT 8 -#define OMAP44XX_REG_NVM_T_RRD_MASK (0xff << 8) -#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT 0 -#define OMAP44XX_REG_NVM_T_RCDMIN_MASK (0xff << 0) - -/* LPDDR2_NVM_TIM_SHDW */ -#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT 28 -#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) -#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT 24 -#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) -#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT 20 -#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK (0xf << 20) -#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT 16 -#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) -#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT 8 -#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) -#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 -#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) - -/* PWR_MGMT_CTRL */ -#define OMAP44XX_REG_IDLEMODE_SHIFT 30 -#define OMAP44XX_REG_IDLEMODE_MASK (0x3 << 30) -#define OMAP44XX_REG_PD_TIM_SHIFT 12 -#define OMAP44XX_REG_PD_TIM_MASK (0xf << 12) -#define OMAP44XX_REG_DPD_EN_SHIFT 11 -#define OMAP44XX_REG_DPD_EN_MASK (1 << 11) -#define OMAP44XX_REG_LP_MODE_SHIFT 8 -#define OMAP44XX_REG_LP_MODE_MASK (0x7 << 8) -#define OMAP44XX_REG_SR_TIM_SHIFT 4 -#define OMAP44XX_REG_SR_TIM_MASK (0xf << 4) -#define OMAP44XX_REG_CS_TIM_SHIFT 0 -#define OMAP44XX_REG_CS_TIM_MASK (0xf << 0) - -/* PWR_MGMT_CTRL_SHDW */ -#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT 8 -#define OMAP44XX_REG_PD_TIM_SHDW_MASK (0xf << 8) -#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT 4 -#define OMAP44XX_REG_SR_TIM_SHDW_MASK (0xf << 4) -#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT 0 -#define OMAP44XX_REG_CS_TIM_SHDW_MASK (0xf << 0) - -/* LPDDR2_MODE_REG_DATA */ -#define OMAP44XX_REG_VALUE_0_SHIFT 0 -#define OMAP44XX_REG_VALUE_0_MASK (0x7f << 0) - -/* LPDDR2_MODE_REG_CFG */ -#define OMAP44XX_REG_CS_SHIFT 31 -#define OMAP44XX_REG_CS_MASK (1 << 31) -#define OMAP44XX_REG_REFRESH_EN_SHIFT 30 -#define OMAP44XX_REG_REFRESH_EN_MASK (1 << 30) -#define OMAP44XX_REG_ADDRESS_SHIFT 0 -#define OMAP44XX_REG_ADDRESS_MASK (0xff << 0) - -/* OCP_CONFIG */ -#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT 24 -#define OMAP44XX_REG_SYS_THRESH_MAX_MASK (0xf << 24) -#define OMAP44XX_REG_MPU_THRESH_MAX_SHIFT 20 -#define OMAP44XX_REG_MPU_THRESH_MAX_MASK (0xf << 20) -#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT 16 -#define OMAP44XX_REG_LL_THRESH_MAX_MASK (0xf << 16) -#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT 0 -#define OMAP44XX_REG_PR_OLD_COUNT_MASK (0xff << 0) - -/* OCP_CFG_VAL_1 */ -#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT 30 -#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) -#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT 28 -#define OMAP44XX_REG_LL_BUS_WIDTH_MASK (0x3 << 28) -#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT 8 -#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK (0xff << 8) -#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT 0 -#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) - -/* OCP_CFG_VAL_2 */ -#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT 16 -#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) -#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT 8 -#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) -#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT 0 -#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) - -/* IODFT_TLGC */ -#define OMAP44XX_REG_TLEC_SHIFT 16 -#define OMAP44XX_REG_TLEC_MASK (0xffff << 16) -#define OMAP44XX_REG_MT_SHIFT 14 -#define OMAP44XX_REG_MT_MASK (1 << 14) -#define OMAP44XX_REG_ACT_CAP_EN_SHIFT 13 -#define OMAP44XX_REG_ACT_CAP_EN_MASK (1 << 13) -#define OMAP44XX_REG_OPG_LD_SHIFT 12 -#define OMAP44XX_REG_OPG_LD_MASK (1 << 12) -#define OMAP44XX_REG_RESET_PHY_SHIFT 10 -#define OMAP44XX_REG_RESET_PHY_MASK (1 << 10) -#define OMAP44XX_REG_MMS_SHIFT 8 -#define OMAP44XX_REG_MMS_MASK (1 << 8) -#define OMAP44XX_REG_MC_SHIFT 4 -#define OMAP44XX_REG_MC_MASK (0x3 << 4) -#define OMAP44XX_REG_PC_SHIFT 1 -#define OMAP44XX_REG_PC_MASK (0x7 << 1) -#define OMAP44XX_REG_TM_SHIFT 0 -#define OMAP44XX_REG_TM_MASK (1 << 0) - -/* IODFT_CTRL_MISR_RSLT */ -#define OMAP44XX_REG_DQM_TLMR_SHIFT 16 -#define OMAP44XX_REG_DQM_TLMR_MASK (0x3ff << 16) -#define OMAP44XX_REG_CTL_TLMR_SHIFT 0 -#define OMAP44XX_REG_CTL_TLMR_MASK (0x7ff << 0) - -/* IODFT_ADDR_MISR_RSLT */ -#define OMAP44XX_REG_ADDR_TLMR_SHIFT 0 -#define OMAP44XX_REG_ADDR_TLMR_MASK (0x1fffff << 0) - -/* IODFT_DATA_MISR_RSLT_1 */ -#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT 0 -#define OMAP44XX_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) - -/* IODFT_DATA_MISR_RSLT_2 */ -#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT 0 -#define OMAP44XX_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) - -/* IODFT_DATA_MISR_RSLT_3 */ -#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT 0 -#define OMAP44XX_REG_DATA_TLMR_66_64_MASK (0x7 << 0) - -/* PERF_CNT_1 */ -#define OMAP44XX_REG_COUNTER1_SHIFT 0 -#define OMAP44XX_REG_COUNTER1_MASK (0xffffffff << 0) - -/* PERF_CNT_2 */ -#define OMAP44XX_REG_COUNTER2_SHIFT 0 -#define OMAP44XX_REG_COUNTER2_MASK (0xffffffff << 0) - -/* PERF_CNT_CFG */ -#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT 31 -#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK (1 << 31) -#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT 30 -#define OMAP44XX_REG_CNTR2_REGION_EN_MASK (1 << 30) -#define OMAP44XX_REG_CNTR2_CFG_SHIFT 16 -#define OMAP44XX_REG_CNTR2_CFG_MASK (0xf << 16) -#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT 15 -#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK (1 << 15) -#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT 14 -#define OMAP44XX_REG_CNTR1_REGION_EN_MASK (1 << 14) -#define OMAP44XX_REG_CNTR1_CFG_SHIFT 0 -#define OMAP44XX_REG_CNTR1_CFG_MASK (0xf << 0) - -/* PERF_CNT_SEL */ -#define OMAP44XX_REG_MCONNID2_SHIFT 24 -#define OMAP44XX_REG_MCONNID2_MASK (0xff << 24) -#define OMAP44XX_REG_REGION_SEL2_SHIFT 16 -#define OMAP44XX_REG_REGION_SEL2_MASK (0x3 << 16) -#define OMAP44XX_REG_MCONNID1_SHIFT 8 -#define OMAP44XX_REG_MCONNID1_MASK (0xff << 8) -#define OMAP44XX_REG_REGION_SEL1_SHIFT 0 -#define OMAP44XX_REG_REGION_SEL1_MASK (0x3 << 0) - -/* PERF_CNT_TIM */ -#define OMAP44XX_REG_TOTAL_TIME_SHIFT 0 -#define OMAP44XX_REG_TOTAL_TIME_MASK (0xffffffff << 0) - -/* READ_IDLE_CTRL */ -#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT 16 -#define OMAP44XX_REG_READ_IDLE_LEN_MASK (0xf << 16) -#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT 0 -#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) - -/* READ_IDLE_CTRL_SHDW */ -#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT 16 -#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) -#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 -#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) - -/* IRQ_EOI */ -#define OMAP44XX_REG_EOI_SHIFT 0 -#define OMAP44XX_REG_EOI_MASK (1 << 0) - -/* IRQSTATUS_RAW_SYS */ -#define OMAP44XX_REG_DNV_SYS_SHIFT 2 -#define OMAP44XX_REG_DNV_SYS_MASK (1 << 2) -#define OMAP44XX_REG_TA_SYS_SHIFT 1 -#define OMAP44XX_REG_TA_SYS_MASK (1 << 1) -#define OMAP44XX_REG_ERR_SYS_SHIFT 0 -#define OMAP44XX_REG_ERR_SYS_MASK (1 << 0) - -/* IRQSTATUS_RAW_LL */ -#define OMAP44XX_REG_DNV_LL_SHIFT 2 -#define OMAP44XX_REG_DNV_LL_MASK (1 << 2) -#define OMAP44XX_REG_TA_LL_SHIFT 1 -#define OMAP44XX_REG_TA_LL_MASK (1 << 1) -#define OMAP44XX_REG_ERR_LL_SHIFT 0 -#define OMAP44XX_REG_ERR_LL_MASK (1 << 0) - -/* IRQSTATUS_SYS */ - -/* IRQSTATUS_LL */ - -/* IRQENABLE_SET_SYS */ -#define OMAP44XX_REG_EN_DNV_SYS_SHIFT 2 -#define OMAP44XX_REG_EN_DNV_SYS_MASK (1 << 2) -#define OMAP44XX_REG_EN_TA_SYS_SHIFT 1 -#define OMAP44XX_REG_EN_TA_SYS_MASK (1 << 1) -#define OMAP44XX_REG_EN_ERR_SYS_SHIFT 0 -#define OMAP44XX_REG_EN_ERR_SYS_MASK (1 << 0) - -/* IRQENABLE_SET_LL */ -#define OMAP44XX_REG_EN_DNV_LL_SHIFT 2 -#define OMAP44XX_REG_EN_DNV_LL_MASK (1 << 2) -#define OMAP44XX_REG_EN_TA_LL_SHIFT 1 -#define OMAP44XX_REG_EN_TA_LL_MASK (1 << 1) -#define OMAP44XX_REG_EN_ERR_LL_SHIFT 0 -#define OMAP44XX_REG_EN_ERR_LL_MASK (1 << 0) - -/* IRQENABLE_CLR_SYS */ - -/* IRQENABLE_CLR_LL */ - -/* ZQ_CONFIG */ -#define OMAP44XX_REG_ZQ_CS1EN_SHIFT 31 -#define OMAP44XX_REG_ZQ_CS1EN_MASK (1 << 31) -#define OMAP44XX_REG_ZQ_CS0EN_SHIFT 30 -#define OMAP44XX_REG_ZQ_CS0EN_MASK (1 << 30) -#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT 29 -#define OMAP44XX_REG_ZQ_DUALCALEN_MASK (1 << 29) -#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT 28 -#define OMAP44XX_REG_ZQ_SFEXITEN_MASK (1 << 28) -#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT 18 -#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) -#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT 16 -#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) -#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT 0 -#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) - -/* TEMP_ALERT_CONFIG */ -#define OMAP44XX_REG_TA_CS1EN_SHIFT 31 -#define OMAP44XX_REG_TA_CS1EN_MASK (1 << 31) -#define OMAP44XX_REG_TA_CS0EN_SHIFT 30 -#define OMAP44XX_REG_TA_CS0EN_MASK (1 << 30) -#define OMAP44XX_REG_TA_SFEXITEN_SHIFT 28 -#define OMAP44XX_REG_TA_SFEXITEN_MASK (1 << 28) -#define OMAP44XX_REG_TA_DEVWDT_SHIFT 26 -#define OMAP44XX_REG_TA_DEVWDT_MASK (0x3 << 26) -#define OMAP44XX_REG_TA_DEVCNT_SHIFT 24 -#define OMAP44XX_REG_TA_DEVCNT_MASK (0x3 << 24) -#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT 0 -#define OMAP44XX_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) - -/* OCP_ERR_LOG */ -#define OMAP44XX_REG_MADDRSPACE_SHIFT 14 -#define OMAP44XX_REG_MADDRSPACE_MASK (0x3 << 14) -#define OMAP44XX_REG_MBURSTSEQ_SHIFT 11 -#define OMAP44XX_REG_MBURSTSEQ_MASK (0x7 << 11) -#define OMAP44XX_REG_MCMD_SHIFT 8 -#define OMAP44XX_REG_MCMD_MASK (0x7 << 8) -#define OMAP44XX_REG_MCONNID_SHIFT 0 -#define OMAP44XX_REG_MCONNID_MASK (0xff << 0) - -/* DDR_PHY_CTRL_1 */ -#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT 4 -#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) -#define OMAP44XX_REG_READ_LATENCY_SHIFT 0 -#define OMAP44XX_REG_READ_LATENCY_MASK (0xf << 0) -#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 -#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) -#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 -#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) - -/* DDR_PHY_CTRL_1_SHDW */ -#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 -#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) -#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT 0 -#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK (0xf << 0) -#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 -#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) -#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 -#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) - -/* DDR_PHY_CTRL_2 */ -#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT 0 -#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) - -/* DMM */ -#define OMAP44XX_DMM_LISA_MAP_BASE 0x4E000040 - -/* Memory Adapter (4460 onwards) */ -#define OMAP44XX_MA_LISA_MAP_BASE 0x482AF040 - -/* DMM_LISA_MAP */ -#define OMAP44XX_SYS_ADDR_SHIFT 24 -#define OMAP44XX_SYS_ADDR_MASK (0xff << 24) -#define OMAP44XX_SYS_SIZE_SHIFT 20 -#define OMAP44XX_SYS_SIZE_MASK (0x7 << 20) -#define OMAP44XX_SDRC_INTL_SHIFT 18 -#define OMAP44XX_SDRC_INTL_MASK (0x3 << 18) -#define OMAP44XX_SDRC_ADDRSPC_SHIFT 16 -#define OMAP44XX_SDRC_ADDRSPC_MASK (0x3 << 16) -#define OMAP44XX_SDRC_MAP_SHIFT 8 -#define OMAP44XX_SDRC_MAP_MASK (0x3 << 8) -#define OMAP44XX_SDRC_ADDR_SHIFT 0 -#define OMAP44XX_SDRC_ADDR_MASK (0xff << 0) - -/* DMM_LISA_MAP fields */ -#define DMM_SDRC_MAP_UNMAPPED 0 -#define DMM_SDRC_MAP_EMIF1_ONLY 1 -#define DMM_SDRC_MAP_EMIF2_ONLY 2 -#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 - -#define DMM_SDRC_INTL_NONE 0 -#define DMM_SDRC_INTL_128B 1 -#define DMM_SDRC_INTL_256B 2 -#define DMM_SDRC_INTL_512 3 - -#define DMM_SDRC_ADDR_SPC_SDRAM 0 -#define DMM_SDRC_ADDR_SPC_NVM 1 -#define DMM_SDRC_ADDR_SPC_INVALID 2 - -#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ - (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\ - (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\ - (DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\ - (CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT)) - -#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ - (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) - -#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ - (DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) - -/* Trap for invalid TILER PAT entries */ -#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ - (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\ - (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\ - (0xFF << OMAP44XX_SYS_ADDR_SHIFT)) - - -/* Reg mapping structure */ -struct emif_reg_struct { - u32 emif_mod_id_rev; - u32 emif_status; - u32 emif_sdram_config; - u32 emif_lpddr2_nvm_config; - u32 emif_sdram_ref_ctrl; - u32 emif_sdram_ref_ctrl_shdw; - u32 emif_sdram_tim_1; - u32 emif_sdram_tim_1_shdw; - u32 emif_sdram_tim_2; - u32 emif_sdram_tim_2_shdw; - u32 emif_sdram_tim_3; - u32 emif_sdram_tim_3_shdw; - u32 emif_lpddr2_nvm_tim; - u32 emif_lpddr2_nvm_tim_shdw; - u32 emif_pwr_mgmt_ctrl; - u32 emif_pwr_mgmt_ctrl_shdw; - u32 emif_lpddr2_mode_reg_data; - u32 padding1[1]; - u32 emif_lpddr2_mode_reg_data_es2; - u32 padding11[1]; - u32 emif_lpddr2_mode_reg_cfg; - u32 emif_l3_config; - u32 emif_l3_cfg_val_1; - u32 emif_l3_cfg_val_2; - u32 emif_iodft_tlgc; - u32 padding2[7]; - u32 emif_perf_cnt_1; - u32 emif_perf_cnt_2; - u32 emif_perf_cnt_cfg; - u32 emif_perf_cnt_sel; - u32 emif_perf_cnt_tim; - u32 padding3; - u32 emif_read_idlectrl; - u32 emif_read_idlectrl_shdw; - u32 padding4; - u32 emif_irqstatus_raw_sys; - u32 emif_irqstatus_raw_ll; - u32 emif_irqstatus_sys; - u32 emif_irqstatus_ll; - u32 emif_irqenable_set_sys; - u32 emif_irqenable_set_ll; - u32 emif_irqenable_clr_sys; - u32 emif_irqenable_clr_ll; - u32 padding5; - u32 emif_zq_config; - u32 emif_temp_alert_config; - u32 emif_l3_err_log; - u32 padding6[4]; - u32 emif_ddr_phy_ctrl_1; - u32 emif_ddr_phy_ctrl_1_shdw; - u32 emif_ddr_phy_ctrl_2; -}; - -struct dmm_lisa_map_regs { - u32 dmm_lisa_map_0; - u32 dmm_lisa_map_1; - u32 dmm_lisa_map_2; - u32 dmm_lisa_map_3; -}; - -#define CS0 0 -#define CS1 1 -/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ -#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ - -/* - * The period of DDR clk is represented as numerator and denominator for - * better accuracy in integer based calculations. However, if the numerator - * and denominator are very huge there may be chances of overflow in - * calculations. So, as a trade-off keep denominator(and consequently - * numerator) within a limit sacrificing some accuracy - but not much - * If denominator and numerator are already small (such as at 400 MHz) - * no adjustment is needed - */ -#define EMIF_PERIOD_DEN_LIMIT 1000 -/* - * Maximum number of different frequencies supported by EMIF driver - * Determines the number of entries in the pointer array for register - * cache - */ -#define EMIF_MAX_NUM_FREQUENCIES 6 -/* - * Indices into the Addressing Table array. - * One entry each for all the different types of devices with different - * addressing schemes - */ -#define ADDR_TABLE_INDEX64M 0 -#define ADDR_TABLE_INDEX128M 1 -#define ADDR_TABLE_INDEX256M 2 -#define ADDR_TABLE_INDEX512M 3 -#define ADDR_TABLE_INDEX1GS4 4 -#define ADDR_TABLE_INDEX2GS4 5 -#define ADDR_TABLE_INDEX4G 6 -#define ADDR_TABLE_INDEX8G 7 -#define ADDR_TABLE_INDEX1GS2 8 -#define ADDR_TABLE_INDEX2GS2 9 -#define ADDR_TABLE_INDEXMAX 10 - -/* Number of Row bits */ -#define ROW_9 0 -#define ROW_10 1 -#define ROW_11 2 -#define ROW_12 3 -#define ROW_13 4 -#define ROW_14 5 -#define ROW_15 6 -#define ROW_16 7 - -/* Number of Column bits */ -#define COL_8 0 -#define COL_9 1 -#define COL_10 2 -#define COL_11 3 -#define COL_7 4 /*Not supported by OMAP included for completeness */ - -/* Number of Banks*/ -#define BANKS1 0 -#define BANKS2 1 -#define BANKS4 2 -#define BANKS8 3 - -/* Refresh rate in micro seconds x 10 */ -#define T_REFI_15_6 156 -#define T_REFI_7_8 78 -#define T_REFI_3_9 39 - -#define EBANK_CS1_DIS 0 -#define EBANK_CS1_EN 1 - -/* Read Latency used by the device at reset */ -#define RL_BOOT 3 -/* Read Latency for the highest frequency you want to use */ -#define RL_FINAL 6 - -/* Interleaving policies at EMIF level- between banks and Chip Selects */ -#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 -#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 - -/* - * Interleaving policy to be used - * Currently set to MAX interleaving for better performance - */ -#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING - -/* State of the core voltage: - * This is important for some parameters such as read idle control and - * ZQ calibration timings. Timings are much stricter when voltage ramp - * is happening compared to when the voltage is stable. - * We need to calculate two sets of values for these parameters and use - * them accordingly - */ -#define LPDDR2_VOLTAGE_STABLE 0 -#define LPDDR2_VOLTAGE_RAMPING 1 - -/* Length of the forced read idle period in terms of cycles */ -#define EMIF_REG_READ_IDLE_LEN_VAL 5 - -/* Interval between forced 'read idles' */ -/* To be used when voltage is changed for DPS/DVFS - 1us */ -#define READ_IDLE_INTERVAL_DVFS (1*1000) -/* - * To be used when voltage is not scaled except by Smart Reflex - * 50us - or maximum value will do - */ -#define READ_IDLE_INTERVAL_NORMAL (50*1000) - - -/* - * Unless voltage is changing due to DVFS one ZQCS command every 50ms should - * be enough. This shoule be enough also in the case when voltage is changing - * due to smart-reflex. - */ -#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) -/* - * If voltage is changing due to DVFS ZQCS should be performed more - * often(every 50us) - */ -#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 - -/* The interval between ZQCL commands as a multiple of ZQCS interval */ -#define REG_ZQ_ZQCL_MULT 4 -/* The interval between ZQINIT commands as a multiple of ZQCL interval */ -#define REG_ZQ_ZQINIT_MULT 3 -/* Enable ZQ Calibration on exiting Self-refresh */ -#define REG_ZQ_SFEXITEN_ENABLE 1 -/* - * ZQ Calibration simultaneously on both chip-selects: - * Needs one calibration resistor per CS - * None of the boards that we know of have this capability - * So disabled by default - */ -#define REG_ZQ_DUALCALEN_DISABLE 0 -/* - * Enable ZQ Calibration by default on CS0. If we are asked to program - * the EMIF there will be something connected to CS0 for sure - */ -#define REG_ZQ_CS0EN_ENABLE 1 - -/* EMIF_PWR_MGMT_CTRL register */ -/* Low power modes */ -#define LP_MODE_DISABLE 0 -#define LP_MODE_CLOCK_STOP 1 -#define LP_MODE_SELF_REFRESH 2 -#define LP_MODE_PWR_DN 3 - -/* REG_DPD_EN */ -#define DPD_DISABLE 0 -#define DPD_ENABLE 1 - -/* Maximum delay before Low Power Modes */ -#define REG_CS_TIM 0xF -#define REG_SR_TIM 0xF -#define REG_PD_TIM 0xF - -/* EMIF_PWR_MGMT_CTRL register */ -#define EMIF_PWR_MGMT_CTRL (\ - ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\ - ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ - ((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\ - & OMAP44XX_REG_LP_MODE_MASK) |\ - ((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\ - & OMAP44XX_REG_DPD_EN_MASK))\ - -#define EMIF_PWR_MGMT_CTRL_SHDW (\ - ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_CS_TIM_SHDW_MASK) |\ - ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_SR_TIM_SHDW_MASK) |\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_PD_TIM_SHDW_MASK) |\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_PD_TIM_SHDW_MASK)) - -/* EMIF_L3_CONFIG register value */ -#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF -#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 -/* - * Value of bits 12:31 of DDR_PHY_CTRL_1 register: - * All these fields have magic values dependent on frequency and - * determined by PHY and DLL integration with EMIF. Setting the magic - * values suggested by hw team. - */ -#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF -#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 -#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 -#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF - -/* -* MR1 value: -* Burst length : 8 -* Burst type : sequential -* Wrap : enabled -* nWR : 3(default). EMIF does not do pre-charge. -* : So nWR is don't care -*/ -#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 - -/* MR2 */ -#define MR2_RL3_WL1 1 -#define MR2_RL4_WL2 2 -#define MR2_RL5_WL2 3 -#define MR2_RL6_WL3 4 - -/* MR10: ZQ calibration codes */ -#define MR10_ZQ_ZQCS 0x56 -#define MR10_ZQ_ZQCL 0xAB -#define MR10_ZQ_ZQINIT 0xFF -#define MR10_ZQ_ZQRESET 0xC3 - -/* TEMP_ALERT_CONFIG */ -#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ -#define TEMP_ALERT_CONFIG_DEVCT_1 0 -#define TEMP_ALERT_CONFIG_DEVWDT_32 2 - -/* MR16 value: refresh full array(no partial array self refresh) */ -#define MR16_REF_FULL_ARRAY 0 - -/* - * Maximum number of entries we keep in our array of timing tables - * We need not keep all the speed bins supported by the device - * We need to keep timing tables for only the speed bins that we - * are interested in - */ -#define MAX_NUM_SPEEDBINS 4 - -/* LPDDR2 Densities */ -#define LPDDR2_DENSITY_64Mb 0 -#define LPDDR2_DENSITY_128Mb 1 -#define LPDDR2_DENSITY_256Mb 2 -#define LPDDR2_DENSITY_512Mb 3 -#define LPDDR2_DENSITY_1Gb 4 -#define LPDDR2_DENSITY_2Gb 5 -#define LPDDR2_DENSITY_4Gb 6 -#define LPDDR2_DENSITY_8Gb 7 -#define LPDDR2_DENSITY_16Gb 8 -#define LPDDR2_DENSITY_32Gb 9 - -/* LPDDR2 type */ -#define LPDDR2_TYPE_S4 0 -#define LPDDR2_TYPE_S2 1 -#define LPDDR2_TYPE_NVM 2 - -/* LPDDR2 IO width */ -#define LPDDR2_IO_WIDTH_32 0 -#define LPDDR2_IO_WIDTH_16 1 -#define LPDDR2_IO_WIDTH_8 2 - -/* Mode register numbers */ -#define LPDDR2_MR0 0 -#define LPDDR2_MR1 1 -#define LPDDR2_MR2 2 -#define LPDDR2_MR3 3 -#define LPDDR2_MR4 4 -#define LPDDR2_MR5 5 -#define LPDDR2_MR6 6 -#define LPDDR2_MR7 7 -#define LPDDR2_MR8 8 -#define LPDDR2_MR9 9 -#define LPDDR2_MR10 10 -#define LPDDR2_MR11 11 -#define LPDDR2_MR16 16 -#define LPDDR2_MR17 17 -#define LPDDR2_MR18 18 - -/* MR0 */ -#define LPDDR2_MR0_DAI_SHIFT 0 -#define LPDDR2_MR0_DAI_MASK 1 -#define LPDDR2_MR0_DI_SHIFT 1 -#define LPDDR2_MR0_DI_MASK (1 << 1) -#define LPDDR2_MR0_DNVI_SHIFT 2 -#define LPDDR2_MR0_DNVI_MASK (1 << 2) - -/* MR4 */ -#define MR4_SDRAM_REF_RATE_SHIFT 0 -#define MR4_SDRAM_REF_RATE_MASK 7 -#define MR4_TUF_SHIFT 7 -#define MR4_TUF_MASK (1 << 7) - -/* MR4 SDRAM Refresh Rate field values */ -#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 -#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 -#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 -#define SDRAM_TEMP_NOMINAL 0x3 -#define SDRAM_TEMP_RESERVED_4 0x4 -#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 -#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 -#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 - -#define LPDDR2_MANUFACTURER_SAMSUNG 1 -#define LPDDR2_MANUFACTURER_QIMONDA 2 -#define LPDDR2_MANUFACTURER_ELPIDA 3 -#define LPDDR2_MANUFACTURER_ETRON 4 -#define LPDDR2_MANUFACTURER_NANYA 5 -#define LPDDR2_MANUFACTURER_HYNIX 6 -#define LPDDR2_MANUFACTURER_MOSEL 7 -#define LPDDR2_MANUFACTURER_WINBOND 8 -#define LPDDR2_MANUFACTURER_ESMT 9 -#define LPDDR2_MANUFACTURER_SPANSION 11 -#define LPDDR2_MANUFACTURER_SST 12 -#define LPDDR2_MANUFACTURER_ZMOS 13 -#define LPDDR2_MANUFACTURER_INTEL 14 -#define LPDDR2_MANUFACTURER_NUMONYX 254 -#define LPDDR2_MANUFACTURER_MICRON 255 - -/* MR8 register fields */ -#define MR8_TYPE_SHIFT 0x0 -#define MR8_TYPE_MASK 0x3 -#define MR8_DENSITY_SHIFT 0x2 -#define MR8_DENSITY_MASK (0xF << 0x2) -#define MR8_IO_WIDTH_SHIFT 0x6 -#define MR8_IO_WIDTH_MASK (0x3 << 0x6) - -struct lpddr2_addressing { - u8 num_banks; - u8 t_REFI_us_x10; - u8 row_sz[2]; /* One entry each for x32 and x16 */ - u8 col_sz[2]; /* One entry each for x32 and x16 */ -}; - -/* Structure for timings from the DDR datasheet */ -struct lpddr2_ac_timings { - u32 max_freq; - u8 RL; - u8 tRPab; - u8 tRCD; - u8 tWR; - u8 tRASmin; - u8 tRRD; - u8 tWTRx2; - u8 tXSR; - u8 tXPx2; - u8 tRFCab; - u8 tRTPx2; - u8 tCKE; - u8 tCKESR; - u8 tZQCS; - u32 tZQCL; - u32 tZQINIT; - u8 tDQSCKMAXx2; - u8 tRASmax; - u8 tFAW; - -}; - -/* - * Min tCK values for some of the parameters: - * If the calculated clock cycles for the respective parameter is - * less than the corresponding min tCK value, we need to set the min - * tCK value. This may happen at lower frequencies. - */ -struct lpddr2_min_tck { - u32 tRL; - u32 tRP_AB; - u32 tRCD; - u32 tWR; - u32 tRAS_MIN; - u32 tRRD; - u32 tWTR; - u32 tXP; - u32 tRTP; - u8 tCKE; - u32 tCKESR; - u32 tFAW; -}; - -struct lpddr2_device_details { - u8 type; - u8 density; - u8 io_width; - u8 manufacturer; -}; - -struct lpddr2_device_timings { - const struct lpddr2_ac_timings **ac_timings; - const struct lpddr2_min_tck *min_tck; -}; - -/* Details of the devices connected to each chip-select of an EMIF instance */ -struct emif_device_details { - const struct lpddr2_device_details *cs0_device_details; - const struct lpddr2_device_details *cs1_device_details; - const struct lpddr2_device_timings *cs0_device_timings; - const struct lpddr2_device_timings *cs1_device_timings; -}; - -/* - * Structure containing shadow of important registers in EMIF - * The calculation function fills in this structure to be later used for - * initialization and DVFS - */ -struct emif_regs { - u32 freq; - u32 sdram_config_init; - u32 sdram_config; - u32 ref_ctrl; - u32 sdram_tim1; - u32 sdram_tim2; - u32 sdram_tim3; - u32 read_idle_ctrl; - u32 zq_config; - u32 temp_alert_config; - u32 emif_ddr_phy_ctlr_1_init; - u32 emif_ddr_phy_ctlr_1; -}; - -/* assert macros */ -#if defined(DEBUG) -#define emif_assert(c) ({ if (!(c)) for (;;); }) -#else -#define emif_assert(c) ({ if (0) hang(); }) -#endif - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); -void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); -#else -struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, - struct lpddr2_device_details *lpddr2_dev_details); -void emif_get_device_timings(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h index 733d8ed34a..74439c9d9b 100644 --- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h @@ -33,7 +33,7 @@ #define OMAP_HSMMC2_BASE 0x480B4100 #define OMAP_HSMMC3_BASE 0x480AD100 -typedef struct hsmmc { +struct hsmmc { unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned int sysstatus; /* 0x14 */ @@ -55,7 +55,7 @@ typedef struct hsmmc { unsigned int ie; /* 0x134 */ unsigned char res4[0x8]; unsigned int capa; /* 0x140 */ -} hsmmc_t; +}; /* * OMAP HS MMC Bit definitions @@ -160,13 +160,6 @@ typedef struct hsmmc { #define CLK_400KHZ 1 #define CLK_MISC 2 -typedef struct { - unsigned int card_type; - unsigned int version; - unsigned int mode; - unsigned int size; - unsigned int RCA; -} mmc_card_data; #define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap.h index 61ebb3d46d..4d8c89ffbd 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -44,7 +44,8 @@ #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 - +#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START +#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END /* CONTROL */ #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) @@ -57,14 +58,11 @@ /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE 0x4A002204 -/* 4430 */ -#define OMAP4430_CONTROL_ID_CODE_ES1_0 0x0B85202F -#define OMAP4430_CONTROL_ID_CODE_ES2_0 0x1B85202F -#define OMAP4430_CONTROL_ID_CODE_ES2_1 0x3B95C02F -#define OMAP4430_CONTROL_ID_CODE_ES2_2 0x4B95C02F -#define OMAP4430_CONTROL_ID_CODE_ES2_3 0x6B95C02F - -/* 4460 */ +#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F @@ -151,7 +149,7 @@ struct omap4_sys_ctrl_regs { unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ unsigned int pad3[260277]; - unsigned int control_pbiaslite; /* 0x4A100600 */ + unsigned int control_pbiaslite; /* 0x4A100600 */ unsigned int pad4[63]; unsigned int control_efuse_1; /* 0x4A100700 */ unsigned int control_efuse_2; /* 0x4A100704 */ @@ -188,16 +186,6 @@ struct control_lpddr2io_regs { #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) -/* Silicon revisions */ -#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF -#define OMAP4430_ES1_0 0x44300100 -#define OMAP4430_ES2_0 0x44300200 -#define OMAP4430_ES2_1 0x44300210 -#define OMAP4430_ES2_2 0x44300220 -#define OMAP4430_ES2_3 0x44300230 -#define OMAP4460_ES1_0 0x44600100 -#define OMAP4460_ES1_1 0x44600110 - /* ROM code defines */ /* Boot device */ #define BOOT_DEVICE_MASK 0xFF @@ -205,5 +193,21 @@ struct control_lpddr2io_regs { #define DEV_DESC_PTR_OFFSET 0x4 #define DEV_DATA_PTR_OFFSET 0x18 #define BOOT_MODE_OFFSET 0x8 +#define RESET_REASON_OFFSET 0x9 +#define CH_FLAGS_OFFSET 0xA + +#define CH_FLAGS_CHSETTINGS (0x1 << 0) +#define CH_FLAGS_CHRAM (0x1 << 1) +#define CH_FLAGS_CHFLASH (0x1 << 2) +#define CH_FLAGS_CHMMCSD (0x1 << 3) +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + char *boot_message; + unsigned int mem_boot_descriptor; + unsigned char omap_bootdevice; + unsigned char reset_reason; + unsigned char ch_flags; +}; +#endif #endif diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 1aacbb12e3..4146e21818 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -21,7 +21,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#include <asm/arch/omap4.h> +#include <asm/arch/omap.h> #include <asm/arch/clocks.h> #include <asm/io.h> #include <asm/omap_common.h> @@ -32,17 +32,17 @@ struct omap_sysinfo { }; extern const struct omap_sysinfo sysinfo; -extern struct omap4_prcm_regs *const prcm; - void gpmc_init(void); void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs_essential(void); void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void set_pl310_ctrl_reg(u32 val); +void omap_rev_string(char *omap_rev_string); void setup_clocks_for_console(void); void prcm_init(void); void bypass_dpll(u32 *const base); @@ -51,7 +51,17 @@ u32 get_sys_clk_freq(void); u32 omap4_ddr_clk(void); void cancel_out(u32 *num, u32 *den, u32 den_limit); void sdram_init(void); -u32 omap4_sdram_size(void); +u32 omap_sdram_size(void); +u32 cortex_rev(void); +void init_omap_revision(void); +void do_io_settings(void); +/* + * This is used to verify if the configuration header + * was executed by Romcode prior to control of transfer + * to the bootloader. SPL is responsible for saving and + * passing this to the u-boot. + */ +extern struct omap_boot_parameters boot_params; static inline u32 running_from_sdram(void) { @@ -64,15 +74,17 @@ static inline u32 running_from_sdram(void) static inline u8 uboot_loaded_by_spl(void) { /* - * Configuration Header is not supported yet, so u-boot init running - * from SDRAM implies that it was loaded by SPL. When this situation - * changes one of these approaches could be taken: - * i. Pass a magic from SPL to U-Boot and U-Boot save it at a known - * location. - * ii. Check the OPP. CH can support only 50% OPP while SPL initializes - * the DPLLs at 100% OPP. + * u-boot can be running from sdram either because of configuration + * Header or by SPL. If because of CH, then the romcode sets the + * CHSETTINGS executed bit to true in the boot parameter structure that + * it passes to the bootloader.This parameter is stored in the ch_flags + * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a + * mandatory section if CH is present. */ - return running_from_sdram(); + if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + return 0; + else + return running_from_sdram(); } /* * The basic hardware init of OMAP(s_init()) can happen in 4 @@ -86,7 +98,7 @@ static inline u8 uboot_loaded_by_spl(void) * This function finds this context. * Defining as inline may help in compiling out unused functions in SPL */ -static inline u32 omap4_hw_init_context(void) +static inline u32 omap_hw_init_context(void) { #ifdef CONFIG_SPL_BUILD return OMAP_INIT_CONTEXT_SPL; diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h new file mode 100644 index 0000000000..d0e6dd68da --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -0,0 +1,722 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * Sricharan R <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP5_H_ +#define _CLOCKS_OMAP5_H_ +#include <common.h> + +/* + * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per + * loop, allow for a minimum of 2 ms wait (in reality the wait will be + * much more than that) + */ +#define LDELAY 1000000 + +#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120) +#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140) +#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160) +#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100) + +struct omap5_prcm_regs { + /* cm1.ckgen */ + u32 cm_clksel_core; /* 4a004100 */ + u32 pad001[1]; /* 4a004104 */ + u32 cm_clksel_abe; /* 4a004108 */ + u32 pad002[1]; /* 4a00410c */ + u32 cm_dll_ctrl; /* 4a004110 */ + u32 pad003[3]; /* 4a004114 */ + u32 cm_clkmode_dpll_core; /* 4a004120 */ + u32 cm_idlest_dpll_core; /* 4a004124 */ + u32 cm_autoidle_dpll_core; /* 4a004128 */ + u32 cm_clksel_dpll_core; /* 4a00412c */ + u32 cm_div_m2_dpll_core; /* 4a004130 */ + u32 cm_div_m3_dpll_core; /* 4a004134 */ + u32 cm_div_h11_dpll_core; /* 4a004138 */ + u32 cm_div_h12_dpll_core; /* 4a00413c */ + u32 cm_div_h13_dpll_core; /* 4a004140 */ + u32 cm_div_h14_dpll_core; /* 4a004144 */ + u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */ + u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */ + u32 cm_emu_override_dpll_core; /* 4a004150 */ + + u32 cm_div_h22_dpllcore; /* 4a004154 */ + u32 cm_div_h23_dpll_core; /* 4a004158 */ + u32 pad0041[1]; /* 4a00415c */ + u32 cm_clkmode_dpll_mpu; /* 4a004160 */ + u32 cm_idlest_dpll_mpu; /* 4a004164 */ + u32 cm_autoidle_dpll_mpu; /* 4a004168 */ + u32 cm_clksel_dpll_mpu; /* 4a00416c */ + u32 cm_div_m2_dpll_mpu; /* 4a004170 */ + u32 pad005[5]; /* 4a004174 */ + u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */ + u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */ + u32 pad006[3]; /* 4a004190 */ + u32 cm_bypclk_dpll_mpu; /* 4a00419c */ + u32 cm_clkmode_dpll_iva; /* 4a0041a0 */ + u32 cm_idlest_dpll_iva; /* 4a0041a4 */ + u32 cm_autoidle_dpll_iva; /* 4a0041a8 */ + u32 cm_clksel_dpll_iva; /* 4a0041ac */ + u32 pad007[2]; /* 4a0041b0 */ + u32 cm_div_h11_dpll_iva; /* 4a0041b8 */ + u32 cm_div_h12_dpll_iva; /* 4a0041bc */ + u32 pad008[2]; /* 4a0041c0 */ + u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */ + u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */ + u32 pad009[3]; /* 4a0041d0 */ + u32 cm_bypclk_dpll_iva; /* 4a0041dc */ + u32 cm_clkmode_dpll_abe; /* 4a0041e0 */ + u32 cm_idlest_dpll_abe; /* 4a0041e4 */ + u32 cm_autoidle_dpll_abe; /* 4a0041e8 */ + u32 cm_clksel_dpll_abe; /* 4a0041ec */ + u32 cm_div_m2_dpll_abe; /* 4a0041f0 */ + u32 cm_div_m3_dpll_abe; /* 4a0041f4 */ + u32 pad010[4]; /* 4a0041f8 */ + u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */ + u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */ + u32 pad011[4]; /* 4a004210 */ + u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */ + u32 cm_idlest_dpll_ddrphy; /* 4a004224 */ + u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */ + u32 cm_clksel_dpll_ddrphy; /* 4a00422c */ + u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */ + u32 pad012[1]; /* 4a004234 */ + u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */ + u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */ + u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */ + u32 pad013[1]; /* 4a004244 */ + u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */ + u32 pad014[5]; /* 4a00424c */ + u32 cm_shadow_freq_config1; /* 4a004260 */ + u32 pad0141[47]; /* 4a004264 */ + u32 cm_mpu_mpu_clkctrl; /* 4a004320 */ + + + /* cm1.dsp */ + u32 pad015[55]; /* 4a004324 */ + u32 cm_dsp_clkstctrl; /* 4a004400 */ + u32 pad016[7]; /* 4a004404 */ + u32 cm_dsp_dsp_clkctrl; /* 4a004420 */ + + /* cm1.abe */ + u32 pad017[55]; /* 4a004424 */ + u32 cm1_abe_clkstctrl; /* 4a004500 */ + u32 pad018[7]; /* 4a004504 */ + u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */ + u32 pad019[1]; /* 4a004524 */ + u32 cm1_abe_aess_clkctrl; /* 4a004528 */ + u32 pad020[1]; /* 4a00452c */ + u32 cm1_abe_pdm_clkctrl; /* 4a004530 */ + u32 pad021[1]; /* 4a004534 */ + u32 cm1_abe_dmic_clkctrl; /* 4a004538 */ + u32 pad022[1]; /* 4a00453c */ + u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */ + u32 pad023[1]; /* 4a004544 */ + u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */ + u32 pad024[1]; /* 4a00454c */ + u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */ + u32 pad025[1]; /* 4a004554 */ + u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */ + u32 pad026[1]; /* 4a00455c */ + u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */ + u32 pad027[1]; /* 4a004564 */ + u32 cm1_abe_timer5_clkctrl; /* 4a004568 */ + u32 pad028[1]; /* 4a00456c */ + u32 cm1_abe_timer6_clkctrl; /* 4a004570 */ + u32 pad029[1]; /* 4a004574 */ + u32 cm1_abe_timer7_clkctrl; /* 4a004578 */ + u32 pad030[1]; /* 4a00457c */ + u32 cm1_abe_timer8_clkctrl; /* 4a004580 */ + u32 pad031[1]; /* 4a004584 */ + u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */ + + /* cm2.ckgen */ + u32 pad032[3805]; /* 4a00458c */ + u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */ + u32 cm_clksel_usb_60mhz; /* 4a008104 */ + u32 cm_scale_fclk; /* 4a008108 */ + u32 pad033[1]; /* 4a00810c */ + u32 cm_core_dvfs_perf1; /* 4a008110 */ + u32 cm_core_dvfs_perf2; /* 4a008114 */ + u32 cm_core_dvfs_perf3; /* 4a008118 */ + u32 cm_core_dvfs_perf4; /* 4a00811c */ + u32 pad034[1]; /* 4a008120 */ + u32 cm_core_dvfs_current; /* 4a008124 */ + u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */ + u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */ + u32 cm_iva_dvfs_perf_abe; /* 4a008130 */ + u32 pad035[1]; /* 4a008134 */ + u32 cm_iva_dvfs_current; /* 4a008138 */ + u32 pad036[1]; /* 4a00813c */ + u32 cm_clkmode_dpll_per; /* 4a008140 */ + u32 cm_idlest_dpll_per; /* 4a008144 */ + u32 cm_autoidle_dpll_per; /* 4a008148 */ + u32 cm_clksel_dpll_per; /* 4a00814c */ + u32 cm_div_m2_dpll_per; /* 4a008150 */ + u32 cm_div_m3_dpll_per; /* 4a008154 */ + u32 cm_div_h11_dpll_per; /* 4a008158 */ + u32 cm_div_h12_dpll_per; /* 4a00815c */ + u32 pad0361[1]; /* 4a008160 */ + u32 cm_div_h14_dpll_per; /* 4a008164 */ + u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */ + u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */ + u32 cm_emu_override_dpll_per; /* 4a008170 */ + u32 pad037[3]; /* 4a008174 */ + u32 cm_clkmode_dpll_usb; /* 4a008180 */ + u32 cm_idlest_dpll_usb; /* 4a008184 */ + u32 cm_autoidle_dpll_usb; /* 4a008188 */ + u32 cm_clksel_dpll_usb; /* 4a00818c */ + u32 cm_div_m2_dpll_usb; /* 4a008190 */ + u32 pad038[5]; /* 4a008194 */ + u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */ + u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */ + u32 pad039[1]; /* 4a0081b0 */ + u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */ + u32 pad040[2]; /* 4a0081b8 */ + u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */ + u32 cm_idlest_dpll_unipro; /* 4a0081c4 */ + u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */ + u32 cm_clksel_dpll_unipro; /* 4a0081cc */ + u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */ + u32 pad041[5]; /* 4a0081d4 */ + u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */ + u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */ + + /* cm2.core */ + u32 pad0411[324]; /* 4a0081f0 */ + u32 cm_l3_1_clkstctrl; /* 4a008700 */ + u32 pad042[1]; /* 4a008704 */ + u32 cm_l3_1_dynamicdep; /* 4a008708 */ + u32 pad043[5]; /* 4a00870c */ + u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */ + u32 pad044[55]; /* 4a008724 */ + u32 cm_l3_2_clkstctrl; /* 4a008800 */ + u32 pad045[1]; /* 4a008804 */ + u32 cm_l3_2_dynamicdep; /* 4a008808 */ + u32 pad046[5]; /* 4a00880c */ + u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */ + u32 pad047[1]; /* 4a008824 */ + u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */ + u32 pad048[1]; /* 4a00882c */ + u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */ + u32 pad049[51]; /* 4a008834 */ + u32 cm_mpu_m3_clkstctrl; /* 4a008900 */ + u32 cm_mpu_m3_staticdep; /* 4a008904 */ + u32 cm_mpu_m3_dynamicdep; /* 4a008908 */ + u32 pad050[5]; /* 4a00890c */ + u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */ + u32 pad051[55]; /* 4a008924 */ + u32 cm_sdma_clkstctrl; /* 4a008a00 */ + u32 cm_sdma_staticdep; /* 4a008a04 */ + u32 cm_sdma_dynamicdep; /* 4a008a08 */ + u32 pad052[5]; /* 4a008a0c */ + u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */ + u32 pad053[55]; /* 4a008a24 */ + u32 cm_memif_clkstctrl; /* 4a008b00 */ + u32 pad054[7]; /* 4a008b04 */ + u32 cm_memif_dmm_clkctrl; /* 4a008b20 */ + u32 pad055[1]; /* 4a008b24 */ + u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */ + u32 pad056[1]; /* 4a008b2c */ + u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */ + u32 pad057[1]; /* 4a008b34 */ + u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */ + u32 pad058[1]; /* 4a008b3c */ + u32 cm_memif_dll_clkctrl; /* 4a008b40 */ + u32 pad059[3]; /* 4a008b44 */ + u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */ + u32 pad060[1]; /* 4a008b54 */ + u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */ + u32 pad061[1]; /* 4a008b5c */ + u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */ + u32 pad062[39]; /* 4a008b64 */ + u32 cm_c2c_clkstctrl; /* 4a008c00 */ + u32 cm_c2c_staticdep; /* 4a008c04 */ + u32 cm_c2c_dynamicdep; /* 4a008c08 */ + u32 pad063[5]; /* 4a008c0c */ + u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */ + u32 pad064[1]; /* 4a008c24 */ + u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */ + u32 pad065[1]; /* 4a008c2c */ + u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */ + u32 pad066[51]; /* 4a008c34 */ + u32 cm_l4cfg_clkstctrl; /* 4a008d00 */ + u32 pad067[1]; /* 4a008d04 */ + u32 cm_l4cfg_dynamicdep; /* 4a008d08 */ + u32 pad068[5]; /* 4a008d0c */ + u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */ + u32 pad069[1]; /* 4a008d24 */ + u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */ + u32 pad070[1]; /* 4a008d2c */ + u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */ + u32 pad071[1]; /* 4a008d34 */ + u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */ + u32 pad072[49]; /* 4a008d3c */ + u32 cm_l3instr_clkstctrl; /* 4a008e00 */ + u32 pad073[7]; /* 4a008e04 */ + u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */ + u32 pad074[1]; /* 4a008e24 */ + u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */ + u32 pad075[5]; /* 4a008e2c */ + u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */ + + + /* cm2.ivahd */ + u32 pad076[47]; /* 4a008e44 */ + u32 cm_ivahd_clkstctrl; /* 4a008f00 */ + u32 pad077[7]; /* 4a008f04 */ + u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */ + u32 pad078[1]; /* 4a008f24 */ + u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */ + + /* cm2.cam */ + u32 pad079[53]; /* 4a008f2c */ + u32 cm_cam_clkstctrl; /* 4a009000 */ + u32 pad080[7]; /* 4a009004 */ + u32 cm_cam_iss_clkctrl; /* 4a009020 */ + u32 pad081[1]; /* 4a009024 */ + u32 cm_cam_fdif_clkctrl; /* 4a009028 */ + + /* cm2.dss */ + u32 pad082[53]; /* 4a00902c */ + u32 cm_dss_clkstctrl; /* 4a009100 */ + u32 pad083[7]; /* 4a009104 */ + u32 cm_dss_dss_clkctrl; /* 4a009120 */ + + /* cm2.sgx */ + u32 pad084[55]; /* 4a009124 */ + u32 cm_sgx_clkstctrl; /* 4a009200 */ + u32 pad085[7]; /* 4a009204 */ + u32 cm_sgx_sgx_clkctrl; /* 4a009220 */ + + /* cm2.l3init */ + u32 pad086[55]; /* 4a009224 */ + u32 cm_l3init_clkstctrl; /* 4a009300 */ + + /* cm2.l3init */ + u32 pad087[9]; /* 4a009304 */ + u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */ + u32 pad088[1]; /* 4a00932c */ + u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */ + u32 pad089[1]; /* 4a009334 */ + u32 cm_l3init_hsi_clkctrl; /* 4a009338 */ + u32 pad090[7]; /* 4a00933c */ + u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */ + u32 pad091[1]; /* 4a00935c */ + u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */ + u32 pad092[1]; /* 4a009364 */ + u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */ + u32 pad093[3]; /* 4a00936c */ + u32 cm_l3init_p1500_clkctrl; /* 4a009378 */ + u32 pad094[21]; /* 4a00937c */ + u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */ + u32 pad095[3]; /* 4a0093d4 */ + u32 cm_l3init_ocp2scp1_clkctrl; + + /* cm2.l4per */ + u32 pad096[7]; /* 4a0093e4 */ + u32 cm_l4per_clkstctrl; /* 4a009400 */ + u32 pad097[1]; /* 4a009404 */ + u32 cm_l4per_dynamicdep; /* 4a009408 */ + u32 pad098[5]; /* 4a00940c */ + u32 cm_l4per_adc_clkctrl; /* 4a009420 */ + u32 pad100[1]; /* 4a009424 */ + u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */ + u32 pad101[1]; /* 4a00942c */ + u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */ + u32 pad102[1]; /* 4a009434 */ + u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */ + u32 pad103[1]; /* 4a00943c */ + u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */ + u32 pad104[1]; /* 4a009444 */ + u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */ + u32 pad105[1]; /* 4a00944c */ + u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */ + u32 pad106[1]; /* 4a009454 */ + u32 cm_l4per_elm_clkctrl; /* 4a009458 */ + u32 pad107[1]; /* 4a00945c */ + u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */ + u32 pad108[1]; /* 4a009464 */ + u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */ + u32 pad109[1]; /* 4a00946c */ + u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */ + u32 pad110[1]; /* 4a009474 */ + u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */ + u32 pad111[1]; /* 4a00947c */ + u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */ + u32 pad112[1]; /* 4a009484 */ + u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */ + u32 pad113[1]; /* 4a00948c */ + u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */ + u32 pad114[1]; /* 4a009494 */ + u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */ + u32 pad115[1]; /* 4a00949c */ + u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */ + u32 pad116[1]; /* 4a0094a4 */ + u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */ + u32 pad117[1]; /* 4a0094ac */ + u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */ + u32 pad118[1]; /* 4a0094b4 */ + u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */ + u32 pad119[1]; /* 4a0094bc */ + u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */ + u32 pad1191[3]; /* 4a0094c4 */ + u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */ + u32 pad120[1]; /* 4a0094d4 */ + u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */ + u32 pad121[3]; /* 4a0094dc */ + u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */ + u32 pad123[1]; /* 4a0094ec */ + u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */ + u32 pad124[1]; /* 4a0094f4 */ + u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */ + u32 pad125[1]; /* 4a0094fc */ + u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */ + u32 pad126[1]; /* 4a009504 */ + u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */ + u32 pad127[1]; /* 4a00950c */ + u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */ + u32 pad1271[1]; /* 4a009514 */ + u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */ + u32 pad1272[1]; /* 4a00951c */ + u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */ + u32 pad128[1]; /* 4a009524 */ + u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */ + u32 pad129[1]; /* 4a00952c */ + u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */ + u32 pad130[1]; /* 4a009534 */ + u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */ + u32 pad131[1]; /* 4a00953c */ + u32 cm_l4per_uart1_clkctrl; /* 4a009540 */ + u32 pad132[1]; /* 4a009544 */ + u32 cm_l4per_uart2_clkctrl; /* 4a009548 */ + u32 pad133[1]; /* 4a00954c */ + u32 cm_l4per_uart3_clkctrl; /* 4a009550 */ + u32 pad134[1]; /* 4a009554 */ + u32 cm_l4per_uart4_clkctrl; /* 4a009558 */ + u32 pad135[1]; /* 4a00955c */ + u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */ + u32 pad136[1]; /* 4a009564 */ + u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */ + u32 pad1371[1]; /* 4a00956c */ + u32 cm_l4per_uart5_clkctrl; /* 4a009570 */ + u32 pad1372[1]; /* 4a009574 */ + u32 cm_l4per_uart6_clkctrl; /* 4a009578 */ + u32 pad1374[1]; /* 4a00957c */ + u32 cm_l4sec_clkstctrl; /* 4a009580 */ + u32 cm_l4sec_staticdep; /* 4a009584 */ + u32 cm_l4sec_dynamicdep; /* 4a009588 */ + u32 pad138[5]; /* 4a00958c */ + u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */ + u32 pad139[1]; /* 4a0095a4 */ + u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */ + u32 pad140[1]; /* 4a0095ac */ + u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */ + u32 pad141[1]; /* 4a0095b4 */ + u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */ + u32 pad142[1]; /* 4a0095bc */ + u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */ + u32 pad143[1]; /* 4a0095c4 */ + u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */ + u32 pad144[3]; /* 4a0095cc */ + u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */ + u32 pad145[3660425]; /* 4a0095dc */ + + /* l4 wkup regs */ + u32 pad201[6211]; /* 4ae00000 */ + u32 cm_abe_pll_ref_clksel; /* 4ae0610c */ + u32 cm_sys_clksel; /* 4ae06110 */ + u32 pad202[1467]; /* 4ae06114 */ + u32 cm_wkup_clkstctrl; /* 4ae07800 */ + u32 pad203[7]; /* 4ae07804 */ + u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */ + u32 pad204; /* 4ae07824 */ + u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */ + u32 pad205; /* 4ae0782c */ + u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */ + u32 pad206; /* 4ae07834 */ + u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */ + u32 pad207; /* 4ae0783c */ + u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */ + u32 pad208; /* 4ae07844 */ + u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */ + u32 pad209; /* 4ae0784c */ + u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */ + u32 pad210; /* 4ae07854 */ + u32 cm_wkup_usim_clkctrl; /* 4ae07858 */ + u32 pad211; /* 4ae0785c */ + u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */ + u32 pad212[5]; /* 4ae07864 */ + u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */ + u32 pad213; /* 4ae0787c */ + u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */ + u32 pad214; /* 4ae07884 */ + u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */ + u32 pad215[197]; /* 4ae0788c */ + u32 prm_vc_val_bypass; /* 4ae07ba0 */ + u32 pad216[4]; + u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ + u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ +}; + +/* DPLL register offsets */ +#define CM_CLKMODE_DPLL 0 +#define CM_IDLEST_DPLL 0x4 +#define CM_AUTOIDLE_DPLL 0x8 +#define CM_CLKSEL_DPLL 0xC + +#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F +#define CM_CLKSEL_DCC_EN_SHIFT 22 +#define CM_CLKSEL_DCC_EN_MASK (1 << 22) + +#define OMAP4_DPLL_MAX_N 127 + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_ABE_PLL_REF_CLKSEL */ +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 + +/* CM_BYPCLK_DPLL_IVA */ +#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 +#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 + +#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/*CM_<clock_domain>__CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + + +/* CM_<clock_domain>_<module>_CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_CAM_ISS_CLKCTRL */ +#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_DSS_DSS_CLKCTRL */ +#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 + +/* CM_MPU_MPU_CLKCTRL */ +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) + +/* Clock frequencies */ +#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 +#define OMAP_32K_CLK_FREQ 32768 + +/* PRM_VC_CFG_I2C_CLK */ +#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 +#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 +#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + +#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F +#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 +#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF +#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 +#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF + +/* SMPS */ +#define SMPS_I2C_SLAVE_ADDR 0x12 +#define SMPS_REG_ADDR_VCORE1 0x55 +#define SMPS_REG_ADDR_VCORE2 0x5B +#define SMPS_REG_ADDR_VCORE3 0x61 + +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 + +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 +#define TPS62361_VSEL0_GPIO 7 + +/* Defines for DPLL setup */ +#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 +#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 +#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +#define NUM_SYS_CLKS 7 + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_h11_dpll; + u32 cm_div_h12_dpll; + u32 cm_div_h13_dpll; + u32 cm_div_h14_dpll; + u32 reserved[2]; + u32 cm_div_h22_dpll; + u32 cm_div_h23_dpll; +}; + +/* DPLL parameter table */ +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 h11; + s8 h12; + s8 h13; + s8 h14; + s8 h22; + s8 h23; +}; + +extern struct omap5_prcm_regs *const prcm; +extern const u32 sys_clk_array[8]; + +void scale_vcores(void); +void do_scale_tps62361(u32 reg, u32 volt_mv); +u32 omap_ddr_clk(void); +void do_scale_vcore(u32 vcore_reg, u32 volt_mv); +void setup_sri2c(void); +void setup_post_dividers(u32 *const base, const struct dpll_params *params); +u32 get_sys_clk_index(void); +void enable_basic_clocks(void); +void enable_non_essential_clocks(void); +void enable_basic_uboot_clocks(void); +void do_enable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_hw_auto, + u32 *const *clk_modules_explicit_en, + u8 wait_for_enable); +const struct dpll_params *get_mpu_dpll_params(void); +const struct dpll_params *get_core_dpll_params(void); +const struct dpll_params *get_per_dpll_params(void); +const struct dpll_params *get_iva_dpll_params(void); +const struct dpll_params *get_usb_dpll_params(void); +const struct dpll_params *get_abe_dpll_params(void); +#endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h new file mode 100644 index 0000000000..0697a732de --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2006-2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _CPU_H +#define _CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct gpmc_cs { + u32 config1; /* 0x00 */ + u32 config2; /* 0x04 */ + u32 config3; /* 0x08 */ + u32 config4; /* 0x0C */ + u32 config5; /* 0x10 */ + u32 config6; /* 0x14 */ + u32 config7; /* 0x18 */ + u32 nand_cmd; /* 0x1C */ + u32 nand_adr; /* 0x20 */ + u32 nand_dat; /* 0x24 */ + u8 res[8]; /* blow up to 0x30 byte */ +}; + +struct gpmc { + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x4]; + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res3[0x20]; + u32 timeout_control; /* 0x40 */ + u8 res4[0xC]; + u32 config; /* 0x50 */ + u32 status; /* 0x54 */ + u8 res5[0x8]; /* 0x58 */ + struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ + u8 res6[0x14]; /* 0x1E0 */ + u32 ecc_config; /* 0x1F4 */ + u32 ecc_control; /* 0x1F8 */ + u32 ecc_size_config; /* 0x1FC */ + u32 ecc1_result; /* 0x200 */ + u32 ecc2_result; /* 0x204 */ + u32 ecc3_result; /* 0x208 */ + u32 ecc4_result; /* 0x20C */ + u32 ecc5_result; /* 0x210 */ + u32 ecc6_result; /* 0x214 */ + u32 ecc7_result; /* 0x218 */ + u32 ecc8_result; /* 0x21C */ + u32 ecc9_result; /* 0x220 */ +}; + +/* Used for board specific gpmc initialization */ +extern struct gpmc *gpmc_cfg; + +struct gptimer { + u32 tidr; /* 0x00 r */ + u8 res1[0xc]; + u32 tiocp_cfg; /* 0x10 rw */ + u8 res2[0x10]; + u32 tisr_raw; /* 0x24 r */ + u32 tisr; /* 0x28 rw */ + u32 tier; /* 0x2c rw */ + u32 ticr; /* 0x30 rw */ + u32 twer; /* 0x34 rw */ + u32 tclr; /* 0x38 rw */ + u32 tcrr; /* 0x3c rw */ + u32 tldr; /* 0x40 rw */ + u32 ttgr; /* 0x44 rw */ + u32 twpc; /* 0x48 r */ + u32 tmar; /* 0x4c rw */ + u32 tcar1; /* 0x50 r */ + u32 tcicr; /* 0x54 rw */ + u32 tcar2; /* 0x58 r */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/* Watchdog */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct watchdog { + u8 res1[0x34]; + u32 wwps; /* 0x34 r */ + u8 res2[0x10]; + u32 wspr; /* 0x48 rw */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +#define SYSCLKDIV_1 (0x1 << 6) +#define SYSCLKDIV_2 (0x1 << 7) + +#define CLKSEL_GPT1 (0x1 << 0) + +#define EN_GPT1 (0x1 << 0) +#define EN_32KSYNC (0x1 << 2) + +#define ST_WDT2 (0x1 << 5) + +#define RESETDONE (0x1 << 0) + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* GPMC BASE */ +#define GPMC_BASE (OMAP54XX_GPMC_BASE) + +/* I2C base */ +#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) +#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) +#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) + +/* MUSB base */ +#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) + +/* OMAP4 GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x0118 +#define OMAP_GPIO_IRQSTATUS2 0x0128 +#define OMAP_GPIO_IRQENABLE2 0x012c +#define OMAP_GPIO_IRQENABLE1 0x011c +#define OMAP_GPIO_WAKE_EN 0x0120 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 +#define OMAP_GPIO_SETIRQENABLE1 0x0164 +#define OMAP_GPIO_CLEARWKUENA 0x0180 +#define OMAP_GPIO_SETWKUENA 0x0184 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + +#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h new file mode 100644 index 0000000000..c14dff0f32 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/gpio.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix@windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä <juha.yrjola@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _GPIO_OMAP5_H +#define _GPIO_OMAP5_H + +#include <asm/omap_gpio.h> + +#define OMAP54XX_GPIO1_BASE 0x4Ae10000 +#define OMAP54XX_GPIO2_BASE 0x48055000 +#define OMAP54XX_GPIO3_BASE 0x48057000 +#define OMAP54XX_GPIO4_BASE 0x48059000 +#define OMAP54XX_GPIO5_BASE 0x4805B000 +#define OMAP54XX_GPIO6_BASE 0x4805D000 + +#endif /* _GPIO_OMAP5_H */ diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h new file mode 100644 index 0000000000..68be03be58 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/i2c.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2004-2010 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP5_I2C_H_ +#define _OMAP5_I2C_H_ + +#define I2C_BUS_MAX 3 +#define I2C_DEFAULT_BASE I2C_BASE1 + +struct i2c { + unsigned short revnb_lo; /* 0x00 */ + unsigned short res1; + unsigned short revnb_hi; /* 0x04 */ + unsigned short res2[13]; + unsigned short sysc; /* 0x20 */ + unsigned short res3; + unsigned short irqstatus_raw; /* 0x24 */ + unsigned short res4; + unsigned short stat; /* 0x28 */ + unsigned short res5; + unsigned short ie; /* 0x2C */ + unsigned short res6; + unsigned short irqenable_clr; /* 0x30 */ + unsigned short res7; + unsigned short iv; /* 0x34 */ + unsigned short res8[45]; + unsigned short syss; /* 0x90 */ + unsigned short res9; + unsigned short buf; /* 0x94 */ + unsigned short res10; + unsigned short cnt; /* 0x98 */ + unsigned short res11; + unsigned short data; /* 0x9C */ + unsigned short res13; + unsigned short res14; /* 0xA0 */ + unsigned short res15; + unsigned short con; /* 0xA4 */ + unsigned short res16; + unsigned short oa; /* 0xA8 */ + unsigned short res17; + unsigned short sa; /* 0xAC */ + unsigned short res18; + unsigned short psc; /* 0xB0 */ + unsigned short res19; + unsigned short scll; /* 0xB4 */ + unsigned short res20; + unsigned short sclh; /* 0xB8 */ + unsigned short res21; + unsigned short systest; /* 0xBC */ + unsigned short res22; + unsigned short bufstat; /* 0xC0 */ + unsigned short res23; +}; + +#endif /* _OMAP5_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h new file mode 100644 index 0000000000..74439c9d9b --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +/* + * OMAP HSMMC register definitions + */ + +#define OMAP_HSMMC1_BASE 0x4809C100 +#define OMAP_HSMMC2_BASE 0x480B4100 +#define OMAP_HSMMC3_BASE 0x480AD100 + +struct hsmmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned char res2[0x14]; + unsigned int con; /* 0x2C */ + unsigned char res3[0xD4]; + unsigned int blk; /* 0x104 */ + unsigned int arg; /* 0x108 */ + unsigned int cmd; /* 0x10C */ + unsigned int rsp10; /* 0x110 */ + unsigned int rsp32; /* 0x114 */ + unsigned int rsp54; /* 0x118 */ + unsigned int rsp76; /* 0x11C */ + unsigned int data; /* 0x120 */ + unsigned int pstate; /* 0x124 */ + unsigned int hctl; /* 0x128 */ + unsigned int sysctl; /* 0x12C */ + unsigned int stat; /* 0x130 */ + unsigned int ie; /* 0x134 */ + unsigned char res4[0x8]; + unsigned int capa; /* 0x140 */ +}; + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define BCE_ENABLE (0x1 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define MSBS_MULTIBLK (0x1 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define DATI_CMDDIS (0x1 << 1) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE 512 +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) + +/* Clock Configurations and Macros */ +#define MMC_CLOCK_REFERENCE 96 /* MHz */ + +#define mmc_reg_out(addr, mask, val)\ + writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) + +int omap_mmc_init(int dev_index); + +#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h new file mode 100644 index 0000000000..b8c21853f0 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h @@ -0,0 +1,344 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated + * Richard Woodruff <r-woodruff2@ti.com> + * Aneesh V <aneesh@ti.com> + * Balaji Krishnamoorthy <balajitk@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_OMAP5_H_ +#define _MUX_OMAP5_H_ + +#include <asm/types.h> + +struct pad_conf_entry { + + u16 offset; + + u16 val; + +} __attribute__ ((__packed__)); + +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD (1 << 3) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define GPMC_AD0 0x0040 +#define GPMC_AD1 0x0042 +#define GPMC_AD2 0x0044 +#define GPMC_AD3 0x0046 +#define GPMC_AD4 0x0048 +#define GPMC_AD5 0x004A +#define GPMC_AD6 0x004C +#define GPMC_AD7 0x004E +#define GPMC_AD8 0x0050 +#define GPMC_AD9 0x0052 +#define GPMC_AD10 0x0054 +#define GPMC_AD11 0x0056 +#define GPMC_AD12 0x0058 +#define GPMC_AD13 0x005A +#define GPMC_AD14 0x005C +#define GPMC_AD15 0x005E +#define GPMC_A16 0x0060 +#define GPMC_A17 0x0062 +#define GPMC_A18 0x0064 +#define GPMC_A19 0x0066 +#define GPMC_A20 0x0068 +#define GPMC_A21 0x006A +#define GPMC_A22 0x006C +#define GPMC_A23 0x006E +#define GPMC_A24 0x0070 +#define GPMC_A25 0x0072 +#define GPMC_NCS0 0x0074 +#define GPMC_NCS1 0x0076 +#define GPMC_NCS2 0x0078 +#define GPMC_NCS3 0x007A +#define GPMC_NWP 0x007C +#define GPMC_CLK 0x007E +#define GPMC_NADV_ALE 0x0080 +#define GPMC_NOE 0x0082 +#define GPMC_NWE 0x0084 +#define GPMC_NBE0_CLE 0x0086 +#define GPMC_NBE1 0x0088 +#define GPMC_WAIT0 0x008A +#define GPMC_WAIT1 0x008C +#define C2C_DATA11 0x008E +#define C2C_DATA12 0x0090 +#define C2C_DATA13 0x0092 +#define C2C_DATA14 0x0094 +#define C2C_DATA15 0x0096 +#define HDMI_HPD 0x0098 +#define HDMI_CEC 0x009A +#define HDMI_DDC_SCL 0x009C +#define HDMI_DDC_SDA 0x009E +#define CSI21_DX0 0x00A0 +#define CSI21_DY0 0x00A2 +#define CSI21_DX1 0x00A4 +#define CSI21_DY1 0x00A6 +#define CSI21_DX2 0x00A8 +#define CSI21_DY2 0x00AA +#define CSI21_DX3 0x00AC +#define CSI21_DY3 0x00AE +#define CSI21_DX4 0x00B0 +#define CSI21_DY4 0x00B2 +#define CSI22_DX0 0x00B4 +#define CSI22_DY0 0x00B6 +#define CSI22_DX1 0x00B8 +#define CSI22_DY1 0x00BA +#define CAM_SHUTTER 0x00BC +#define CAM_STROBE 0x00BE +#define CAM_GLOBALRESET 0x00C0 +#define USBB1_ULPITLL_CLK 0x00C2 +#define USBB1_ULPITLL_STP 0x00C4 +#define USBB1_ULPITLL_DIR 0x00C6 +#define USBB1_ULPITLL_NXT 0x00C8 +#define USBB1_ULPITLL_DAT0 0x00CA +#define USBB1_ULPITLL_DAT1 0x00CC +#define USBB1_ULPITLL_DAT2 0x00CE +#define USBB1_ULPITLL_DAT3 0x00D0 +#define USBB1_ULPITLL_DAT4 0x00D2 +#define USBB1_ULPITLL_DAT5 0x00D4 +#define USBB1_ULPITLL_DAT6 0x00D6 +#define USBB1_ULPITLL_DAT7 0x00D8 +#define USBB1_HSIC_DATA 0x00DA +#define USBB1_HSIC_STROBE 0x00DC +#define USBC1_ICUSB_DP 0x00DE +#define USBC1_ICUSB_DM 0x00E0 +#define SDMMC1_CLK 0x00E2 +#define SDMMC1_CMD 0x00E4 +#define SDMMC1_DAT0 0x00E6 +#define SDMMC1_DAT1 0x00E8 +#define SDMMC1_DAT2 0x00EA +#define SDMMC1_DAT3 0x00EC +#define SDMMC1_DAT4 0x00EE +#define SDMMC1_DAT5 0x00F0 +#define SDMMC1_DAT6 0x00F2 +#define SDMMC1_DAT7 0x00F4 +#define ABE_MCBSP2_CLKX 0x00F6 +#define ABE_MCBSP2_DR 0x00F8 +#define ABE_MCBSP2_DX 0x00FA +#define ABE_MCBSP2_FSX 0x00FC +#define ABE_MCBSP1_CLKX 0x00FE +#define ABE_MCBSP1_DR 0x0100 +#define ABE_MCBSP1_DX 0x0102 +#define ABE_MCBSP1_FSX 0x0104 +#define ABE_PDM_UL_DATA 0x0106 +#define ABE_PDM_DL_DATA 0x0108 +#define ABE_PDM_FRAME 0x010A +#define ABE_PDM_LB_CLK 0x010C +#define ABE_CLKS 0x010E +#define ABE_DMIC_CLK1 0x0110 +#define ABE_DMIC_DIN1 0x0112 +#define ABE_DMIC_DIN2 0x0114 +#define ABE_DMIC_DIN3 0x0116 +#define UART2_CTS 0x0118 +#define UART2_RTS 0x011A +#define UART2_RX 0x011C +#define UART2_TX 0x011E +#define HDQ_SIO 0x0120 +#define I2C1_SCL 0x0122 +#define I2C1_SDA 0x0124 +#define I2C2_SCL 0x0126 +#define I2C2_SDA 0x0128 +#define I2C3_SCL 0x012A +#define I2C3_SDA 0x012C +#define I2C4_SCL 0x012E +#define I2C4_SDA 0x0130 +#define MCSPI1_CLK 0x0132 +#define MCSPI1_SOMI 0x0134 +#define MCSPI1_SIMO 0x0136 +#define MCSPI1_CS0 0x0138 +#define MCSPI1_CS1 0x013A +#define MCSPI1_CS2 0x013C +#define MCSPI1_CS3 0x013E +#define UART3_CTS_RCTX 0x0140 +#define UART3_RTS_SD 0x0142 +#define UART3_RX_IRRX 0x0144 +#define UART3_TX_IRTX 0x0146 +#define SDMMC5_CLK 0x0148 +#define SDMMC5_CMD 0x014A +#define SDMMC5_DAT0 0x014C +#define SDMMC5_DAT1 0x014E +#define SDMMC5_DAT2 0x0150 +#define SDMMC5_DAT3 0x0152 +#define MCSPI4_CLK 0x0154 +#define MCSPI4_SIMO 0x0156 +#define MCSPI4_SOMI 0x0158 +#define MCSPI4_CS0 0x015A +#define UART4_RX 0x015C +#define UART4_TX 0x015E +#define USBB2_ULPITLL_CLK 0x0160 +#define USBB2_ULPITLL_STP 0x0162 +#define USBB2_ULPITLL_DIR 0x0164 +#define USBB2_ULPITLL_NXT 0x0166 +#define USBB2_ULPITLL_DAT0 0x0168 +#define USBB2_ULPITLL_DAT1 0x016A +#define USBB2_ULPITLL_DAT2 0x016C +#define USBB2_ULPITLL_DAT3 0x016E +#define USBB2_ULPITLL_DAT4 0x0170 +#define USBB2_ULPITLL_DAT5 0x0172 +#define USBB2_ULPITLL_DAT6 0x0174 +#define USBB2_ULPITLL_DAT7 0x0176 +#define USBB2_HSIC_DATA 0x0178 +#define USBB2_HSIC_STROBE 0x017A +#define UNIPRO_TX0 0x017C +#define UNIPRO_TY0 0x017E +#define UNIPRO_TX1 0x0180 +#define UNIPRO_TY1 0x0182 +#define UNIPRO_TX2 0x0184 +#define UNIPRO_TY2 0x0186 +#define UNIPRO_RX0 0x0188 +#define UNIPRO_RY0 0x018A +#define UNIPRO_RX1 0x018C +#define UNIPRO_RY1 0x018E +#define UNIPRO_RX2 0x0190 +#define UNIPRO_RY2 0x0192 +#define USBA0_OTG_CE 0x0194 +#define USBA0_OTG_DP 0x0196 +#define USBA0_OTG_DM 0x0198 +#define FREF_CLK1_OUT 0x019A +#define FREF_CLK2_OUT 0x019C +#define SYS_NIRQ1 0x019E +#define SYS_NIRQ2 0x01A0 +#define SYS_BOOT0 0x01A2 +#define SYS_BOOT1 0x01A4 +#define SYS_BOOT2 0x01A6 +#define SYS_BOOT3 0x01A8 +#define SYS_BOOT4 0x01AA +#define SYS_BOOT5 0x01AC +#define DPM_EMU0 0x01AE +#define DPM_EMU1 0x01B0 +#define DPM_EMU2 0x01B2 +#define DPM_EMU3 0x01B4 +#define DPM_EMU4 0x01B6 +#define DPM_EMU5 0x01B8 +#define DPM_EMU6 0x01BA +#define DPM_EMU7 0x01BC +#define DPM_EMU8 0x01BE +#define DPM_EMU9 0x01C0 +#define DPM_EMU10 0x01C2 +#define DPM_EMU11 0x01C4 +#define DPM_EMU12 0x01C6 +#define DPM_EMU13 0x01C8 +#define DPM_EMU14 0x01CA +#define DPM_EMU15 0x01CC +#define DPM_EMU16 0x01CE +#define DPM_EMU17 0x01D0 +#define DPM_EMU18 0x01D2 +#define DPM_EMU19 0x01D4 +#define WAKEUPEVENT_0 0x01D8 +#define WAKEUPEVENT_1 0x01DC +#define WAKEUPEVENT_2 0x01E0 +#define WAKEUPEVENT_3 0x01E4 +#define WAKEUPEVENT_4 0x01E8 +#define WAKEUPEVENT_5 0x01EC +#define WAKEUPEVENT_6 0x01F0 + +#define WKUP_REVISION 0x0000 +#define WKUP_HWINFO 0x0004 +#define WKUP_SYSCONFIG 0x0010 +#define PAD0_SIM_IO 0x0040 +#define PAD1_SIM_CLK 0x0042 +#define PAD0_SIM_RESET 0x0044 +#define PAD1_SIM_CD 0x0046 +#define PAD0_SIM_PWRCTRL 0x0048 +#define PAD1_SR_SCL 0x004A +#define PAD0_SR_SDA 0x004C +#define PAD1_FREF_XTAL_IN 0x004E +#define PAD0_FREF_SLICER_IN 0x0050 +#define PAD1_FREF_CLK_IOREQ 0x0052 +#define PAD0_FREF_CLK0_OUT 0x0054 +#define PAD1_FREF_CLK3_REQ 0x0056 +#define PAD0_FREF_CLK3_OUT 0x0058 +#define PAD1_FREF_CLK4_REQ 0x005A +#define PAD0_FREF_CLK4_OUT 0x005C +#define PAD1_SYS_32K 0x005E +#define PAD0_SYS_NRESPWRON 0x0060 +#define PAD1_SYS_NRESWARM 0x0062 +#define PAD0_SYS_PWR_REQ 0x0064 +#define PAD1_SYS_PWRON_RESET 0x0066 +#define PAD0_SYS_BOOT6 0x0068 +#define PAD1_SYS_BOOT7 0x006A +#define PAD0_JTAG_NTRST 0x006C +#define PAD1_JTAG_TCK 0x006D +#define PAD0_JTAG_RTCK 0x0070 +#define PAD1_JTAG_TMS_TMSC 0x0072 +#define PAD0_JTAG_TDI 0x0074 +#define PAD1_JTAG_TDO 0x0076 +#define PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_SPARE_RW 0x0614 +#define CONTROL_SPARE_R 0x0618 +#define CONTROL_SPARE_R_C0 0x061C + +#endif /* _MUX_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h new file mode 100644 index 0000000000..d811d6ec23 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -0,0 +1,223 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Authors: + * Aneesh V <aneesh@ti.com> + * Sricharan R <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP5_H_ +#define _OMAP5_H_ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP54XX_L4_CORE_BASE 0x4A000000 +#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 +#define OMAP54XX_L4_PER_BASE 0x48000000 + +#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 +#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000 +#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START +#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END + +/* CONTROL */ +#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) +#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800) +#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800) + +/* LPDDR2 IO regs. To be verified */ +#define LPDDR2_IO_REGS_BASE 0x4A100638 + +/* CONTROL_ID_CODE */ +#define CONTROL_ID_CODE (CTRL_BASE + 0x204) + +/* To be verified */ +#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F + +/* STD_FUSE_PROD_ID_1 */ +#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) +#define PROD_ID_1_SILICON_TYPE_SHIFT 16 +#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16) + +/* UART */ +#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) +#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) +#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) + +/* General Purpose Timers */ +#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) +#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) +#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) + +/* Watchdog Timer2 - MPU watchdog */ +#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000) + +/* GPMC */ +#define OMAP54XX_GPMC_BASE 0x50000000 + +/* SYSTEM CONTROL MODULE */ +#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000 + +/* + * Hardware Register Details + */ + +/* Watchdog Timer */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* GP Timer */ +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4AE06000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 + +/* Control Module */ +#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) +#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f +#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 +#define CONTROL_EFUSE_2_OVERRIDE 0x00084000 + +/* LPDDR2 IO regs */ +#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C +#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E +#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C +#define LPDDR2IO_GR10_WD_MASK (3 << 17) +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 + +/* CONTROL_EFUSE_2 */ +#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 + +#define MMC1_PWRDNZ (1 << 26) +#define MMC1_PBIASLITE_PWRDNZ (1 << 22) +#define MMC1_PBIASLITE_VMODE (1 << 21) + +#ifndef __ASSEMBLY__ + +struct s32ktimer { + unsigned char res[0x10]; + unsigned int s32k_cr; /* 0x10 */ +}; + +struct omap4_sys_ctrl_regs { + unsigned int pad1[129]; + unsigned int control_id_code; /* 0x4A002204 */ + unsigned int pad11[22]; + unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */ + unsigned int pad2[47]; + unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */ + unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ + unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ + unsigned int pad3[260277]; + unsigned int control_pbiaslite; /* 0x4A100600 */ + unsigned int pad4[63]; + unsigned int control_efuse_1; /* 0x4A100700 */ + unsigned int control_efuse_2; /* 0x4A100704 */ +}; + +struct control_lpddr2io_regs { + unsigned int control_lpddr2io1_0; + unsigned int control_lpddr2io1_1; + unsigned int control_lpddr2io1_2; + unsigned int control_lpddr2io1_3; + unsigned int control_lpddr2io2_0; + unsigned int control_lpddr2io2_1; + unsigned int control_lpddr2io2_2; + unsigned int control_lpddr2io2_3; +}; +#endif /* __ASSEMBLY__ */ + +/* + * Non-secure SRAM Addresses + * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE + * at 0x40304000(EMU base) so that our code works for both EMU and GP + */ +#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_ROM_VECT_BASE 0x4031F000 +/* Temporary SRAM stack used while low level init is done */ +#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END + +#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +/* + * SRAM scratch space entries + */ +#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR +#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) +#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) +#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) + +/* Silicon revisions */ +#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF +#define OMAP4430_ES1_0 0x44300100 +#define OMAP4430_ES2_0 0x44300200 +#define OMAP4430_ES2_1 0x44300210 +#define OMAP4430_ES2_2 0x44300220 +#define OMAP4430_ES2_3 0x44300230 +#define OMAP4460_ES1_0 0x44600100 +#define OMAP4460_ES1_1 0x44600110 + +/* ROM code defines */ +/* Boot device */ +#define BOOT_DEVICE_MASK 0xFF +#define BOOT_DEVICE_OFFSET 0x8 +#define DEV_DESC_PTR_OFFSET 0x4 +#define DEV_DATA_PTR_OFFSET 0x18 +#define BOOT_MODE_OFFSET 0x8 +#define RESET_REASON_OFFSET 0x9 +#define CH_FLAGS_OFFSET 0xA + +#define CH_FLAGS_CHSETTINGS (0x1 << 0) +#define CH_FLAGS_CHRAM (0x1 << 1) +#define CH_FLAGS_CHFLASH (0x1 << 2) +#define CH_FLAGS_CHMMCSD (0x1 << 3) + +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + char *boot_message; + unsigned int mem_boot_descriptor; + unsigned char omap_bootdevice; + unsigned char reset_reason; + unsigned char ch_flags; +}; +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h new file mode 100644 index 0000000000..c31e18ca22 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include <asm/arch/omap.h> +#include <asm/io.h> +#include <asm/arch/clocks.h> +#include <asm/omap_common.h> +#include <asm/arch/mux_omap5.h> +#include <asm/arch/clocks.h> + +struct omap_sysinfo { + char *board_string; +}; +extern const struct omap_sysinfo sysinfo; + +void gpmc_init(void); +void watchdog_init(void); +u32 get_device_type(void); +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs_essential(void); +void set_muxconf_regs_non_essential(void); +void sr32(void *, u32, u32, u32); +u32 wait_on_value(u32, u32, void *, u32); +void sdelay(unsigned long); +void omap_rev_string(char *omap_rev_string); +void setup_clocks_for_console(void); +void prcm_init(void); +void bypass_dpll(u32 *const base); +void freq_update_core(void); +u32 get_sys_clk_freq(void); +u32 omap5_ddr_clk(void); +void cancel_out(u32 *num, u32 *den, u32 den_limit); +void sdram_init(void); +u32 omap_sdram_size(void); +u32 cortex_rev(void); +void init_omap_revision(void); +void do_io_settings(void); + +/* + * This is used to verify if the configuration header + * was executed by Romcode prior to control of transfer + * to the bootloader. SPL is responsible for saving and + * passing this to the u-boot. + */ +extern struct omap_boot_parameters boot_params; + +static inline u32 running_from_sdram(void) +{ + u32 pc; + asm volatile ("mov %0, pc" : "=r" (pc)); + return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) && + (pc < OMAP54XX_DRAM_ADDR_SPACE_END)); +} + +static inline u8 uboot_loaded_by_spl(void) +{ + /* + * u-boot can be running from sdram either because of configuration + * Header or by SPL. If because of CH, then the romcode sets the + * CHSETTINGS executed bit to true in the boot parameter structure that + * it passes to the bootloader.This parameter is stored in the ch_flags + * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a + * mandatory section if CH is present. + */ + if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + return 0; + else + return running_from_sdram(); +} +/* + * The basic hardware init of OMAP(s_init()) can happen in 4 + * different contexts: + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. Non-XIP U-Boot loaded to SDRAM by SPL + * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * + * This function finds this context. + * Defining as inline may help in compiling out unused functions in SPL + */ +static inline u32 omap_hw_init_context(void) +{ +#ifdef CONFIG_SPL_BUILD + return OMAP_INIT_CONTEXT_SPL; +#else + if (uboot_loaded_by_spl()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; + else if (running_from_sdram()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; + else + return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; +#endif +} + +static inline u32 omap_revision(void) +{ + extern u32 *const omap5_revision; + return *omap5_revision; +} + +#endif diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index 109fdc06aa..8527c68c81 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -109,7 +109,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */ #define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */ #define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */ #define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */ #define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */ @@ -126,7 +126,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */ #define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */ #define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #define DCSR(x) (0x40000000 | ((x) << 2)) @@ -134,7 +134,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ -#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ @@ -315,117 +315,6 @@ typedef void (*ExcpHndlr) (void) ; /******************************************************************************/ /* - * UARTs - */ -/* Full Function UART (FFUART) */ -#define FFUART FFRBR -#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */ -#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */ -#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */ -#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */ -#define FFFCR 0x40100008 /* FIFO Control Register (write only) */ -#define FFLCR 0x4010000C /* Line Control Register (read/write) */ -#define FFMCR 0x40100010 /* Modem Control Register (read/write) */ -#define FFLSR 0x40100014 /* Line Status Register (read only) */ -#define FFMSR 0x40100018 /* Modem Status Register (read only) */ -#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */ -#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */ -#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Bluetooth UART (BTUART) */ -#define BTUART BTRBR -#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */ -#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */ -#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */ -#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */ -#define BTFCR 0x40200008 /* FIFO Control Register (write only) */ -#define BTLCR 0x4020000C /* Line Control Register (read/write) */ -#define BTMCR 0x40200010 /* Modem Control Register (read/write) */ -#define BTLSR 0x40200014 /* Line Status Register (read only) */ -#define BTMSR 0x40200018 /* Modem Status Register (read only) */ -#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */ -#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */ -#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Standard UART (STUART) */ -#define STUART STRBR -#define STRBR 0x40700000 /* Receive Buffer Register (read only) */ -#define STTHR 0x40700000 /* Transmit Holding Register (write only) */ -#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */ -#define STIIR 0x40700008 /* Interrupt ID Register (read only) */ -#define STFCR 0x40700008 /* FIFO Control Register (write only) */ -#define STLCR 0x4070000C /* Line Control Register (read/write) */ -#define STMCR 0x40700010 /* Modem Control Register (read/write) */ -#define STLSR 0x40700014 /* Line Status Register (read only) */ -#define STMSR 0x40700018 /* Reserved */ -#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */ -#define STISR 0x40700020 /* Infrared Selection Register (read/write) */ -#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) /* */ -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -/******************************************************************************/ -/* * IrSR (Infrared Selection Register) */ #define IrSR_OFFSET 0x20 @@ -549,7 +438,7 @@ typedef void (*ExcpHndlr) (void) ; /* * USB Device Controller */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define UDCCR 0x40600000 /* UDC Control Register */ #define UDCCR_UDE (1 << 0) /* UDC enable */ @@ -908,9 +797,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) #define UDC_BCR_MASK (0x3ff) -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) /******************************************************************************/ /* @@ -981,7 +870,7 @@ typedef void (*ExcpHndlr) (void) ; #define UP2OCR_CPVPE (1<<1) #define UP2OCR_CPVEN (1<<0) -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /******************************************************************************/ /* @@ -1034,7 +923,7 @@ typedef void (*ExcpHndlr) (void) ; #define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */ #define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */ #define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */ #define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */ @@ -1062,7 +951,7 @@ typedef void (*ExcpHndlr) (void) ; #define OMCR10 0x40A000D8 /* OS Match Control Register 10 */ #define OMCR11 0x40A000DC /* OS Match Control Register 11 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #define OSSR_M4 (1 << 4) /* Match status channel 4 */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ @@ -1163,7 +1052,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_PXA27X) +#if !defined(CONFIG_CPU_PXA27X) #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #endif #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ @@ -1182,7 +1071,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ #define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ #endif @@ -1198,7 +1087,7 @@ typedef void (*ExcpHndlr) (void) ; #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ -#if !defined(CONFIG_PXA27X) +#if !defined(CONFIG_CPU_PXA27X) #define CCCR_L09 (0x1F) #define CCCR_L27 (0x1) #define CCCR_L32 (0x2) @@ -1231,7 +1120,7 @@ typedef void (*ExcpHndlr) (void) ; #define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */ #define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */ #define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */ #define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */ @@ -1239,7 +1128,7 @@ typedef void (*ExcpHndlr) (void) ; #define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */ #define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */ #define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /* * Interrupt Controller @@ -1251,14 +1140,14 @@ typedef void (*ExcpHndlr) (void) ; #define ICPR 0x40D00010 /* Interrupt Controller Pending Register */ #define ICCR 0x40D00014 /* Interrupt Controller Control Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */ #define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */ #define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */ #define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */ #define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */ #define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /******************************************************************************/ /* @@ -1299,7 +1188,7 @@ typedef void (*ExcpHndlr) (void) ; #define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ #define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ #define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ #define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ @@ -1309,7 +1198,7 @@ typedef void (*ExcpHndlr) (void) ; #define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ #define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ #define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #ifdef CONFIG_CPU_MONAHANS #define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ @@ -1355,7 +1244,7 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) #define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) #define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) #define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) @@ -2234,7 +2123,7 @@ typedef void (*ExcpHndlr) (void) ; #define LCCR0_PDD_S 12 #define LCCR0_BM (1 << 20) /* Branch mask */ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ @@ -2360,7 +2249,7 @@ typedef void (*ExcpHndlr) (void) ; #define LCSR1_IU6 (1 << 29) #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define LDCMD_SOFINT (1 << 22) #define LDCMD_EOFINT (1 << 21) #endif @@ -2591,7 +2480,7 @@ typedef void (*ExcpHndlr) (void) ; #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ @@ -2605,7 +2494,7 @@ typedef void (*ExcpHndlr) (void) ; #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ /* LCD registers */ #define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ @@ -2739,6 +2628,6 @@ typedef void (*ExcpHndlr) (void) ; #define OSCR4 0x40A00040 /* OS Timer Counter Register */ #define OMCR4 0x40A000C0 /* */ -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ #endif /* _PXA_REGS_H_ */ diff --git a/arch/arm/cpu/armv7/omap4/sys_info.c b/arch/arm/include/asm/arch-pxa/pxa.h index b9e57659f0..49c6552c57 100644 --- a/arch/arm/cpu/armv7/omap4/sys_info.c +++ b/arch/arm/include/asm/arch-pxa/pxa.h @@ -1,10 +1,7 @@ /* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> + * PXA common functions * - * Author : - * Aneesh V <aneesh@ti.com> - * Steve Sakoman <steve@sakoman.com> + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,32 +19,11 @@ * MA 02111-1307 USA */ -#include <common.h> -#include <asm/arch/sys_proto.h> +#ifndef __PXA_H__ +#define __PXA_H__ -/* - * get_device_type(): tell if GP/HS/EMU/TST - */ -u32 get_device_type(void) -{ - return 0; -} - -/* - * get_board_rev() - get board revision - */ -u32 get_board_rev(void) -{ - return 0x20; -} - -/* - * Print CPU information - */ -int print_cpuinfo(void) -{ - - puts("CPU : OMAP4430\n"); +int cpu_is_pxa25x(void); +int cpu_is_pxa27x(void); +void pxa2xx_dram_init(void); - return 0; -} +#endif /* __PXA_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-uart.h b/arch/arm/include/asm/arch-pxa/regs-uart.h new file mode 100644 index 0000000000..355e892457 --- /dev/null +++ b/arch/arm/include/asm/arch-pxa/regs-uart.h @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __REGS_UART_H__ +#define __REGS_UART_H__ + +#define FFUART_BASE 0x40100000 +#define BTUART_BASE 0x40200000 +#define STUART_BASE 0x40700000 +#define HWUART_BASE 0x41600000 + +struct pxa_uart_regs { + union { + uint32_t thr; + uint32_t rbr; + uint32_t dll; + }; + union { + uint32_t ier; + uint32_t dlh; + }; + union { + uint32_t fcr; + uint32_t iir; + }; + uint32_t lcr; + uint32_t mcr; + uint32_t lsr; + uint32_t msr; + uint32_t spr; + uint32_t isr; +}; + +#define IER_DMAE (1 << 7) +#define IER_UUE (1 << 6) +#define IER_NRZE (1 << 5) +#define IER_RTIOE (1 << 4) +#define IER_MIE (1 << 3) +#define IER_RLSE (1 << 2) +#define IER_TIE (1 << 1) +#define IER_RAVIE (1 << 0) + +#define IIR_FIFOES1 (1 << 7) +#define IIR_FIFOES0 (1 << 6) +#define IIR_TOD (1 << 3) +#define IIR_IID2 (1 << 2) +#define IIR_IID1 (1 << 1) +#define IIR_IP (1 << 0) + +#define FCR_ITL2 (1 << 7) +#define FCR_ITL1 (1 << 6) +#define FCR_RESETTF (1 << 2) +#define FCR_RESETRF (1 << 1) +#define FCR_TRFIFOE (1 << 0) +#define FCR_ITL_1 0 +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) +#define LCR_SB (1 << 6) +#define LCR_STKYP (1 << 5) +#define LCR_EPS (1 << 4) +#define LCR_PEN (1 << 3) +#define LCR_STB (1 << 2) +#define LCR_WLS1 (1 << 1) +#define LCR_WLS0 (1 << 0) + +#define LSR_FIFOE (1 << 7) +#define LSR_TEMT (1 << 6) +#define LSR_TDRQ (1 << 5) +#define LSR_BI (1 << 4) +#define LSR_FE (1 << 3) +#define LSR_PE (1 << 2) +#define LSR_OE (1 << 1) +#define LSR_DR (1 << 0) + +#define MCR_LOOP (1 << 4) +#define MCR_OUT2 (1 << 3) +#define MCR_OUT1 (1 << 2) +#define MCR_RTS (1 << 1) +#define MCR_DTR (1 << 0) + +#define MSR_DCD (1 << 7) +#define MSR_RI (1 << 6) +#define MSR_DSR (1 << 5) +#define MSR_CTS (1 << 4) +#define MSR_DDCD (1 << 3) +#define MSR_TERI (1 << 2) +#define MSR_DDSR (1 << 1) +#define MSR_DCTS (1 << 0) + +#endif /* __REGS_UART_H__ */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 9adc563788..ad9a875de5 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -31,6 +31,9 @@ #define MIDR_CORTEX_A9_R1P3 0x411FC093 #define MIDR_CORTEX_A9_R2P10 0x412FC09A +/* Cortex-A15 revisions */ +#define MIDR_CORTEX_A15_R0P0 0x410FC0F0 + /* CCSIDR */ #define CCSIDR_LINE_SIZE_OFFSET 0 #define CCSIDR_LINE_SIZE_MASK 0x7 diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 501ce0e680..5bbb0a0464 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h new file mode 100644 index 0000000000..e5c7d2cabe --- /dev/null +++ b/arch/arm/include/asm/emif.h @@ -0,0 +1,1035 @@ +/* + * OMAP44xx EMIF header + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Aneesh V <aneesh@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ +#include <asm/types.h> +#include <common.h> + +/* Base address */ +#define EMIF1_BASE 0x4c000000 +#define EMIF2_BASE 0x4d000000 + +/* Registers shifts and masks */ + +/* EMIF_MOD_ID_REV */ +#define EMIF_REG_SCHEME_SHIFT 30 +#define EMIF_REG_SCHEME_MASK (0x3 << 30) +#define EMIF_REG_MODULE_ID_SHIFT 16 +#define EMIF_REG_MODULE_ID_MASK (0xfff << 16) +#define EMIF_REG_RTL_VERSION_SHIFT 11 +#define EMIF_REG_RTL_VERSION_MASK (0x1f << 11) +#define EMIF_REG_MAJOR_REVISION_SHIFT 8 +#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8) +#define EMIF_REG_MINOR_REVISION_SHIFT 0 +#define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0) + +/* STATUS */ +#define EMIF_REG_BE_SHIFT 31 +#define EMIF_REG_BE_MASK (1 << 31) +#define EMIF_REG_DUAL_CLK_MODE_SHIFT 30 +#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) +#define EMIF_REG_FAST_INIT_SHIFT 29 +#define EMIF_REG_FAST_INIT_MASK (1 << 29) +#define EMIF_REG_PHY_DLL_READY_SHIFT 2 +#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2) + +/* SDRAM_CONFIG */ +#define EMIF_REG_SDRAM_TYPE_SHIFT 29 +#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29) +#define EMIF_REG_IBANK_POS_SHIFT 27 +#define EMIF_REG_IBANK_POS_MASK (0x3 << 27) +#define EMIF_REG_DDR_TERM_SHIFT 24 +#define EMIF_REG_DDR_TERM_MASK (0x7 << 24) +#define EMIF_REG_DDR2_DDQS_SHIFT 23 +#define EMIF_REG_DDR2_DDQS_MASK (1 << 23) +#define EMIF_REG_DYN_ODT_SHIFT 21 +#define EMIF_REG_DYN_ODT_MASK (0x3 << 21) +#define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20 +#define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20) +#define EMIF_REG_SDRAM_DRIVE_SHIFT 18 +#define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18) +#define EMIF_REG_CWL_SHIFT 16 +#define EMIF_REG_CWL_MASK (0x3 << 16) +#define EMIF_REG_NARROW_MODE_SHIFT 14 +#define EMIF_REG_NARROW_MODE_MASK (0x3 << 14) +#define EMIF_REG_CL_SHIFT 10 +#define EMIF_REG_CL_MASK (0xf << 10) +#define EMIF_REG_ROWSIZE_SHIFT 7 +#define EMIF_REG_ROWSIZE_MASK (0x7 << 7) +#define EMIF_REG_IBANK_SHIFT 4 +#define EMIF_REG_IBANK_MASK (0x7 << 4) +#define EMIF_REG_EBANK_SHIFT 3 +#define EMIF_REG_EBANK_MASK (1 << 3) +#define EMIF_REG_PAGESIZE_SHIFT 0 +#define EMIF_REG_PAGESIZE_MASK (0x7 << 0) + +/* SDRAM_CONFIG_2 */ +#define EMIF_REG_CS1NVMEN_SHIFT 30 +#define EMIF_REG_CS1NVMEN_MASK (1 << 30) +#define EMIF_REG_EBANK_POS_SHIFT 27 +#define EMIF_REG_EBANK_POS_MASK (1 << 27) +#define EMIF_REG_RDBNUM_SHIFT 4 +#define EMIF_REG_RDBNUM_MASK (0x3 << 4) +#define EMIF_REG_RDBSIZE_SHIFT 0 +#define EMIF_REG_RDBSIZE_MASK (0x7 << 0) + +/* SDRAM_REF_CTRL */ +#define EMIF_REG_INITREF_DIS_SHIFT 31 +#define EMIF_REG_INITREF_DIS_MASK (1 << 31) +#define EMIF_REG_SRT_SHIFT 29 +#define EMIF_REG_SRT_MASK (1 << 29) +#define EMIF_REG_ASR_SHIFT 28 +#define EMIF_REG_ASR_MASK (1 << 28) +#define EMIF_REG_PASR_SHIFT 24 +#define EMIF_REG_PASR_MASK (0x7 << 24) +#define EMIF_REG_REFRESH_RATE_SHIFT 0 +#define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0) + +/* SDRAM_REF_CTRL_SHDW */ +#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0 +#define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) + +/* SDRAM_TIM_1 */ +#define EMIF_REG_T_RP_SHIFT 25 +#define EMIF_REG_T_RP_MASK (0xf << 25) +#define EMIF_REG_T_RCD_SHIFT 21 +#define EMIF_REG_T_RCD_MASK (0xf << 21) +#define EMIF_REG_T_WR_SHIFT 17 +#define EMIF_REG_T_WR_MASK (0xf << 17) +#define EMIF_REG_T_RAS_SHIFT 12 +#define EMIF_REG_T_RAS_MASK (0x1f << 12) +#define EMIF_REG_T_RC_SHIFT 6 +#define EMIF_REG_T_RC_MASK (0x3f << 6) +#define EMIF_REG_T_RRD_SHIFT 3 +#define EMIF_REG_T_RRD_MASK (0x7 << 3) +#define EMIF_REG_T_WTR_SHIFT 0 +#define EMIF_REG_T_WTR_MASK (0x7 << 0) + +/* SDRAM_TIM_1_SHDW */ +#define EMIF_REG_T_RP_SHDW_SHIFT 25 +#define EMIF_REG_T_RP_SHDW_MASK (0xf << 25) +#define EMIF_REG_T_RCD_SHDW_SHIFT 21 +#define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21) +#define EMIF_REG_T_WR_SHDW_SHIFT 17 +#define EMIF_REG_T_WR_SHDW_MASK (0xf << 17) +#define EMIF_REG_T_RAS_SHDW_SHIFT 12 +#define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12) +#define EMIF_REG_T_RC_SHDW_SHIFT 6 +#define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6) +#define EMIF_REG_T_RRD_SHDW_SHIFT 3 +#define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3) +#define EMIF_REG_T_WTR_SHDW_SHIFT 0 +#define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_2 */ +#define EMIF_REG_T_XP_SHIFT 28 +#define EMIF_REG_T_XP_MASK (0x7 << 28) +#define EMIF_REG_T_ODT_SHIFT 25 +#define EMIF_REG_T_ODT_MASK (0x7 << 25) +#define EMIF_REG_T_XSNR_SHIFT 16 +#define EMIF_REG_T_XSNR_MASK (0x1ff << 16) +#define EMIF_REG_T_XSRD_SHIFT 6 +#define EMIF_REG_T_XSRD_MASK (0x3ff << 6) +#define EMIF_REG_T_RTP_SHIFT 3 +#define EMIF_REG_T_RTP_MASK (0x7 << 3) +#define EMIF_REG_T_CKE_SHIFT 0 +#define EMIF_REG_T_CKE_MASK (0x7 << 0) + +/* SDRAM_TIM_2_SHDW */ +#define EMIF_REG_T_XP_SHDW_SHIFT 28 +#define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28) +#define EMIF_REG_T_ODT_SHDW_SHIFT 25 +#define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25) +#define EMIF_REG_T_XSNR_SHDW_SHIFT 16 +#define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16) +#define EMIF_REG_T_XSRD_SHDW_SHIFT 6 +#define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6) +#define EMIF_REG_T_RTP_SHDW_SHIFT 3 +#define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3) +#define EMIF_REG_T_CKE_SHDW_SHIFT 0 +#define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_3 */ +#define EMIF_REG_T_CKESR_SHIFT 21 +#define EMIF_REG_T_CKESR_MASK (0x7 << 21) +#define EMIF_REG_ZQ_ZQCS_SHIFT 15 +#define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15) +#define EMIF_REG_T_TDQSCKMAX_SHIFT 13 +#define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13) +#define EMIF_REG_T_RFC_SHIFT 4 +#define EMIF_REG_T_RFC_MASK (0x1ff << 4) +#define EMIF_REG_T_RAS_MAX_SHIFT 0 +#define EMIF_REG_T_RAS_MAX_MASK (0xf << 0) + +/* SDRAM_TIM_3_SHDW */ +#define EMIF_REG_T_CKESR_SHDW_SHIFT 21 +#define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21) +#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15 +#define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) +#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13 +#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) +#define EMIF_REG_T_RFC_SHDW_SHIFT 4 +#define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4) +#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0 +#define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) + +/* LPDDR2_NVM_TIM */ +#define EMIF_REG_NVM_T_XP_SHIFT 28 +#define EMIF_REG_NVM_T_XP_MASK (0x7 << 28) +#define EMIF_REG_NVM_T_WTR_SHIFT 24 +#define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24) +#define EMIF_REG_NVM_T_RP_SHIFT 20 +#define EMIF_REG_NVM_T_RP_MASK (0xf << 20) +#define EMIF_REG_NVM_T_WRA_SHIFT 16 +#define EMIF_REG_NVM_T_WRA_MASK (0xf << 16) +#define EMIF_REG_NVM_T_RRD_SHIFT 8 +#define EMIF_REG_NVM_T_RRD_MASK (0xff << 8) +#define EMIF_REG_NVM_T_RCDMIN_SHIFT 0 +#define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0) + +/* LPDDR2_NVM_TIM_SHDW */ +#define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28 +#define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) +#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24 +#define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) +#define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20 +#define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20) +#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16 +#define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) +#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8 +#define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) +#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 +#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) + +/* PWR_MGMT_CTRL */ +#define EMIF_REG_IDLEMODE_SHIFT 30 +#define EMIF_REG_IDLEMODE_MASK (0x3 << 30) +#define EMIF_REG_PD_TIM_SHIFT 12 +#define EMIF_REG_PD_TIM_MASK (0xf << 12) +#define EMIF_REG_DPD_EN_SHIFT 11 +#define EMIF_REG_DPD_EN_MASK (1 << 11) +#define EMIF_REG_LP_MODE_SHIFT 8 +#define EMIF_REG_LP_MODE_MASK (0x7 << 8) +#define EMIF_REG_SR_TIM_SHIFT 4 +#define EMIF_REG_SR_TIM_MASK (0xf << 4) +#define EMIF_REG_CS_TIM_SHIFT 0 +#define EMIF_REG_CS_TIM_MASK (0xf << 0) + +/* PWR_MGMT_CTRL_SHDW */ +#define EMIF_REG_PD_TIM_SHDW_SHIFT 8 +#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 8) +#define EMIF_REG_SR_TIM_SHDW_SHIFT 4 +#define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4) +#define EMIF_REG_CS_TIM_SHDW_SHIFT 0 +#define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0) + +/* LPDDR2_MODE_REG_DATA */ +#define EMIF_REG_VALUE_0_SHIFT 0 +#define EMIF_REG_VALUE_0_MASK (0x7f << 0) + +/* LPDDR2_MODE_REG_CFG */ +#define EMIF_REG_CS_SHIFT 31 +#define EMIF_REG_CS_MASK (1 << 31) +#define EMIF_REG_REFRESH_EN_SHIFT 30 +#define EMIF_REG_REFRESH_EN_MASK (1 << 30) +#define EMIF_REG_ADDRESS_SHIFT 0 +#define EMIF_REG_ADDRESS_MASK (0xff << 0) + +/* OCP_CONFIG */ +#define EMIF_REG_SYS_THRESH_MAX_SHIFT 24 +#define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24) +#define EMIF_REG_MPU_THRESH_MAX_SHIFT 20 +#define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20) +#define EMIF_REG_LL_THRESH_MAX_SHIFT 16 +#define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16) +#define EMIF_REG_PR_OLD_COUNT_SHIFT 0 +#define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0) + +/* OCP_CFG_VAL_1 */ +#define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30 +#define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) +#define EMIF_REG_LL_BUS_WIDTH_SHIFT 28 +#define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28) +#define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8 +#define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8) +#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0 +#define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) + +/* OCP_CFG_VAL_2 */ +#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16 +#define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) +#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8 +#define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) +#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0 +#define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) + +/* IODFT_TLGC */ +#define EMIF_REG_TLEC_SHIFT 16 +#define EMIF_REG_TLEC_MASK (0xffff << 16) +#define EMIF_REG_MT_SHIFT 14 +#define EMIF_REG_MT_MASK (1 << 14) +#define EMIF_REG_ACT_CAP_EN_SHIFT 13 +#define EMIF_REG_ACT_CAP_EN_MASK (1 << 13) +#define EMIF_REG_OPG_LD_SHIFT 12 +#define EMIF_REG_OPG_LD_MASK (1 << 12) +#define EMIF_REG_RESET_PHY_SHIFT 10 +#define EMIF_REG_RESET_PHY_MASK (1 << 10) +#define EMIF_REG_MMS_SHIFT 8 +#define EMIF_REG_MMS_MASK (1 << 8) +#define EMIF_REG_MC_SHIFT 4 +#define EMIF_REG_MC_MASK (0x3 << 4) +#define EMIF_REG_PC_SHIFT 1 +#define EMIF_REG_PC_MASK (0x7 << 1) +#define EMIF_REG_TM_SHIFT 0 +#define EMIF_REG_TM_MASK (1 << 0) + +/* IODFT_CTRL_MISR_RSLT */ +#define EMIF_REG_DQM_TLMR_SHIFT 16 +#define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16) +#define EMIF_REG_CTL_TLMR_SHIFT 0 +#define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0) + +/* IODFT_ADDR_MISR_RSLT */ +#define EMIF_REG_ADDR_TLMR_SHIFT 0 +#define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0) + +/* IODFT_DATA_MISR_RSLT_1 */ +#define EMIF_REG_DATA_TLMR_31_0_SHIFT 0 +#define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_2 */ +#define EMIF_REG_DATA_TLMR_63_32_SHIFT 0 +#define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_3 */ +#define EMIF_REG_DATA_TLMR_66_64_SHIFT 0 +#define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0) + +/* PERF_CNT_1 */ +#define EMIF_REG_COUNTER1_SHIFT 0 +#define EMIF_REG_COUNTER1_MASK (0xffffffff << 0) + +/* PERF_CNT_2 */ +#define EMIF_REG_COUNTER2_SHIFT 0 +#define EMIF_REG_COUNTER2_MASK (0xffffffff << 0) + +/* PERF_CNT_CFG */ +#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31 +#define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31) +#define EMIF_REG_CNTR2_REGION_EN_SHIFT 30 +#define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30) +#define EMIF_REG_CNTR2_CFG_SHIFT 16 +#define EMIF_REG_CNTR2_CFG_MASK (0xf << 16) +#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15 +#define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15) +#define EMIF_REG_CNTR1_REGION_EN_SHIFT 14 +#define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14) +#define EMIF_REG_CNTR1_CFG_SHIFT 0 +#define EMIF_REG_CNTR1_CFG_MASK (0xf << 0) + +/* PERF_CNT_SEL */ +#define EMIF_REG_MCONNID2_SHIFT 24 +#define EMIF_REG_MCONNID2_MASK (0xff << 24) +#define EMIF_REG_REGION_SEL2_SHIFT 16 +#define EMIF_REG_REGION_SEL2_MASK (0x3 << 16) +#define EMIF_REG_MCONNID1_SHIFT 8 +#define EMIF_REG_MCONNID1_MASK (0xff << 8) +#define EMIF_REG_REGION_SEL1_SHIFT 0 +#define EMIF_REG_REGION_SEL1_MASK (0x3 << 0) + +/* PERF_CNT_TIM */ +#define EMIF_REG_TOTAL_TIME_SHIFT 0 +#define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0) + +/* READ_IDLE_CTRL */ +#define EMIF_REG_READ_IDLE_LEN_SHIFT 16 +#define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16) +#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0 +#define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) + +/* READ_IDLE_CTRL_SHDW */ +#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16 +#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) +#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 +#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) + +/* IRQ_EOI */ +#define EMIF_REG_EOI_SHIFT 0 +#define EMIF_REG_EOI_MASK (1 << 0) + +/* IRQSTATUS_RAW_SYS */ +#define EMIF_REG_DNV_SYS_SHIFT 2 +#define EMIF_REG_DNV_SYS_MASK (1 << 2) +#define EMIF_REG_TA_SYS_SHIFT 1 +#define EMIF_REG_TA_SYS_MASK (1 << 1) +#define EMIF_REG_ERR_SYS_SHIFT 0 +#define EMIF_REG_ERR_SYS_MASK (1 << 0) + +/* IRQSTATUS_RAW_LL */ +#define EMIF_REG_DNV_LL_SHIFT 2 +#define EMIF_REG_DNV_LL_MASK (1 << 2) +#define EMIF_REG_TA_LL_SHIFT 1 +#define EMIF_REG_TA_LL_MASK (1 << 1) +#define EMIF_REG_ERR_LL_SHIFT 0 +#define EMIF_REG_ERR_LL_MASK (1 << 0) + +/* IRQSTATUS_SYS */ + +/* IRQSTATUS_LL */ + +/* IRQENABLE_SET_SYS */ +#define EMIF_REG_EN_DNV_SYS_SHIFT 2 +#define EMIF_REG_EN_DNV_SYS_MASK (1 << 2) +#define EMIF_REG_EN_TA_SYS_SHIFT 1 +#define EMIF_REG_EN_TA_SYS_MASK (1 << 1) +#define EMIF_REG_EN_ERR_SYS_SHIFT 0 +#define EMIF_REG_EN_ERR_SYS_MASK (1 << 0) + +/* IRQENABLE_SET_LL */ +#define EMIF_REG_EN_DNV_LL_SHIFT 2 +#define EMIF_REG_EN_DNV_LL_MASK (1 << 2) +#define EMIF_REG_EN_TA_LL_SHIFT 1 +#define EMIF_REG_EN_TA_LL_MASK (1 << 1) +#define EMIF_REG_EN_ERR_LL_SHIFT 0 +#define EMIF_REG_EN_ERR_LL_MASK (1 << 0) + +/* IRQENABLE_CLR_SYS */ + +/* IRQENABLE_CLR_LL */ + +/* ZQ_CONFIG */ +#define EMIF_REG_ZQ_CS1EN_SHIFT 31 +#define EMIF_REG_ZQ_CS1EN_MASK (1 << 31) +#define EMIF_REG_ZQ_CS0EN_SHIFT 30 +#define EMIF_REG_ZQ_CS0EN_MASK (1 << 30) +#define EMIF_REG_ZQ_DUALCALEN_SHIFT 29 +#define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29) +#define EMIF_REG_ZQ_SFEXITEN_SHIFT 28 +#define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28) +#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18 +#define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) +#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16 +#define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) +#define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0 +#define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) + +/* TEMP_ALERT_CONFIG */ +#define EMIF_REG_TA_CS1EN_SHIFT 31 +#define EMIF_REG_TA_CS1EN_MASK (1 << 31) +#define EMIF_REG_TA_CS0EN_SHIFT 30 +#define EMIF_REG_TA_CS0EN_MASK (1 << 30) +#define EMIF_REG_TA_SFEXITEN_SHIFT 28 +#define EMIF_REG_TA_SFEXITEN_MASK (1 << 28) +#define EMIF_REG_TA_DEVWDT_SHIFT 26 +#define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26) +#define EMIF_REG_TA_DEVCNT_SHIFT 24 +#define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24) +#define EMIF_REG_TA_REFINTERVAL_SHIFT 0 +#define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) + +/* OCP_ERR_LOG */ +#define EMIF_REG_MADDRSPACE_SHIFT 14 +#define EMIF_REG_MADDRSPACE_MASK (0x3 << 14) +#define EMIF_REG_MBURSTSEQ_SHIFT 11 +#define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11) +#define EMIF_REG_MCMD_SHIFT 8 +#define EMIF_REG_MCMD_MASK (0x7 << 8) +#define EMIF_REG_MCONNID_SHIFT 0 +#define EMIF_REG_MCONNID_MASK (0xff << 0) + +/* DDR_PHY_CTRL_1 */ +#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4 +#define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) +#define EMIF_REG_READ_LATENCY_SHIFT 0 +#define EMIF_REG_READ_LATENCY_MASK (0xf << 0) +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_1_SHDW */ +#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 +#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) +#define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0 +#define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0) +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_2 */ +#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 +#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) + +/* DMM */ +#define DMM_BASE 0x4E000040 + +/* Memory Adapter */ +#define MA_BASE 0x482AF040 + +/* DMM_LISA_MAP */ +#define EMIF_SYS_ADDR_SHIFT 24 +#define EMIF_SYS_ADDR_MASK (0xff << 24) +#define EMIF_SYS_SIZE_SHIFT 20 +#define EMIF_SYS_SIZE_MASK (0x7 << 20) +#define EMIF_SDRC_INTL_SHIFT 18 +#define EMIF_SDRC_INTL_MASK (0x3 << 18) +#define EMIF_SDRC_ADDRSPC_SHIFT 16 +#define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16) +#define EMIF_SDRC_MAP_SHIFT 8 +#define EMIF_SDRC_MAP_MASK (0x3 << 8) +#define EMIF_SDRC_ADDR_SHIFT 0 +#define EMIF_SDRC_ADDR_MASK (0xff << 0) + +/* DMM_LISA_MAP fields */ +#define DMM_SDRC_MAP_UNMAPPED 0 +#define DMM_SDRC_MAP_EMIF1_ONLY 1 +#define DMM_SDRC_MAP_EMIF2_ONLY 2 +#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 + +#define DMM_SDRC_INTL_NONE 0 +#define DMM_SDRC_INTL_128B 1 +#define DMM_SDRC_INTL_256B 2 +#define DMM_SDRC_INTL_512 3 + +#define DMM_SDRC_ADDR_SPC_SDRAM 0 +#define DMM_SDRC_ADDR_SPC_NVM 1 +#define DMM_SDRC_ADDR_SPC_INVALID 2 + +#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ + (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ + (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ + (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) + +#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) + +#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) + +/* Trap for invalid TILER PAT entries */ +#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ + (0 << EMIF_SDRC_ADDR_SHIFT) |\ + (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\ + (0xFF << EMIF_SYS_ADDR_SHIFT)) + + +/* Reg mapping structure */ +struct emif_reg_struct { + u32 emif_mod_id_rev; + u32 emif_status; + u32 emif_sdram_config; + u32 emif_lpddr2_nvm_config; + u32 emif_sdram_ref_ctrl; + u32 emif_sdram_ref_ctrl_shdw; + u32 emif_sdram_tim_1; + u32 emif_sdram_tim_1_shdw; + u32 emif_sdram_tim_2; + u32 emif_sdram_tim_2_shdw; + u32 emif_sdram_tim_3; + u32 emif_sdram_tim_3_shdw; + u32 emif_lpddr2_nvm_tim; + u32 emif_lpddr2_nvm_tim_shdw; + u32 emif_pwr_mgmt_ctrl; + u32 emif_pwr_mgmt_ctrl_shdw; + u32 emif_lpddr2_mode_reg_data; + u32 padding1[1]; + u32 emif_lpddr2_mode_reg_data_es2; + u32 padding11[1]; + u32 emif_lpddr2_mode_reg_cfg; + u32 emif_l3_config; + u32 emif_l3_cfg_val_1; + u32 emif_l3_cfg_val_2; + u32 emif_iodft_tlgc; + u32 padding2[7]; + u32 emif_perf_cnt_1; + u32 emif_perf_cnt_2; + u32 emif_perf_cnt_cfg; + u32 emif_perf_cnt_sel; + u32 emif_perf_cnt_tim; + u32 padding3; + u32 emif_read_idlectrl; + u32 emif_read_idlectrl_shdw; + u32 padding4; + u32 emif_irqstatus_raw_sys; + u32 emif_irqstatus_raw_ll; + u32 emif_irqstatus_sys; + u32 emif_irqstatus_ll; + u32 emif_irqenable_set_sys; + u32 emif_irqenable_set_ll; + u32 emif_irqenable_clr_sys; + u32 emif_irqenable_clr_ll; + u32 padding5; + u32 emif_zq_config; + u32 emif_temp_alert_config; + u32 emif_l3_err_log; + u32 padding6[4]; + u32 emif_ddr_phy_ctrl_1; + u32 emif_ddr_phy_ctrl_1_shdw; + u32 emif_ddr_phy_ctrl_2; +}; + +struct dmm_lisa_map_regs { + u32 dmm_lisa_map_0; + u32 dmm_lisa_map_1; + u32 dmm_lisa_map_2; + u32 dmm_lisa_map_3; +}; + +#define CS0 0 +#define CS1 1 +/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ +#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ + +/* + * The period of DDR clk is represented as numerator and denominator for + * better accuracy in integer based calculations. However, if the numerator + * and denominator are very huge there may be chances of overflow in + * calculations. So, as a trade-off keep denominator(and consequently + * numerator) within a limit sacrificing some accuracy - but not much + * If denominator and numerator are already small (such as at 400 MHz) + * no adjustment is needed + */ +#define EMIF_PERIOD_DEN_LIMIT 1000 +/* + * Maximum number of different frequencies supported by EMIF driver + * Determines the number of entries in the pointer array for register + * cache + */ +#define EMIF_MAX_NUM_FREQUENCIES 6 +/* + * Indices into the Addressing Table array. + * One entry each for all the different types of devices with different + * addressing schemes + */ +#define ADDR_TABLE_INDEX64M 0 +#define ADDR_TABLE_INDEX128M 1 +#define ADDR_TABLE_INDEX256M 2 +#define ADDR_TABLE_INDEX512M 3 +#define ADDR_TABLE_INDEX1GS4 4 +#define ADDR_TABLE_INDEX2GS4 5 +#define ADDR_TABLE_INDEX4G 6 +#define ADDR_TABLE_INDEX8G 7 +#define ADDR_TABLE_INDEX1GS2 8 +#define ADDR_TABLE_INDEX2GS2 9 +#define ADDR_TABLE_INDEXMAX 10 + +/* Number of Row bits */ +#define ROW_9 0 +#define ROW_10 1 +#define ROW_11 2 +#define ROW_12 3 +#define ROW_13 4 +#define ROW_14 5 +#define ROW_15 6 +#define ROW_16 7 + +/* Number of Column bits */ +#define COL_8 0 +#define COL_9 1 +#define COL_10 2 +#define COL_11 3 +#define COL_7 4 /*Not supported by OMAP included for completeness */ + +/* Number of Banks*/ +#define BANKS1 0 +#define BANKS2 1 +#define BANKS4 2 +#define BANKS8 3 + +/* Refresh rate in micro seconds x 10 */ +#define T_REFI_15_6 156 +#define T_REFI_7_8 78 +#define T_REFI_3_9 39 + +#define EBANK_CS1_DIS 0 +#define EBANK_CS1_EN 1 + +/* Read Latency used by the device at reset */ +#define RL_BOOT 3 +/* Read Latency for the highest frequency you want to use */ +#ifdef CONFIG_OMAP54XX +#define RL_FINAL 8 +#else +#define RL_FINAL 6 +#endif + + +/* Interleaving policies at EMIF level- between banks and Chip Selects */ +#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 +#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 + +/* + * Interleaving policy to be used + * Currently set to MAX interleaving for better performance + */ +#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING + +/* State of the core voltage: + * This is important for some parameters such as read idle control and + * ZQ calibration timings. Timings are much stricter when voltage ramp + * is happening compared to when the voltage is stable. + * We need to calculate two sets of values for these parameters and use + * them accordingly + */ +#define LPDDR2_VOLTAGE_STABLE 0 +#define LPDDR2_VOLTAGE_RAMPING 1 + +/* Length of the forced read idle period in terms of cycles */ +#define EMIF_REG_READ_IDLE_LEN_VAL 5 + +/* Interval between forced 'read idles' */ +/* To be used when voltage is changed for DPS/DVFS - 1us */ +#define READ_IDLE_INTERVAL_DVFS (1*1000) +/* + * To be used when voltage is not scaled except by Smart Reflex + * 50us - or maximum value will do + */ +#define READ_IDLE_INTERVAL_NORMAL (50*1000) + + +/* + * Unless voltage is changing due to DVFS one ZQCS command every 50ms should + * be enough. This shoule be enough also in the case when voltage is changing + * due to smart-reflex. + */ +#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) +/* + * If voltage is changing due to DVFS ZQCS should be performed more + * often(every 50us) + */ +#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 + +/* The interval between ZQCL commands as a multiple of ZQCS interval */ +#define REG_ZQ_ZQCL_MULT 4 +/* The interval between ZQINIT commands as a multiple of ZQCL interval */ +#define REG_ZQ_ZQINIT_MULT 3 +/* Enable ZQ Calibration on exiting Self-refresh */ +#define REG_ZQ_SFEXITEN_ENABLE 1 +/* + * ZQ Calibration simultaneously on both chip-selects: + * Needs one calibration resistor per CS + * None of the boards that we know of have this capability + * So disabled by default + */ +#define REG_ZQ_DUALCALEN_DISABLE 0 +/* + * Enable ZQ Calibration by default on CS0. If we are asked to program + * the EMIF there will be something connected to CS0 for sure + */ +#define REG_ZQ_CS0EN_ENABLE 1 + +/* EMIF_PWR_MGMT_CTRL register */ +/* Low power modes */ +#define LP_MODE_DISABLE 0 +#define LP_MODE_CLOCK_STOP 1 +#define LP_MODE_SELF_REFRESH 2 +#define LP_MODE_PWR_DN 3 + +/* REG_DPD_EN */ +#define DPD_DISABLE 0 +#define DPD_ENABLE 1 + +/* Maximum delay before Low Power Modes */ +#define REG_CS_TIM 0xF +#define REG_SR_TIM 0xF +#define REG_PD_TIM 0xF + +/* EMIF_PWR_MGMT_CTRL register */ +#define EMIF_PWR_MGMT_CTRL (\ + ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ + ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ + ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\ + & EMIF_REG_LP_MODE_MASK) |\ + ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\ + & EMIF_REG_DPD_EN_MASK))\ + +#define EMIF_PWR_MGMT_CTRL_SHDW (\ + ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\ + & EMIF_REG_CS_TIM_SHDW_MASK) |\ + ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\ + & EMIF_REG_SR_TIM_SHDW_MASK) |\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ + & EMIF_REG_PD_TIM_SHDW_MASK) |\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ + & EMIF_REG_PD_TIM_SHDW_MASK)) + +/* EMIF_L3_CONFIG register value */ +#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A300000 + +/* + * Value of bits 12:31 of DDR_PHY_CTRL_1 register: + * All these fields have magic values dependent on frequency and + * determined by PHY and DLL integration with EMIF. Setting the magic + * values suggested by hw team. + */ +#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF +#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 +#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 +#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF + +/* +* MR1 value: +* Burst length : 8 +* Burst type : sequential +* Wrap : enabled +* nWR : 3(default). EMIF does not do pre-charge. +* : So nWR is don't care +*/ +#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 + +/* MR2 */ +#define MR2_RL3_WL1 1 +#define MR2_RL4_WL2 2 +#define MR2_RL5_WL2 3 +#define MR2_RL6_WL3 4 + +/* MR10: ZQ calibration codes */ +#define MR10_ZQ_ZQCS 0x56 +#define MR10_ZQ_ZQCL 0xAB +#define MR10_ZQ_ZQINIT 0xFF +#define MR10_ZQ_ZQRESET 0xC3 + +/* TEMP_ALERT_CONFIG */ +#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ +#define TEMP_ALERT_CONFIG_DEVCT_1 0 +#define TEMP_ALERT_CONFIG_DEVWDT_32 2 + +/* MR16 value: refresh full array(no partial array self refresh) */ +#define MR16_REF_FULL_ARRAY 0 + +/* + * Maximum number of entries we keep in our array of timing tables + * We need not keep all the speed bins supported by the device + * We need to keep timing tables for only the speed bins that we + * are interested in + */ +#define MAX_NUM_SPEEDBINS 4 + +/* LPDDR2 Densities */ +#define LPDDR2_DENSITY_64Mb 0 +#define LPDDR2_DENSITY_128Mb 1 +#define LPDDR2_DENSITY_256Mb 2 +#define LPDDR2_DENSITY_512Mb 3 +#define LPDDR2_DENSITY_1Gb 4 +#define LPDDR2_DENSITY_2Gb 5 +#define LPDDR2_DENSITY_4Gb 6 +#define LPDDR2_DENSITY_8Gb 7 +#define LPDDR2_DENSITY_16Gb 8 +#define LPDDR2_DENSITY_32Gb 9 + +/* LPDDR2 type */ +#define LPDDR2_TYPE_S4 0 +#define LPDDR2_TYPE_S2 1 +#define LPDDR2_TYPE_NVM 2 + +/* LPDDR2 IO width */ +#define LPDDR2_IO_WIDTH_32 0 +#define LPDDR2_IO_WIDTH_16 1 +#define LPDDR2_IO_WIDTH_8 2 + +/* Mode register numbers */ +#define LPDDR2_MR0 0 +#define LPDDR2_MR1 1 +#define LPDDR2_MR2 2 +#define LPDDR2_MR3 3 +#define LPDDR2_MR4 4 +#define LPDDR2_MR5 5 +#define LPDDR2_MR6 6 +#define LPDDR2_MR7 7 +#define LPDDR2_MR8 8 +#define LPDDR2_MR9 9 +#define LPDDR2_MR10 10 +#define LPDDR2_MR11 11 +#define LPDDR2_MR16 16 +#define LPDDR2_MR17 17 +#define LPDDR2_MR18 18 + +/* MR0 */ +#define LPDDR2_MR0_DAI_SHIFT 0 +#define LPDDR2_MR0_DAI_MASK 1 +#define LPDDR2_MR0_DI_SHIFT 1 +#define LPDDR2_MR0_DI_MASK (1 << 1) +#define LPDDR2_MR0_DNVI_SHIFT 2 +#define LPDDR2_MR0_DNVI_MASK (1 << 2) + +/* MR4 */ +#define MR4_SDRAM_REF_RATE_SHIFT 0 +#define MR4_SDRAM_REF_RATE_MASK 7 +#define MR4_TUF_SHIFT 7 +#define MR4_TUF_MASK (1 << 7) + +/* MR4 SDRAM Refresh Rate field values */ +#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 +#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 +#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 +#define SDRAM_TEMP_NOMINAL 0x3 +#define SDRAM_TEMP_RESERVED_4 0x4 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 +#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 + +#define LPDDR2_MANUFACTURER_SAMSUNG 1 +#define LPDDR2_MANUFACTURER_QIMONDA 2 +#define LPDDR2_MANUFACTURER_ELPIDA 3 +#define LPDDR2_MANUFACTURER_ETRON 4 +#define LPDDR2_MANUFACTURER_NANYA 5 +#define LPDDR2_MANUFACTURER_HYNIX 6 +#define LPDDR2_MANUFACTURER_MOSEL 7 +#define LPDDR2_MANUFACTURER_WINBOND 8 +#define LPDDR2_MANUFACTURER_ESMT 9 +#define LPDDR2_MANUFACTURER_SPANSION 11 +#define LPDDR2_MANUFACTURER_SST 12 +#define LPDDR2_MANUFACTURER_ZMOS 13 +#define LPDDR2_MANUFACTURER_INTEL 14 +#define LPDDR2_MANUFACTURER_NUMONYX 254 +#define LPDDR2_MANUFACTURER_MICRON 255 + +/* MR8 register fields */ +#define MR8_TYPE_SHIFT 0x0 +#define MR8_TYPE_MASK 0x3 +#define MR8_DENSITY_SHIFT 0x2 +#define MR8_DENSITY_MASK (0xF << 0x2) +#define MR8_IO_WIDTH_SHIFT 0x6 +#define MR8_IO_WIDTH_MASK (0x3 << 0x6) + +struct lpddr2_addressing { + u8 num_banks; + u8 t_REFI_us_x10; + u8 row_sz[2]; /* One entry each for x32 and x16 */ + u8 col_sz[2]; /* One entry each for x32 and x16 */ +}; + +/* Structure for timings from the DDR datasheet */ +struct lpddr2_ac_timings { + u32 max_freq; + u8 RL; + u8 tRPab; + u8 tRCD; + u8 tWR; + u8 tRASmin; + u8 tRRD; + u8 tWTRx2; + u8 tXSR; + u8 tXPx2; + u8 tRFCab; + u8 tRTPx2; + u8 tCKE; + u8 tCKESR; + u8 tZQCS; + u32 tZQCL; + u32 tZQINIT; + u8 tDQSCKMAXx2; + u8 tRASmax; + u8 tFAW; + +}; + +/* + * Min tCK values for some of the parameters: + * If the calculated clock cycles for the respective parameter is + * less than the corresponding min tCK value, we need to set the min + * tCK value. This may happen at lower frequencies. + */ +struct lpddr2_min_tck { + u32 tRL; + u32 tRP_AB; + u32 tRCD; + u32 tWR; + u32 tRAS_MIN; + u32 tRRD; + u32 tWTR; + u32 tXP; + u32 tRTP; + u8 tCKE; + u32 tCKESR; + u32 tFAW; +}; + +struct lpddr2_device_details { + u8 type; + u8 density; + u8 io_width; + u8 manufacturer; +}; + +struct lpddr2_device_timings { + const struct lpddr2_ac_timings **ac_timings; + const struct lpddr2_min_tck *min_tck; +}; + +/* Details of the devices connected to each chip-select of an EMIF instance */ +struct emif_device_details { + const struct lpddr2_device_details *cs0_device_details; + const struct lpddr2_device_details *cs1_device_details; + const struct lpddr2_device_timings *cs0_device_timings; + const struct lpddr2_device_timings *cs1_device_timings; +}; + +/* + * Structure containing shadow of important registers in EMIF + * The calculation function fills in this structure to be later used for + * initialization and DVFS + */ +struct emif_regs { + u32 freq; + u32 sdram_config_init; + u32 sdram_config; + u32 ref_ctrl; + u32 sdram_tim1; + u32 sdram_tim2; + u32 sdram_tim3; + u32 read_idle_ctrl; + u32 zq_config; + u32 temp_alert_config; + u32 emif_ddr_phy_ctlr_1_init; + u32 emif_ddr_phy_ctlr_1; +}; + +/* assert macros */ +#if defined(DEBUG) +#define emif_assert(c) ({ if (!(c)) for (;;); }) +#else +#define emif_assert(c) ({ if (0) hang(); }) +#endif + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); +#else +struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details); +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings); +#endif + +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +extern u32 *const T_num; +extern u32 *const T_den; +extern u32 *const emif_sizes; +#endif + + +#endif diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 254905137c..2d5c3bc376 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1104,6 +1104,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_THALES_ADC 3492 #define MACH_TYPE_UBISYS_P9D_EVP 3493 #define MACH_TYPE_ATDGP318 3494 +#define MACH_TYPE_OMAP5_SEVM 3777 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14209,6 +14210,18 @@ extern unsigned int __machine_arch_type; # define machine_is_atdgp318() (0) #endif +#ifdef CONFIG_MACH_OMAP5_SEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP5_SEVM +# endif +# define machine_is_omap5_sevm() (machine_arch_type == MACH_TYPE_OMAP5_SEVM) +#else +# define machine_is_omap5_sevm() (0) +#endif + /* * These have not yet been registered */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 3f2f004afb..1ec651b353 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -37,7 +37,16 @@ void preloader_console_init(void); /* Boot device */ -#ifdef CONFIG_OMAP44XX /* OMAP4 */ +#ifdef CONFIG_OMAP54XX +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 +#define BOOT_DEVICE_MMC3 7 +#elif defined(CONFIG_OMAP44XX) /* OMAP4 */ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 @@ -71,10 +80,10 @@ struct spl_image_info { extern struct spl_image_info spl_image; +extern u32* boot_params_ptr; u32 omap_boot_device(void); u32 omap_boot_mode(void); - /* SPL common function s*/ void spl_parse_image_header(const struct image_header *header); void omap_rev_string(char *omap_rev_string); @@ -85,4 +94,27 @@ void spl_nand_load_image(void); /* MMC SPL functions */ void spl_mmc_load_image(void); +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void); +#endif + +/* + * silicon revisions. + * Moving this to common, so that most of code can be moved to common, + * directories. + */ + +/* omap4 */ +#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF +#define OMAP4430_ES1_0 0x44300100 +#define OMAP4430_ES2_0 0x44300200 +#define OMAP4430_ES2_1 0x44300210 +#define OMAP4430_ES2_2 0x44300220 +#define OMAP4430_ES2_3 0x44300230 +#define OMAP4460_ES1_0 0x44600100 +#define OMAP4460_ES1_1 0x44600110 + +/* omap5 */ +#define OMAP5430_SILICON_ID_INVALID 0 +#define OMAP5430_ES1_0 0x54300100 #endif /* _OMAP_COMMON_H_ */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index a482706fe8..3d78274072 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -73,10 +73,6 @@ extern int AT91F_DataflashInit(void); extern void dataflash_print_info(void); #endif -#ifdef CONFIG_DRIVER_RTL8019 -extern void rtl8019_get_enetaddr (uchar * addr); -#endif - #if defined(CONFIG_HARD_I2C) || \ defined(CONFIG_SOFT_I2C) #include <i2c.h> diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index eb3e26d4d2..e1b87bebad 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -13,7 +13,9 @@ int raise (int signum) { +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("raise: Signal # %d caught\n", signum); +#endif return 0; } diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index f9d46de231..3595aa2a99 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -48,9 +48,10 @@ ALL-y += $(obj)u-boot.ldr endif ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y) CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o -HOSTCFLAGS_NOPED += \ +HOSTCFLAGS_NOPED_ADSP := \ $(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) </dev/null \ | awk '$$2 ~ /ADSP/ { print "-D" $$2 }') +HOSTCFLAGS_NOPED += $(HOSTCFLAGS_NOPED_ADSP) else CREATE_LDR_ENV = endif diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c index 0cb833a0e4..20aeab81a2 100644 --- a/arch/blackfin/cpu/traps.c +++ b/arch/blackfin/cpu/traps.c @@ -150,7 +150,10 @@ int trap_c(struct pt_regs *regs, uint32_t level) (data ? 'D' : 'I'), (void *)new_cplb_addr); bfin_panic(regs); } else - debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end); + debug("CPLB addr %p matches map 0x%p - 0x%p\n", + (void *)new_cplb_addr, + (void *)bfin_memory_map[i].start, + (void *)bfin_memory_map[i].end); new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags); if (data) { @@ -163,16 +166,17 @@ int trap_c(struct pt_regs *regs, uint32_t level) /* find the next unlocked entry and evict it */ i = last_evicted & 0xF; - debug("last evicted = %i\n", i); + debug("last evicted = %zu\n", i); CPLB_DATA = CPLB_DATA_BASE + i; while (*CPLB_DATA & CPLB_LOCK) { - debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA); + debug("skipping %zu %p - %08X\n", i, CPLB_DATA, *CPLB_DATA); i = (i + 1) & 0xF; /* wrap around */ CPLB_DATA = CPLB_DATA_BASE + i; } CPLB_ADDR = CPLB_ADDR_BASE + i; - debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA); + debug("evicting entry %zu: 0x%p 0x%08X\n", i, + (void *)*CPLB_ADDR, *CPLB_DATA); last_evicted = i + 1; /* need to turn off cplbs whenever we muck with the cplb table */ @@ -190,7 +194,8 @@ int trap_c(struct pt_regs *regs, uint32_t level) CPLB_ADDR = CPLB_ADDR_BASE; CPLB_DATA = CPLB_DATA_BASE; for (i = 0; i < 16; ++i) - debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++); + debug("%2zu 0x%p 0x%08X\n", i, + (void *)*CPLB_ADDR++, *CPLB_DATA++); break; } diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index a70473c229..e3ee4cd353 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -308,7 +308,6 @@ static void board_net_init_r(bd_t *bd) void board_init_r(gd_t * id, ulong dest_addr) { - char *s; bd_t *bd; gd = id; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index 170bbfc356..a98a9262eb 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -284,7 +284,7 @@ void cpu_init_f(void) mbar_writeLong(MCF_FMPLL_SYNCR, MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); #endif - while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; + while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ; } /* diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c index 0ab666e8d7..c2636b1215 100644 --- a/arch/nds32/cpu/n1213/ag101/cpu.c +++ b/arch/nds32/cpu/n1213/ag101/cpu.c @@ -45,10 +45,6 @@ */ int cleanup_before_linux(void) { -#ifdef CONFIG_MMU - unsigned long i; -#endif - disable_interrupts(); #ifdef CONFIG_MMU @@ -123,8 +119,8 @@ void icache_inval_range(unsigned long start, unsigned long end) void flush_cache(unsigned long addr, unsigned long size) { - dcache_flush_range(addr , addr + size); - icache_inval_range(addr , addr + size); + dcache_flush_range(addr, addr + size); + icache_inval_range(addr, addr + size); } void icache_enable(void) diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c index c099c33acd..caa36b8be8 100644 --- a/arch/nds32/cpu/n1213/ag101/timer.c +++ b/arch/nds32/cpu/n1213/ag101/timer.c @@ -33,7 +33,7 @@ static ulong lastdec; int timer_init(void) { - static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; unsigned int cr; debug("%s()\n", __func__); @@ -80,7 +80,7 @@ int timer_init(void) */ void reset_timer_masked(void) { - static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; /* capure current decrementer value time */ #ifdef CONFIG_FTTMR010_EXT_CLK @@ -104,7 +104,7 @@ void reset_timer(void) */ ulong get_timer_masked(void) { - static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; /* current tick value */ #ifdef CONFIG_FTTMR010_EXT_CLK @@ -160,7 +160,7 @@ void set_timer(ulong t) /* delay x useconds AND preserve advance timestamp value */ void __udelay(unsigned long usec) { - static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; + struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; #ifdef CONFIG_FTTMR010_EXT_CLK long tmo = usec * (TIMER_CLOCK / 1000) / 1000; diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds index 45221ee78a..190342062a 100644 --- a/arch/nds32/cpu/n1213/u-boot.lds +++ b/arch/nds32/cpu/n1213/u-boot.lds @@ -41,7 +41,7 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { *(.data*) } . = ALIGN(4); diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h index 2c105f7fab..39c3dc8d92 100644 --- a/arch/nds32/include/asm/io.h +++ b/arch/nds32/include/asm/io.h @@ -165,6 +165,24 @@ static inline unsigned int readl(unsigned int *addr) #define __raw_base_readw(base, off) __arch_base_getw(base, off) #define __raw_base_readl(base, off) __arch_base_getl(base, off) +#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) + +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) + +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) + +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) + +#define out_8(a, v) __raw_writeb(v, a) +#define in_8(a) __raw_readb(a) + /* * Now, pick up the machine-defined IO definitions * #include <asm/arch/io.h> diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h index a6f1c93494..7b52b989bc 100644 --- a/arch/nds32/include/asm/mach-types.h +++ b/arch/nds32/include/asm/mach-types.h @@ -26,4 +26,18 @@ extern unsigned int __machine_arch_type; # define machine_is_adpag101() (0) #endif +#define MACH_TYPE_ADPAG101P 1 + +#ifdef CONFIG_ARCH_ADPAG101P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADPAG101P +# endif +# define machine_is_adpag101p() (machine_arch_type == MACH_TYPE_ADPAG101P) +#else +# define machine_is_adpag101p() (1) +#endif + #endif /* __ASM_NDS32_MACH_TYPE_H */ diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 2fd0e93d45..66e45370cc 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -351,6 +351,11 @@ void board_init_r(gd_t *id, ulong dest_addr) nand_init(); /* go init the NAND */ #endif +#if defined(CONFIG_CMD_IDE) + puts("IDE: "); + ide_init(); +#endif + #ifdef CONFIG_GENERIC_MMC puts("MMC: "); mmc_initialize(gd->bd); diff --git a/arch/nios2/cpu/Makefile b/arch/nios2/cpu/Makefile index aa41160af3..402fd749dd 100644 --- a/arch/nios2/cpu/Makefile +++ b/arch/nios2/cpu/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)lib$(CPU).o START = start.o SOBJS = exceptions.o COBJS = cpu.o interrupts.o sysid.o traps.o epcs.o +COBJS += fdt.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index ef360eecbb..edf256017a 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -24,6 +24,7 @@ #include <common.h> #include <nios2.h> #include <nios2-io.h> +#include <asm/cache.h> #if defined (CONFIG_SYS_NIOS_SYSID_BASE) extern void display_sysid (void); @@ -47,3 +48,18 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) nios2_callr(CONFIG_SYS_RESET_ADDR); return 0; } + +int dcache_status(void) +{ + return 1; +} + +void dcache_enable(void) +{ + flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE); +} + +void dcache_disable(void) +{ + flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE); +} diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c new file mode 100644 index 0000000000..b1ed9e17f2 --- /dev/null +++ b/arch/nios2/cpu/fdt.c @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2011, Missing Link Electronics + * Joachim Foerster <joachim@missinglinkelectronics.com> + * + * Taken from arch/powerpc/cpu/ppc4xx/fdt.c: + * + * (C) Copyright 2007-2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#include <libfdt.h> +#include <libfdt_env.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void __ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +void ft_board_setup(void *blob, bd_t *bd) \ + __attribute__((weak, alias("__ft_board_setup"))); + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + /* + * Fixup all ethernet nodes + * Note: aliases in the dts are required for this + */ + fdt_fixup_ethernet(blob); +} +#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */ diff --git a/arch/nios2/include/asm/gpio.h b/arch/nios2/include/asm/gpio.h index 4b21c8f7f2..908381f5f7 100644 --- a/arch/nios2/include/asm/gpio.h +++ b/arch/nios2/include/asm/gpio.h @@ -5,8 +5,8 @@ * bit[0] data * bit[1] output enable * - * when CONFIG_SYS_GPIO_BASE is not defined, board may provide - * its own driver. + * When CONFIG_SYS_GPIO_BASE is not defined, the board may either + * provide its own driver or the altera_pio driver may be used. * * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> * @@ -58,6 +58,15 @@ static inline int gpio_is_valid(int number) return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH; } #else +#ifdef CONFIG_ALTERA_PIO +extern int altera_pio_init(u32 base, u8 width, char iot, + u32 rstval, u32 negmask, + const char *label); + +extern void altera_pio_info(void); +#define gpio_status() altera_pio_info() +#endif + extern int gpio_request(unsigned gpio, const char *label); extern int gpio_free(unsigned gpio); extern int gpio_direction_input(unsigned gpio); diff --git a/arch/powerpc/cpu/mpc512x/i2c.c b/arch/powerpc/cpu/mpc512x/i2c.c index e2d909751e..0ea12806b9 100644 --- a/arch/powerpc/cpu/mpc512x/i2c.c +++ b/arch/powerpc/cpu/mpc512x/i2c.c @@ -78,9 +78,8 @@ static int wait_for_bb (void) status = mpc_reg_in (®s->msr); while (timeout-- && (status & I2C_BB)) { - volatile int temp; mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); - temp = mpc_reg_in (®s->mdr); + (void)mpc_reg_in(®s->mdr); mpc_reg_out (®s->mcr, 0, I2C_STA); mpc_reg_out (®s->mcr, 0, 0); mpc_reg_out (®s->mcr, I2C_EN, 0); diff --git a/arch/powerpc/cpu/mpc512x/pci.c b/arch/powerpc/cpu/mpc512x/pci.c index 141db8b865..16f034d58f 100644 --- a/arch/powerpc/cpu/mpc512x/pci.c +++ b/arch/powerpc/cpu/mpc512x/pci.c @@ -52,7 +52,6 @@ pci_init_board(void) volatile law512x_t *pci_law; volatile pot512x_t *pci_pot; volatile pcictrl512x_t *pci_ctrl; - volatile pciconf512x_t *pci_conf; u16 reg16; u32 reg32; u32 dev; @@ -73,7 +72,6 @@ pci_init_board(void) pci_law = im->sysconf.pcilaw; pci_pot = im->ios.pot; pci_ctrl = &im->pci_ctrl; - pci_conf = &im->pci_conf; hose = &pci_hose; diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 3855bfd457..04d519a4c7 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -149,7 +149,7 @@ long int spd_sdram() unsigned int memsize; unsigned int law_size; unsigned char caslat, caslat_ctrl; - unsigned int trfc, trfc_clk, trfc_low, trfc_high; + unsigned int trfc, trfc_clk, trfc_low; unsigned int trcd_clk, trtp_clk; unsigned char cke_min_clk; unsigned char add_lat, wr_lat; @@ -542,7 +542,6 @@ long int spd_sdram() * so preadjust it down 8 first before splitting it up. */ trfc_low = (trfc_clk - 8) & 0xf; - trfc_high = ((trfc_clk - 8) >> 4) & 0x3; ddr->timing_cfg_1 = (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */ diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a09eb91406..2ed5a98424 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -53,6 +53,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) + puts("Work-around for Erratum CPU-A003999 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) + puts("Work-around for Erratum DDR-A003473 enabled\n"); +#endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); #endif @@ -103,6 +109,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 puts("Work-around for Erratum NMG_LBC103 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + puts("Work-around for Erratum NMG ETSEC129 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 49c0551692..c1815e8860 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -42,6 +42,16 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * Default board reset function + */ +static void +__board_reset(void) +{ + /* Do nothing */ +} +void board_reset(void) __attribute__((weak, alias("__board_reset"))); + int checkcpu (void) { sys_info_t sysinfo; @@ -215,7 +225,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) mtspr(DBCR0,val); #else volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ + + /* Attempt board-specific reset */ + board_reset(); + + /* Next try asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); udelay(100); #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 0a4ce538f3..2e4a06c35a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,12 +37,15 @@ #include <asm/mmu.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <linux/compiler.h> #include "mp.h" -#ifdef CONFIG_SYS_QE_FW_IN_NAND +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include <nand.h> #include <errno.h> #endif +#include "../../../../drivers/block/fsl_sata.h" + DECLARE_GLOBAL_DATA_PTR; extern void srio_init(void); @@ -301,6 +304,7 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); */ int cpu_init_r(void) { + __maybe_unused u32 svr = get_svr(); #ifdef CONFIG_SYS_LBC_LCRR volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif @@ -316,11 +320,9 @@ int cpu_init_r(void) #if defined(CONFIG_L2_CACHE) volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile uint cache_ctl; - uint svr, ver; - uint l2srbar; + uint ver; u32 l2siz_field; - svr = get_svr(); ver = SVR_SOC_VER(svr); asm("msync;isync"); @@ -385,8 +387,8 @@ int cpu_init_r(void) if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { puts("already enabled"); - l2srbar = l2cache->l2srbar0; #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) + u32 l2srbar = l2cache->l2srbar0; if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE && l2srbar >= CONFIG_SYS_FLASH_BASE) { l2srbar = CONFIG_SYS_INIT_L2_ADDR; @@ -402,8 +404,8 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) - if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || - (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) { + if ((SVR_SOC_VER(svr) == SVR_P2040) || + (SVR_SOC_VER(svr) == SVR_P2040_E)) { puts("N/A\n"); goto skip_l2; } @@ -489,6 +491,32 @@ skip_l2: fman_enet_init(); #endif +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) + /* + * For P1022/1013 Rev1.0 silicon, after power on SATA host + * controller is configured in legacy mode instead of the + * expected enterprise mode. Software needs to clear bit[28] + * of HControl register to change to enterprise mode from + * legacy mode. We assume that the controller is offline. + */ + if (IS_SVR_REV(svr, 1, 0) && + ((SVR_SOC_VER(svr) == SVR_P1022) || + (SVR_SOC_VER(svr) == SVR_P1022_E) || + (SVR_SOC_VER(svr) == SVR_P1013) || + (SVR_SOC_VER(svr) == SVR_P1013_E))) { + fsl_sata_reg_t *reg; + + /* first SATA controller */ + reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; + clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); + + /* second SATA controller */ + reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; + clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); + } +#endif + + return 0; } @@ -524,17 +552,17 @@ void cpu_secondary_init_r(void) { #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ -#ifdef CONFIG_SYS_QE_FW_IN_NAND +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND int ret; - size_t fw_length = CONFIG_SYS_QE_FW_LENGTH; + size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; /* load QE firmware from NAND flash to DDR first */ - ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, - &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); + ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, + &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); if (ret && ret == -EUCLEAN) { printf ("NAND read for QE firmware at offset %x failed %d\n", - CONFIG_SYS_QE_FW_IN_NAND, ret); + CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); } #endif qe_init(qe_base); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 4ef3c9a8a5..091af7c95a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -71,7 +71,7 @@ void cpu_init_early_f(void) #endif #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; - u32 *l2srbar, *dst, *src; + u32 *dst, *src; void (*setup_ifc_sram)(void); #endif @@ -137,7 +137,7 @@ void cpu_init_early_f(void) dst = (u32 *) SRAM_BASE_ADDR; src = (u32 *) setup_ifc; for (i = 0; i < 1024; i++) - *l2srbar++ = *src++; + *dst++ = *src++; setup_ifc_sram(); diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index c8c84a1f7e..18e9cc5b8b 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -115,6 +115,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, for (i = 0; i < 32; i++) out_be32(&ddr->debug[i], regs->debug[i]); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); +#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ + /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 9d31568412..977770e99d 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -466,7 +466,7 @@ void fdt_fixup_fman_firmware(void *blob) return; } - if (length > CONFIG_SYS_FMAN_FW_LENGTH) { + if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { printf("Fman firmware at %p is too large (size=%u)\n", fmanfw, length); return; @@ -660,8 +660,19 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", "timer-frequency", gd->bus_clk/2, 1); + /* + * clock-freq should change to clock-frequency and + * flexcan-v1.0 should change to p1010-flexcan respectively + * in the future. + */ do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", - "clock_freq", gd->bus_clk, 1); + "clock_freq", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", + "clock-frequency", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan", + "clock-frequency", gd->bus_clk/2, 1); fdt_fixup_usb(blob); } @@ -677,6 +688,12 @@ void ft_cpu_setup(void *blob, bd_t *bd) #define CCSR_VIRT_TO_PHYS(x) \ (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) +static void msg(const char *name, uint64_t uaddr, uint64_t daddr) +{ + printf("Warning: U-Boot configured %s at address %llx,\n" + "but the device tree has it at %llx\n", name, uaddr, daddr); +} + /* * Verify the device tree * @@ -692,33 +709,32 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ int ft_verify_fdt(void *fdt) { - uint64_t ccsr = 0; + uint64_t addr = 0; int aliases; int off; /* First check the CCSR base address */ off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); if (off > 0) - ccsr = fdt_get_base_address(fdt, off); + addr = fdt_get_base_address(fdt, off); - if (!ccsr) { + if (!addr) { printf("Warning: could not determine base CCSR address in " "device tree\n"); /* No point in checking anything else */ return 0; } - if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) { - printf("Warning: U-Boot configured CCSR at address %llx,\n" - "but the device tree has it at %llx\n", - (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr); + if (addr != CONFIG_SYS_CCSRBAR_PHYS) { + msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); /* No point in checking anything else */ return 0; } /* - * Get the 'aliases' node. If there isn't one, then there's nothing - * left to do. + * Check some nodes via aliases. We assume that U-Boot and the device + * tree enumerate the devices equally. E.g. the first serial port in + * U-Boot is the same as "serial0" in the device tree. */ aliases = fdt_path_offset(fdt, "/aliases"); if (aliases > 0) { @@ -735,5 +751,30 @@ int ft_verify_fdt(void *fdt) #endif } + /* + * The localbus node is typically a root node, even though the lbc + * controller is part of CCSR. If we were to put the lbc node under + * the SOC node, then the 'ranges' property in the lbc node would + * translate through the 'ranges' property of the parent SOC node, and + * we don't want that. Since it's a separate node, it's possible for + * the 'reg' property to be wrong, so check it here. For now, we + * only check for "fsl,elbc" nodes. + */ +#ifdef CONFIG_SYS_LBC_ADDR + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); + if (off > 0) { + const u32 *reg = fdt_getprop(fdt, off, "reg", NULL); + if (reg) { + uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); + + addr = fdt_translate_address(fdt, off, reg); + if (uaddr != addr) { + msg("the localbus", uaddr, addr); + return 0; + } + } + } +#endif + return 1; } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 89ed5b47fc..4b52dad56c 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -495,7 +495,6 @@ void fsl_serdes_init(void) int cfg; serdes_corenet_t *srds_regs; int lane, bank, idx; - enum srds_prtcl lane_prtcl; int have_bank[SRDS_MAX_BANK] = {}; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 u32 serdes8_devdisr = 0; @@ -507,6 +506,7 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; @@ -516,6 +516,7 @@ void fsl_serdes_init(void) */ if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; +#endif /* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -617,7 +618,10 @@ void fsl_serdes_init(void) } } +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl; + idx = serdes_get_lane_idx(lane); lane_prtcl = serdes_get_prtcl(cfg, lane); @@ -729,6 +733,7 @@ void fsl_serdes_init(void) #endif } +#endif #ifdef DEBUG puts("\n"); diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 6678ed4118..c81e19c0e9 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -68,6 +68,12 @@ __secondary_start_page: mtspr SPRN_HID1,r3 #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 + mfspr r3,977 + oris r3,r3,0x0100 + mtspr 977,r3 +#endif + /* Enable branch prediction */ lis r3,BUCSR_ENABLE@h ori r3,r3,BUCSR_ENABLE@l diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 5e0d78d006..4d37d6e863 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -253,6 +253,12 @@ l2_disabled: mtspr HID1,r0 #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 + mfspr r3,977 + oris r3,r3,0x0100 + mtspr 977,r3 +#endif + /* Enable Branch Prediction */ #if defined(CONFIG_BTB) lis r0,BUCSR_ENABLE@h @@ -319,6 +325,55 @@ l2_disabled: #endif /* CONFIG_MPC8569 */ /* + * Search for the TLB that covers the code we're executing, and shrink it + * so that it covers only this 4K page. That will ensure that any other + * TLB we create won't interfere with it. We assume that the TLB exists, + * which is why we don't check the Valid bit of MAS1. + * + * This is necessary, for example, when booting from the on-chip ROM, + * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. + * If we don't shrink this TLB now, then we'll accidentally delete it + * in "purge_old_ccsr_tlb" below. + */ + bl nexti /* Find our address */ +nexti: mflr r1 /* R1 = our PC */ + li r2, 0 + mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ + isync + msync + tlbsx 0, r1 /* This must succeed */ + + /* Set the size of the TLB to 4KB */ + mfspr r3, MAS1 + li r2, 0xF00 + andc r3, r3, r2 /* Clear the TSIZE bits */ + ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l + mtspr MAS1, r3 + + /* + * Set the base address of the TLB to our PC. We assume that + * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. + */ + lis r3, MAS2_EPN@h + ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ + + and r1, r1, r3 /* Our PC, rounded down to the nearest page */ + + mfspr r2, MAS2 + andc r2, r2, r3 + or r2, r2, r1 + mtspr MAS2, r2 /* Set the EPN to our PC base address */ + + mfspr r2, MAS3 + andc r2, r2, r3 + or r2, r2, r1 + mtspr MAS3, r2 /* Set the RPN to our PC base address */ + + isync + msync + tlbwe + +/* * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default * location is not where we want it. This typically happens on a 36-bit * system, where we want to move CCSR to near the top of 36-bit address space. @@ -352,6 +407,8 @@ purge_old_ccsr_tlb: li r1, 0 mtspr MAS6, r1 /* Search the current address space and PID */ + isync + msync tlbsx 0, r8 mfspr r1, MAS1 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ @@ -359,6 +416,8 @@ purge_old_ccsr_tlb: rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ mtspr MAS1, r1 + isync + msync tlbwe 1: @@ -387,7 +446,7 @@ create_ccsr_new_tlb: tlbwe /* - * Create a TLB for the old location of CCSR. Register R9 is reserved + * Create a TLB for the current location of CCSR. Register R9 is reserved * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: @@ -407,6 +466,33 @@ create_ccsr_old_tlb: msync tlbwe + /* + * We have a TLB for what we think is the current (old) CCSR. Let's + * verify that, otherwise we won't be able to move it. + * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only + * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. + */ +verify_old_ccsr: + lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h + ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l +#ifdef CONFIG_FSL_CORENET + lwz r1, 4(r9) /* CCSRBARL */ +#else + lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ + slwi r1, r1, 12 +#endif + + cmpl 0, r0, r1 + + /* + * If the value we read from CCSRBARL is not what we expect, then + * enter an infinite loop. This will at least allow a debugger to + * halt execution and examine TLBs, etc. There's no point in going + * on. + */ +infinite_debug_loop: + bne infinite_debug_loop + #ifdef CONFIG_FSL_CORENET #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) @@ -446,7 +532,7 @@ create_temp_law: */ read_old_ccsrbar: lwz r0, 0(r9) /* CCSRBARH */ - lwz r0, 4(r9) /* CCSRBARH */ + lwz r0, 4(r9) /* CCSRBARL */ isync /* diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 01a3561fa0..929f6a607e 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -172,7 +172,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, void disable_tlb(u8 esel) { - u32 _mas0, _mas1, _mas2, _mas3, _mas7; + u32 _mas0, _mas1, _mas2, _mas3; free_tlb_cam(esel); @@ -180,14 +180,13 @@ void disable_tlb(u8 esel) _mas1 = 0; _mas2 = 0; _mas3 = 0; - _mas7 = 0; mtspr(MAS0, _mas0); mtspr(MAS1, _mas1); mtspr(MAS2, _mas2); mtspr(MAS3, _mas3); #ifdef CONFIG_ENABLE_36BIT_PHYS - mtspr(MAS7, _mas7); + mtspr(MAS7, 0); #endif asm volatile("isync;msync;tlbwe;isync"); @@ -252,16 +251,20 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) unsigned int tlb_size; unsigned int wimge = 0; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; - unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; + unsigned int max_cam; u64 size, memsize = (u64)memsize_in_meg << 20; #ifdef CONFIG_SYS_PPC_DDR_WIMGE wimge = CONFIG_SYS_PPC_DDR_WIMGE; #endif size = min(memsize, CONFIG_MAX_MEM_MAPPED); - - /* Convert (4^max) kB to (2^max) bytes */ - max_cam = max_cam * 2 + 10; + if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { + /* Convert (4^max) kB to (2^max) bytes */ + max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10; + } else { + /* Convert (2^max) kB to (2^max) bytes */ + max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10; + } for (i = 0; size && i < 8; i++) { int ram_tlb_index = find_free_tlbcam(); diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index ffcc8e6212..d2c8c78e86 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -48,7 +48,6 @@ checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; - uint ver; uint major, minor; char buf1[32], buf2[32]; volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; @@ -57,7 +56,6 @@ checkcpu(void) uint msscr0 = mfspr(MSSCR0); svr = get_svr(); - ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); @@ -77,7 +75,6 @@ checkcpu(void) puts("Core: "); pvr = get_pvr(); - ver = PVR_E600_VER(pvr); major = PVR_E600_MAJ(pvr); minor = PVR_E600_MIN(pvr); diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index 7725c67b48..1bbf4ccc65 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -125,6 +125,7 @@ DECLARE_GLOBAL_DATA_PTR; /************************************************************************/ #include <video_font.h> /* Get font data, width and height */ +#include <video_font_data.h> #ifdef CONFIG_VIDEO_LOGO #include <video_logo.h> /* Get logo data, width and height */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 15cd375ae3..2067d53ad2 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -672,7 +672,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, rcw_en = 1; ap_en = popts->ap_en; } else { - rcw_en = 0; ap_en = 0; } @@ -702,9 +701,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((obc_cfg & 0x1) << 6) | ((ap_en & 0x1) << 5) | ((d_init & 0x1) << 4) -#ifdef CONFIG_FSL_DDR3 | ((rcw_en & 0x1) << 2) -#endif | ((md_en & 0x1) << 0) ); debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); @@ -745,7 +742,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, #ifdef CONFIG_FSL_DDR3 if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < 4; i++) { + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (popts->rtt_override) rtt_wr = popts->rtt_wr_override_value; else @@ -944,7 +941,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < 4; i++) { + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (popts->rtt_override) rtt = popts->rtt_override_value; else diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index ffb503a777..d0a546610e 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -135,6 +135,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { case DDR3_SPD_MODULETYPE_RDIMM: case DDR3_SPD_MODULETYPE_MINI_RDIMM: + case DDR3_SPD_MODULETYPE_72B_SO_RDIMM: /* Registered/buffered DIMMs */ pdimm->registered_dimm = 1; for (i = 0; i < 16; i += 2) { @@ -148,6 +149,12 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, case DDR3_SPD_MODULETYPE_SO_DIMM: case DDR3_SPD_MODULETYPE_MICRO_DIMM: case DDR3_SPD_MODULETYPE_MINI_UDIMM: + case DDR3_SPD_MODULETYPE_MINI_CDIMM: + case DDR3_SPD_MODULETYPE_72B_SO_UDIMM: + case DDR3_SPD_MODULETYPE_72B_SO_CDIMM: + case DDR3_SPD_MODULETYPE_LRDIMM: + case DDR3_SPD_MODULETYPE_16B_SO_DIMM: + case DDR3_SPD_MODULETYPE_32B_SO_DIMM: /* Unbuffered DIMMs */ if (spd->mod_section.unbuffered.addr_mapping & 0x1) pdimm->mirrored_dimm = 1; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c index d7d66ef491..5b724371f6 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c @@ -1354,7 +1354,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo) { unsigned long long ddrsize; const char *prompt = "FSL DDR>"; - unsigned int len; char buffer[CONFIG_SYS_CBSIZE]; char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ int argc; @@ -1389,7 +1388,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo) * No need to worry for buffer overflow here in * this function; readline() maxes out at CFG_CBSIZE */ - len = readline_into_buffer(prompt, buffer); + readline_into_buffer(prompt, buffer); argc = parse_line(buffer, argv); if (argc == 0) continue; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 4dc748b951..00ec57be1f 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -483,7 +483,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int i; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; +#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) const struct dynamic_odt *pdodt = odt_unknown; +#endif ulong ddr_freq; /* @@ -493,6 +495,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; +#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) /* Chip select options. */ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { switch (pdimm[0].n_ranks) { @@ -546,6 +549,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, break; } } +#endif /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 112c603532..d07ae1b4fe 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -87,13 +87,12 @@ void ft_fixup_num_cores(void *blob) { #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ #ifdef CONFIG_HAS_FSL_DR_USB -static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, - const char *phy_type) +static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, + const char *phy_type, int start_offset) { const char *compat = "fsl-usb2-dr"; const char *prop_mode = "dr_mode"; const char *prop_type = "phy_type"; - static int start_offset = -1; int node_offset; int err; @@ -102,7 +101,7 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, if (node_offset < 0) { printf("WARNING: could not find compatible node %s: %s.\n", compat, fdt_strerror(node_offset)); - return; + return -1; } if (mode) { @@ -121,16 +120,18 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, prop_type, compat, fdt_strerror(err)); } - start_offset = node_offset; + return node_offset; } void fdt_fixup_dr_usb(void *blob, bd_t *bd) { const char *modes[] = { "host", "peripheral", "otg" }; - const char *phys[] = { "ulpi", "umti" }; + const char *phys[] = { "ulpi", "utmi" }; const char *mode = NULL; const char *phy_type = NULL; char usb1_defined = 0; + int usb_mode_off = -1; + int usb_phy_off = -1; char str[5]; int i, j; @@ -153,11 +154,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) } } if (mode_idx >= 0) - fdt_fixup_usb_mode_phy_type(blob, - modes[mode_idx], NULL); + usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, + modes[mode_idx], NULL, usb_mode_off); if (phy_idx >= 0) - fdt_fixup_usb_mode_phy_type(blob, - NULL, phys[phy_idx]); + usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, + NULL, phys[phy_idx], usb_phy_off); if (!strcmp(str, "usb1")) usb1_defined = 1; if (mode_idx < 0 && phy_idx < 0) @@ -165,11 +166,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) } } if (!usb1_defined) { + int usb_off = -1; mode = getenv("usb_dr_mode"); phy_type = getenv("usb_phy_type"); if (!mode && !phy_type) return; - fdt_fixup_usb_mode_phy_type(blob, mode, phy_type); + fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off); } } #endif /* CONFIG_HAS_FSL_DR_USB */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index d78962ff87..587576bacf 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -107,7 +107,7 @@ void init_early_memctl_regs(void) void upmconfig(uint upm, uint *table, uint size) { fsl_lbc_t *lbc = LBC_BASE_ADDR; - int i, mdr, mad, old_mad = 0; + int i, mad, old_mad = 0; u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK); u32 msel = BR_UPMx_TO_MSEL(upm); u32 *mxmr = &lbc->mamr + upm; @@ -138,7 +138,7 @@ void upmconfig(uint upm, uint *table, uint size) for (i = 0; i < size; i++) { out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i); out_be32(&lbc->mdr, table[i]); - mdr = in_be32(&lbc->mdr); + (void)in_be32(&lbc->mdr); *dummy = 0; do { mad = in_be32(mxmr) & MxMR_MAD_MSK; diff --git a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c index a31b17e9e8..48aa75391d 100644 --- a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c +++ b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c @@ -116,26 +116,25 @@ long int spd_sdram(int(read_spd)(uint addr)) { int tmp,row,col; int total_size,bank_size,bank_code; - int ecc_on; int mode; int bank_cnt; int sdram0_pmit=0x07c00000; + int sdram0_b0cr; + int sdram0_b1cr = 0; #ifndef CONFIG_405EP /* not on PPC405EP */ + int sdram0_b2cr = 0; + int sdram0_b3cr = 0; int sdram0_besr0 = -1; int sdram0_besr1 = -1; int sdram0_eccesr = -1; -#endif int sdram0_ecccfg; + int ecc_on; +#endif int sdram0_rtr=0; int sdram0_tr=0; - int sdram0_b0cr; - int sdram0_b1cr; - int sdram0_b2cr; - int sdram0_b3cr; - int sdram0_cfg=0; int t_rp; @@ -295,6 +294,7 @@ long int spd_sdram(int(read_spd)(uint addr)) if (bank_cnt > 4) /* we only have 4 banks to work with */ SPD_ERR("SDRAM - unsupported module rows for this width\n"); +#ifndef CONFIG_405EP /* not on PPC405EP */ /* now check for ECC ability of module. We only support ECC * on 32 bit wide devices with 8 bit ECC. */ @@ -305,6 +305,7 @@ long int spd_sdram(int(read_spd)(uint addr)) sdram0_ecccfg = 0; ecc_on = 0; } +#endif /*------------------------------------------------------------------ * calculate total size @@ -378,9 +379,6 @@ long int spd_sdram(int(read_spd)(uint addr)) * using the calculated values, compute the bank * config register values. * -------------------------------------------------------------------*/ - sdram0_b1cr = 0; - sdram0_b2cr = 0; - sdram0_b3cr = 0; /* compute the size of each bank */ bank_size = total_size / bank_cnt; @@ -444,8 +442,10 @@ long int spd_sdram(int(read_spd)(uint addr)) /* SDRAM have a power on delay, 500 micro should do */ udelay(500); sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; +#ifndef CONFIG_405EP /* not on PPC405EP */ if (ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK; +#endif mtsdram(SDRAM0_CFG, sdram0_cfg); return (total_size); diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c index e05daf23b7..8a20a2b1e0 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c @@ -380,8 +380,6 @@ static void program_cfg0(unsigned long *dimm_populated, unsigned char ecc; unsigned char attributes; unsigned long data_width; - unsigned long dimm_32bit; - unsigned long dimm_64bit; /* * get Memory Controller Options 0 data @@ -423,10 +421,8 @@ static void program_cfg0(unsigned long *dimm_populated, (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) + (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8); if (data_width == 64 || data_width == 72) { - dimm_64bit = TRUE; cfg0 |= SDRAM_CFG0_DMWD_64; } else if (data_width == 32 || data_width == 40) { - dimm_32bit = TRUE; cfg0 |= SDRAM_CFG0_DMWD_32; } else { printf("WARNING: DIMM with datawidth of %lu bits.\n", diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 4a2f33744d..85217ea272 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -445,9 +445,6 @@ static unsigned char spd_read(uchar chip, uint addr) phys_size_t initdram(int board_type) { unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; - unsigned char spd0[MAX_SPD_BYTES]; - unsigned char spd1[MAX_SPD_BYTES]; - unsigned char *dimm_spd[MAXDIMMS]; unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE}; unsigned long num_dimm_banks; /* on board dimm banks */ unsigned long val; @@ -458,12 +455,6 @@ phys_size_t initdram(int board_type) num_dimm_banks = sizeof(iic0_dimm_addr); /*------------------------------------------------------------------ - * Set up an array of SPD matrixes. - *-----------------------------------------------------------------*/ - dimm_spd[0] = spd0; - dimm_spd[1] = spd1; - - /*------------------------------------------------------------------ * Reset the DDR-SDRAM controller. *-----------------------------------------------------------------*/ mtsdr(SDR0_SRST, SDR0_SRST0_DMC); @@ -1000,7 +991,6 @@ static void program_copt1(unsigned long *dimm_populated, unsigned long attribute = 0; unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */ unsigned long bankcount; - unsigned long ddrtype; unsigned long val; #ifdef CONFIG_DDR_ECC @@ -1045,8 +1035,6 @@ static void program_copt1(unsigned long *dimm_populated, else /* bank count = 8 */ mcopt1 |= SDRAM_MCOPT1_8_BANKS; - /* test DDR type */ - ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2); /* test for buffered/unbuffered, registered, differential clocks */ registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20); attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21); @@ -1500,7 +1488,6 @@ static void program_mode(unsigned long *dimm_populated, else sdram_ddr1 = FALSE; - /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */ cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit); @@ -2490,12 +2477,6 @@ static void DQS_calibration_process(void) unsigned long val; long rffd_average; long max_start; - long min_end; - unsigned long begin_rqfd[MAXRANKS]; - unsigned long begin_rffd[MAXRANKS]; - unsigned long end_rqfd[MAXRANKS]; - unsigned long end_rffd[MAXRANKS]; - char window_found; unsigned long dlycal; unsigned long dly_val; unsigned long max_pass_length; @@ -2506,6 +2487,7 @@ static void DQS_calibration_process(void) unsigned char fail_found; unsigned char pass_found; #if !defined(CONFIG_DDR_RQDC_FIXED) + int window_found; u32 rqdc_reg; u32 rqfd; u32 rqfd_start; @@ -2559,16 +2541,6 @@ calibration_loop: #endif /* CONFIG_DDR_RQDC_FIXED */ max_start = 0; - min_end = 0; - begin_rqfd[0] = 0; - begin_rffd[0] = 0; - begin_rqfd[1] = 0; - begin_rffd[1] = 0; - end_rqfd[0] = 0; - end_rffd[0] = 0; - end_rqfd[1] = 0; - end_rffd[1] = 0; - window_found = FALSE; max_pass_length = 0; max_start = 0; @@ -2576,7 +2548,6 @@ calibration_loop: current_pass_length = 0; current_fail_length = 0; current_start = 0; - window_found = FALSE; fail_found = FALSE; pass_found = FALSE; @@ -2621,7 +2592,6 @@ calibration_loop: if (fail_found == FALSE) { fail_found = TRUE; } else if (pass_found == TRUE) { - window_found = TRUE; break; } } diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 4b8e65a51d..3c87bfb60e 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -154,18 +154,20 @@ u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt"))); static u32 *get_membase(int bxcr_num) { - ulong bxcf; u32 *membase; #if defined(SDRAM_R0BAS) /* BAS from Memory Queue rank reg. */ membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num))); - bxcf = 0; /* just to satisfy the compiler */ #else - /* BAS from SDRAM_MBxCF mem rank reg. */ - mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); - membase = (u32 *)((bxcf & 0xfff80000) << 3); + { + ulong bxcf; + + /* BAS from SDRAM_MBxCF mem rank reg. */ + mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); + membase = (u32 *)((bxcf & 0xfff80000) << 3); + } #endif return membase; @@ -719,7 +721,9 @@ static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal) static u32 DQS_calibration_methodB(struct ddrautocal *cal) { ulong rfdc_reg; +#ifndef CONFIG_DDR_RFDC_FIXED ulong rffd; +#endif ulong rqdc_reg; ulong rqfd; @@ -837,7 +841,6 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal) mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); #endif /* CONFIG_DDR_RFDC_FIXED */ - rffd = rffd_average; in_window = 0; curr_win_min = curr_win_max = 0; diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c index a87e93b80c..43b972fbb2 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c @@ -227,7 +227,6 @@ static void pcie_dmer_enable(void) static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 *val) { - u8 *address; *val = 0; if (validate_endpoint(hose)) @@ -255,7 +254,7 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) return 0; - address = pcie_get_base(hose, devfn); + pcie_get_base(hose, devfn); offset += devfn << 4; /* @@ -287,8 +286,6 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 val) { - u8 *address; - if (validate_endpoint(hose)) return 0; /* No upstream config access */ @@ -307,7 +304,7 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) return 0; - address = pcie_get_base(hose, devfn); + pcie_get_base(hose, devfn); offset += devfn << 4; /* @@ -1063,7 +1060,6 @@ int ppc4xx_init_pcie_endport(int port) void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; - volatile void *rmbase = NULL; pci_set_ops(hose, pcie_read_config_byte, @@ -1076,18 +1072,15 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) switch (port) { case 0: mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; - rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE; hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; break; case 1: mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; - rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE; hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; break; #if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; - rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE; hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; break; #endif diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile index d97ca207c0..3d62255039 100644 --- a/arch/powerpc/cpu/ppc4xx/Makefile +++ b/arch/powerpc/cpu/ppc4xx/Makefile @@ -61,7 +61,6 @@ COBJS += tlb.o COBJS += traps.o COBJS += usb.o COBJS += usb_ohci.o -COBJS += usbdev.o COBJS-$(CONFIG_XILINX_440) += xilinx_irq.o ifndef CONFIG_XILINX_440 COBJS += 4xx_uart.o diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c index 542ab69a13..231f69ebd0 100644 --- a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c +++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c @@ -113,8 +113,6 @@ static force_inline void set_mcopt1_mchk(u32 bits) */ static void inject_ecc_error(void *ptr, int par) { - u32 val; - /* * Taken from PPC460EX/EXr/GT users manual (Rev 1.21) * 22.2.17.13 ECC Diagnostics @@ -124,7 +122,7 @@ static void inject_ecc_error(void *ptr, int par) */ out_be32(ptr, 0x00000000); - val = in_be32(ptr); + in_be32(ptr); /* 6. Set memory controller to no error checking */ set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON); @@ -136,7 +134,7 @@ static void inject_ecc_error(void *ptr, int par) out_be32(ptr, in_be32(ptr) ^ 0x00000003); /* 8. Wait for SDRAM idle */ - val = in_be32(ptr); + in_be32(ptr); set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP); /* Wait for SDRAM idle */ @@ -151,7 +149,6 @@ static void rewrite_ecc_parity(void *ptr, int par) u32 end_address; u32 address_increment; u32 mcopt1; - u32 val; /* * Fill ECC parity byte again. Otherwise further accesses to @@ -159,7 +156,7 @@ static void rewrite_ecc_parity(void *ptr, int par) */ /* Wait for SDRAM idle */ - val = in_be32(0x00000000); + in_be32(0x00000000); set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN); /* ECC bit set method for non-cached memory */ diff --git a/arch/powerpc/cpu/ppc4xx/iop480_uart.c b/arch/powerpc/cpu/ppc4xx/iop480_uart.c index 0e3423f7ab..027ca30c25 100644 --- a/arch/powerpc/cpu/ppc4xx/iop480_uart.c +++ b/arch/powerpc/cpu/ppc4xx/iop480_uart.c @@ -134,7 +134,6 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { - volatile char val; unsigned short br_reg; br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); @@ -149,7 +148,7 @@ int serial_init (void) out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - val = in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ + in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ return (0); } diff --git a/arch/powerpc/cpu/ppc4xx/usb.c b/arch/powerpc/cpu/ppc4xx/usb.c index 592efe70a7..8c71f75e60 100644 --- a/arch/powerpc/cpu/ppc4xx/usb.c +++ b/arch/powerpc/cpu/ppc4xx/usb.c @@ -30,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#include "usbdev.h" - int usb_cpu_init(void) { #ifdef CONFIG_4xx_DCACHE @@ -39,9 +37,6 @@ int usb_cpu_init(void) change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); #endif -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) - usb_dev_init(); -#endif return 0; } diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c index fe091e3fa0..4fb7031203 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c @@ -44,8 +44,6 @@ #include <usb.h> #include "usb_ohci.h" -#include "usbdev.h" - #define OHCI_USE_NPS /* force NoPowerSwitching mode */ #undef OHCI_VERBOSE_DEBUG /* not always helpful */ #undef DEBUG @@ -753,10 +751,9 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf static void dl_transfer_length(td_t * td) { - __u32 tdINFO, tdBE, tdCBP; + __u32 tdBE, tdCBP; urb_priv_t *lurb_priv = &urb_priv; - tdINFO = ohci_cpu_to_le32 (td->hwINFO); tdBE = ohci_cpu_to_le32 (td->hwBE); tdCBP = ohci_cpu_to_le32 (td->hwCBP); @@ -1624,11 +1621,6 @@ int usb_lowlevel_init(void) ohci_inited = 1; urb_finished = 1; -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) - /* init the device driver */ - usb_dev_init(); -#endif - return 0; } diff --git a/arch/powerpc/cpu/ppc4xx/usbdev.c b/arch/powerpc/cpu/ppc4xx/usbdev.c deleted file mode 100644 index fe398afc02..0000000000 --- a/arch/powerpc/cpu/ppc4xx/usbdev.c +++ /dev/null @@ -1,230 +0,0 @@ -/*USB 1.1,2.0 device*/ - -#include <common.h> -#include <asm/processor.h> - -#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && defined(CONFIG_CMD_USB) - -#include <usb.h> -#include <asm/ppc4xx-uic.h> -#include "usbdev.h" - -#define USB_DT_DEVICE 0x01 -#define USB_DT_CONFIG 0x02 -#define USB_DT_STRING 0x03 -#define USB_DT_INTERFACE 0x04 -#define USB_DT_ENDPOINT 0x05 - -int set_value = -1; - -void process_endpoints(unsigned short usb2d0_intrin) -{ - /*will hold the packet received */ - struct usb_device_descriptor usb_device_packet; - struct usb_configuration_descriptor usb_config_packet; - struct usb_string_descriptor usb_string_packet; - struct devrequest setup_packet; - unsigned int *setup_packet_pt; - unsigned char *packet_pt = NULL; - int temp, temp1; - - int i; - - /*printf("{USB device} - endpoint 0x%X \n", usb2d0_intrin); */ - - /*set usb address, seems to not work unless it is done in the next - interrupt, so that is why it is done this way */ - if (set_value != -1) - *(unsigned char *)USB2D0_FADDR_8 = (unsigned char)set_value; - - /*endpoint 1 */ - if (usb2d0_intrin & 0x01) { - setup_packet_pt = (unsigned int *)&setup_packet; - - /*copy packet */ - setup_packet_pt[0] = *(unsigned int *)USB2D0_FIFO_0; - setup_packet_pt[1] = *(unsigned int *)USB2D0_FIFO_0; - temp = *(unsigned int *)USB2D0_FIFO_0; - temp1 = *(unsigned int *)USB2D0_FIFO_0; - - /*do some swapping */ - setup_packet.value = swap_16(setup_packet.value); - setup_packet.index = swap_16(setup_packet.index); - setup_packet.length = swap_16(setup_packet.length); - - /*clear rx packet */ - *(unsigned short *)USB2D0_INCSR0_8 = 0x48; - - /*printf("0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", setup_packet.requesttype, - setup_packet.request, setup_packet.value, - setup_packet.index, setup_packet.length, temp, temp1 ); */ - - switch (setup_packet.request) { - case USB_REQ_GET_DESCRIPTOR: - - switch (setup_packet.value >> 8) { - case USB_DT_DEVICE: - /*create packet */ - usb_device_packet.bLength = 18; - usb_device_packet.bDescriptorType = - USB_DT_DEVICE; -#ifdef USB_2_0_DEVICE - usb_device_packet.bcdUSB = swap_16(0x200); -#else - usb_device_packet.bcdUSB = swap_16(0x110); -#endif - usb_device_packet.bDeviceClass = 0xff; - usb_device_packet.bDeviceSubClass = 0; - usb_device_packet.bDeviceProtocol = 0; - usb_device_packet.bMaxPacketSize0 = 32; - usb_device_packet.idVendor = swap_16(1); - usb_device_packet.idProduct = swap_16(2); - usb_device_packet.bcdDevice = swap_16(0x300); - usb_device_packet.iManufacturer = 1; - usb_device_packet.iProduct = 1; - usb_device_packet.iSerialNumber = 1; - usb_device_packet.bNumConfigurations = 1; - - /*put packet in fifo */ - packet_pt = (unsigned char *)&usb_device_packet; - break; - - case USB_DT_CONFIG: - /*create packet */ - usb_config_packet.bLength = 9; - usb_config_packet.bDescriptorType = - USB_DT_CONFIG; - usb_config_packet.wTotalLength = swap_16(25); - usb_config_packet.bNumInterfaces = 1; - usb_config_packet.bConfigurationValue = 1; - usb_config_packet.iConfiguration = 0; - usb_config_packet.bmAttributes = 0x40; - usb_config_packet.bMaxPower = 0; - - /*put packet in fifo */ - packet_pt = (unsigned char *)&usb_config_packet; - break; - - case USB_DT_STRING: - /*create packet */ - usb_string_packet.bLength = 2; - usb_string_packet.bDescriptorType = - USB_DT_STRING; - usb_string_packet.wData[0] = 0x0094; - - /*put packet in fifo */ - packet_pt = (unsigned char *)&usb_string_packet; - break; - } - - /*put packet in fifo */ - for (i = 0; i < (setup_packet.length); i++) { - *(unsigned char *)USB2D0_FIFO_0 = packet_pt[i]; - } - - /*give tx command */ - *(unsigned short *)USB2D0_INCSR0_8 = 0x0a; - - break; - - case USB_REQ_SET_ADDRESS: - - /*copy usb address */ - set_value = setup_packet.value; - - break; - } - - } -} - -void process_other(unsigned char usb2d0_intrusb) -{ - - /*check for sof */ - if (usb2d0_intrusb & 0x08) { - /*printf("{USB device} - sof detected\n"); */ - } - - /*check for reset */ - if (usb2d0_intrusb & 0x04) { - /*printf("{USB device} - reset detected\n"); */ - - /*copy usb address of zero, need to do this when usb reset */ - set_value = 0; - } - - if (usb2d0_intrusb & 0x02) { - /*printf("{USB device} - resume detected\n"); */ - } - - if (usb2d0_intrusb & 0x01) { - /*printf("{USB device} - suspend detected\n"); */ - } -} - -int usbInt(void) -{ - /*Must read these 2 registers and use values to clear interrupts. If you - do not read them then the interrupt will not be cleared. If you do not - use the variable the optimizer will not do a read. */ - volatile unsigned short usb2d0_intrin = - *(unsigned short *)USB2D0_INTRIN_16; - volatile unsigned char usb2d0_intrusb = - *(unsigned char *)USB2D0_INTRUSB_8; - - /*check if there was an endpoint interrupt */ - if (usb2d0_intrin != 0) { - process_endpoints(usb2d0_intrin); - } - - /*check for other interrupts */ - if (usb2d0_intrusb != 0) { - process_other(usb2d0_intrusb); - } - - return 0; -} - -#if defined(CONFIG_440EPX) -void usb_dev_init() -{ - printf("USB 2.0 Device init\n"); - - /*usb dev init */ - *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */ - - /*enable interrupts */ - *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f; - - irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt, - NULL); -} -#else -void usb_dev_init() -{ -#ifdef USB_2_0_DEVICE - printf("USB 2.0 Device init\n"); - /*select 2.0 device */ - mtsdr(SDR0_USB0, 0x0); /* 2.0 */ - - /*usb dev init */ - *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */ -#else - printf("USB 1.1 Device init\n"); - /*select 1.1 device */ - mtsdr(SDR0_USB0, 0x2); /* 1.1 */ - - /*usb dev init */ - *(unsigned char *)USB2D0_POWER_8 = 0xc0; /* 1.1 */ -#endif - - /*enable interrupts */ - *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f; - - irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt, - NULL); -} -#endif - -#endif /* CONFIG_440EP || CONFIG_440EPX */ diff --git a/arch/powerpc/cpu/ppc4xx/usbdev.h b/arch/powerpc/cpu/ppc4xx/usbdev.h deleted file mode 100644 index ef6a2da649..0000000000 --- a/arch/powerpc/cpu/ppc4xx/usbdev.h +++ /dev/null @@ -1,31 +0,0 @@ -#include <config.h> - -/*Common Registers*/ -#define USB2D0_INTRIN_16 (CONFIG_SYS_USB_DEVICE | 0x100) -#define USB2D0_POWER_8 (CONFIG_SYS_USB_DEVICE | 0x102) -#define USB2D0_FADDR_8 (CONFIG_SYS_USB_DEVICE | 0x103) -#define USB2D0_INTRINE_16 (CONFIG_SYS_USB_DEVICE | 0x104) -#define USB2D0_INTROUT_16 (CONFIG_SYS_USB_DEVICE | 0x106) -#define USB2D0_INTRUSBE_8 (CONFIG_SYS_USB_DEVICE | 0x108) -#define USB2D0_INTRUSB_8 (CONFIG_SYS_USB_DEVICE | 0x109) -#define USB2D0_INTROUTE_16 (CONFIG_SYS_USB_DEVICE | 0x10a) -#define USB2D0_TSTMODE_8 (CONFIG_SYS_USB_DEVICE | 0x10c) -#define USB2D0_INDEX_8 (CONFIG_SYS_USB_DEVICE | 0x10d) -#define USB2D0_FRAME_16 (CONFIG_SYS_USB_DEVICE | 0x10e) - -/*Indexed Registers*/ -#define USB2D0_INCSR0_8 (CONFIG_SYS_USB_DEVICE | 0x110) -#define USB2D0_INCSR_16 (CONFIG_SYS_USB_DEVICE | 0x110) -#define USB2D0_INMAXP_16 (CONFIG_SYS_USB_DEVICE | 0x112) -#define USB2D0_OUTCSR_16 (CONFIG_SYS_USB_DEVICE | 0x114) -#define USB2D0_OUTMAXP_16 (CONFIG_SYS_USB_DEVICE | 0x116) -#define USB2D0_OUTCOUNT0_8 (CONFIG_SYS_USB_DEVICE | 0x11a) -#define USB2D0_OUTCOUNT_16 (CONFIG_SYS_USB_DEVICE | 0x11a) - -/*FIFOs*/ -#define USB2D0_FIFO_0 (CONFIG_SYS_USB_DEVICE | 0x120) -#define USB2D0_FIFO_1 (CONFIG_SYS_USB_DEVICE | 0x124) -#define USB2D0_FIFO_2 (CONFIG_SYS_USB_DEVICE | 0x128) -#define USB2D0_FIFO_3 (CONFIG_SYS_USB_DEVICE | 0x12c) - -void usb_dev_init(void); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index c3d6ba9e99..8654625fac 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 +#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 @@ -149,6 +150,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -236,6 +238,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -312,12 +315,15 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P2041) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -330,12 +336,15 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -348,6 +357,8 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P3060) #define CONFIG_MAX_CPUS 8 @@ -363,6 +374,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -373,6 +385,8 @@ #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -401,6 +415,8 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES9 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) @@ -408,6 +424,7 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -420,12 +437,14 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -438,6 +457,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #else #error Processor type not defined for this platform diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 99fe97d087..9b08cb8c1a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2420,6 +2420,7 @@ struct ccsr_rman { #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 +#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 #ifdef CONFIG_TSECV2 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 #else diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index ef5076b24d..209103e3ce 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -392,17 +392,17 @@ extern void print_bats(void); */ #define MAS0_TLBSEL_MSK 0x30000000 -#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK) +#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK) #define MAS0_ESEL_MSK 0x0FFF0000 -#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK) +#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK) #define MAS0_NV(x) ((x) & 0x00000FFF) #define MAS1_VALID 0x80000000 #define MAS1_IPROT 0x40000000 -#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) +#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) #define MAS1_TS 0x00001000 -#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) -#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10))) +#define MAS1_TSIZE(x) (((x) << 8) & 0x00000F00) +#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10)) #define MAS2_EPN 0xFFFFF000 #define MAS2_X0 0x00000040 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 1b96b84dcb..4e32639821 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -513,7 +513,13 @@ #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ +#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */ #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ +#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */ +#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ +#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ +#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk index f46b38fa0f..bdd3315ee1 100644 --- a/arch/sh/cpu/sh2/config.mk +++ b/arch/sh/cpu/sh2/config.mk @@ -24,10 +24,11 @@ ENDIANNESS += -EB ifdef CONFIG_SH2A -PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -mno-fdpic -ffreestanding +PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -ffreestanding else # SH2 PLATFORM_CPPFLAGS += -m3e -mb endif +PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic) PLATFORM_RELFLAGS += -ffixed-r13 PLATFORM_LDFLAGS += $(ENDIANNESS) diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index 377005cd4d..dc75e3981c 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -106,3 +106,25 @@ int cache_control(unsigned int cmd) return 0; } + +void dcache_wback_range(u32 start, u32 end) +{ + u32 v; + + start &= ~(L1_CACHE_BYTES - 1); + for (v = start; v < end; v += L1_CACHE_BYTES) { + asm volatile ("ocbwb %0" : /* no output */ + : "m" (__m(v))); + } +} + +void dcache_invalid_range(u32 start, u32 end) +{ + u32 v; + + start &= ~(L1_CACHE_BYTES - 1); + for (v = start; v < end; v += L1_CACHE_BYTES) { + asm volatile ("ocbi %0" : /* no output */ + : "m" (__m(v))); + } +} diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h index 6ffab4d374..24941b3019 100644 --- a/arch/sh/include/asm/cache.h +++ b/arch/sh/include/asm/cache.h @@ -10,27 +10,9 @@ int cache_control(unsigned int cmd); struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct *)(x)) -void dcache_wback_range(u32 start, u32 end) -{ - u32 v; - - start &= ~(L1_CACHE_BYTES - 1); - for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbwb %0" : /* no output */ - : "m" (__m(v))); - } -} - -void dcache_invalid_range(u32 start, u32 end) -{ - u32 v; - - start &= ~(L1_CACHE_BYTES - 1); - for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbi %0" : /* no output */ - : "m" (__m(v))); - } -} +void dcache_wback_range(u32 start, u32 end); +void dcache_invalid_range(u32 start, u32 end); + #else /* diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index 9b29d3ae7c..4351e8edff 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -44,6 +44,8 @@ # include <asm/cpu_sh7722.h> #elif defined (CONFIG_CPU_SH7723) # include <asm/cpu_sh7723.h> +#elif defined (CONFIG_CPU_SH7724) +# include <asm/cpu_sh7724.h> #elif defined (CONFIG_CPU_SH7757) # include <asm/cpu_sh7757.h> #elif defined (CONFIG_CPU_SH7763) diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h new file mode 100644 index 0000000000..3bb51d3f18 --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7724.h @@ -0,0 +1,234 @@ +/* + * (C) Copyright 2008, 2011 Renesas Solutions Corp. + * + * SH7724 Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH7724_H_ +#define _ASM_CPU_SH7724_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000090d + +/* EXP */ +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 + +/* MMU */ +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define PASCR 0xFF000070 +#define IRMCR 0xFF000078 + +/* CACHE */ +#define CCR 0xFF00001C +#define RAMCR 0xFF000074 + +/* INTC */ + +/* BSC */ +#define MMSELR 0xFF800020 +#define CMNCR 0xFEC10000 +#define CS0BCR 0xFEC10004 +#define CS2BCR 0xFEC10008 +#define CS4BCR 0xFEC10010 +#define CS5ABCR 0xFEC10014 +#define CS5BBCR 0xFEC10018 +#define CS6ABCR 0xFEC1001C +#define CS6BBCR 0xFEC10020 +#define CS0WCR 0xFEC10024 +#define CS2WCR 0xFEC10028 +#define CS4WCR 0xFEC10030 +#define CS5AWCR 0xFEC10034 +#define CS5BWCR 0xFEC10038 +#define CS6AWCR 0xFEC1003C +#define CS6BWCR 0xFEC10040 +#define RBWTCNT 0xFEC10054 + +/* SBSC */ +#define SBSC_SDCR 0xFE400008 +#define SBSC_SDWCR 0xFE40000C +#define SBSC_SDPCR 0xFE400010 +#define SBSC_RTCSR 0xFE400014 +#define SBSC_RTCNT 0xFE400018 +#define SBSC_RTCOR 0xFE40001C +#define SBSC_RFCR 0xFE400020 + +/* DSBC */ +#define DBKIND 0xFD000008 +#define DBSTATE 0xFD00000C +#define DBEN 0xFD000010 +#define DBCMDCNT 0xFD000014 +#define DBCKECNT 0xFD000018 +#define DBCONF 0xFD000020 +#define DBTR0 0xFD000030 +#define DBTR1 0xFD000034 +#define DBTR2 0xFD000038 +#define DBTR3 0xFD00003C +#define DBRFPDN0 0xFD000040 +#define DBRFPDN1 0xFD000044 +#define DBRFPDN2 0xFD000048 +#define DBRFSTS 0xFD00004C +#define DBMRCNT 0xFD000060 +#define DBPDCNT0 0xFD000108 + +/* DMAC */ + +/* CPG */ +#define FRQCRA 0xA4150000 +#define FRQCRB 0xA4150004 +#define FRQCR FRQCRA +#define VCLKCR 0xA4150004 +#define SCLKACR 0xA4150008 +#define SCLKBCR 0xA415000C +#define IRDACLKCR 0xA4150018 +#define PLLCR 0xA4150024 +#define DLLFRQ 0xA4150050 + +/* LOW POWER MODE */ +#define STBCR 0xA4150020 +#define MSTPCR0 0xA4150030 +#define MSTPCR1 0xA4150034 +#define MSTPCR2 0xA4150038 + +/* RWDT */ +#define RWTCNT 0xA4520000 +#define RWTCSR 0xA4520004 +#define WTCNT RWTCNT + +/* TMU */ +#define TSTR 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 + +/* TPU */ + +/* CMT */ +#define CMSTR 0xA44A0000 +#define CMCSR 0xA44A0060 +#define CMCNT 0xA44A0064 +#define CMCOR 0xA44A0068 + +/* MSIOF */ + +/* SCIF */ +#define SCIF0_BASE 0xFFE00000 +#define SCIF1_BASE 0xFFE10000 +#define SCIF2_BASE 0xFFE20000 +#define SCIF3_BASE 0xa4e30000 +#define SCIF4_BASE 0xa4e40000 +#define SCIF5_BASE 0xa4e50000 + +/* RTC */ +/* IrDA */ +/* KEYSC */ +/* USB */ +/* IIC */ +/* FLCTL */ +/* VPU */ +/* VIO(CEU) */ +/* VIO(VEU) */ +/* VIO(BEU) */ +/* 2DG */ +/* LCDC */ +/* VOU */ +/* TSIF */ +/* SIU */ +/* ATAPI */ + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PDCR 0xA4050106 +#define PECR 0xA4050108 +#define PFCR 0xA405010A +#define PGCR 0xA405010C +#define PHCR 0xA405010E +#define PJCR 0xA4050110 +#define PKCR 0xA4050112 +#define PLCR 0xA4050114 +#define PMCR 0xA4050116 +#define PNCR 0xA4050118 +#define PQCR 0xA405011A +#define PRCR 0xA405011C +#define PSCR 0xA405011E +#define PTCR 0xA4050140 +#define PUCR 0xA4050142 +#define PVCR 0xA4050144 +#define PWCR 0xA4050146 +#define PXCR 0xA4050148 +#define PYCR 0xA405014A +#define PZCR 0xA405014C +#define PSELA 0xA405014E +#define PSELB 0xA4050150 +#define PSELC 0xA4050152 +#define PSELD 0xA4050154 +#define PSELE 0xA4050156 +#define HIZCRA 0xA4050158 +#define HIZCRB 0xA405015A +#define HIZCRC 0xA405015C +#define HIZCRD 0xA405015E +#define MSELCRA 0xA4050180 +#define MSELCRB 0xA4050182 +#define PULCR 0xA4050184 +#define DRVCRA 0xA405018A +#define DRVCRB 0xA405018C + +/* I/O Port */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 +#define PDDR 0xA4050126 +#define PEDR 0xA4050128 +#define PFDR 0xA405012A +#define PGDR 0xA405012C +#define PHDR 0xA405012E +#define PJDR 0xA4050130 +#define PKDR 0xA4050132 +#define PLDR 0xA4050134 +#define PMDR 0xA4050136 +#define PNDR 0xA4050138 +#define PQDR 0xA405013A +#define PRDR 0xA405013C +#define PSDR 0xA405013E +#define PTDR 0xA4050160 +#define PUDR 0xA4050162 +#define PVDR 0xA4050164 +#define PWDR 0xA4050166 +#define PYDR 0xA4050168 +#define PZDR 0xA405016A + +/* Ether */ +#define EDMR 0xA4600000 + +/* UBC */ +/* H-UDI */ + +#endif /* _ASM_CPU_SH7724_H_ */ diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 6aaf55ae82..256811afd4 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -28,6 +28,7 @@ GLSOBJS += ashiftrt.o GLSOBJS += ashiftlt.o GLSOBJS += lshiftrt.o GLSOBJS += ashldi3.o +GLSOBJS += ashrsi3.o GLSOBJS += lshrdi3.o GLSOBJS += movmem.o diff --git a/arch/sh/lib/ashrsi3.S b/arch/sh/lib/ashrsi3.S new file mode 100644 index 0000000000..6f3cf46b77 --- /dev/null +++ b/arch/sh/lib/ashrsi3.S @@ -0,0 +1,185 @@ +/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006 + Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ + +!! libgcc routines for the Renesas / SuperH SH CPUs. +!! Contributed by Steve Chamberlain. +!! sac@cygnus.com + +!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines +!! recoded in assembly by Toshiyasu Morita +!! tm@netcom.com + +/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and + ELF local label prefixes by J"orn Rennecke + amylaar@cygnus.com */ + +! +! __ashrsi3 +! +! Entry: +! +! r4: Value to shift +! r5: Shifts +! +! Exit: +! +! r0: Result +! +! Destroys: +! +! (none) +! + + .global __ashrsi3 + + .align 2 +__ashrsi3: + mov #31,r0 + and r0,r5 + mova ashrsi3_table,r0 + mov.b @(r0,r5),r5 +#ifdef __sh1__ + add r5,r0 + jmp @r0 +#else + braf r5 +#endif + mov r4,r0 + + .align 2 +ashrsi3_table: + .byte ashrsi3_0-ashrsi3_table + .byte ashrsi3_1-ashrsi3_table + .byte ashrsi3_2-ashrsi3_table + .byte ashrsi3_3-ashrsi3_table + .byte ashrsi3_4-ashrsi3_table + .byte ashrsi3_5-ashrsi3_table + .byte ashrsi3_6-ashrsi3_table + .byte ashrsi3_7-ashrsi3_table + .byte ashrsi3_8-ashrsi3_table + .byte ashrsi3_9-ashrsi3_table + .byte ashrsi3_10-ashrsi3_table + .byte ashrsi3_11-ashrsi3_table + .byte ashrsi3_12-ashrsi3_table + .byte ashrsi3_13-ashrsi3_table + .byte ashrsi3_14-ashrsi3_table + .byte ashrsi3_15-ashrsi3_table + .byte ashrsi3_16-ashrsi3_table + .byte ashrsi3_17-ashrsi3_table + .byte ashrsi3_18-ashrsi3_table + .byte ashrsi3_19-ashrsi3_table + .byte ashrsi3_20-ashrsi3_table + .byte ashrsi3_21-ashrsi3_table + .byte ashrsi3_22-ashrsi3_table + .byte ashrsi3_23-ashrsi3_table + .byte ashrsi3_24-ashrsi3_table + .byte ashrsi3_25-ashrsi3_table + .byte ashrsi3_26-ashrsi3_table + .byte ashrsi3_27-ashrsi3_table + .byte ashrsi3_28-ashrsi3_table + .byte ashrsi3_29-ashrsi3_table + .byte ashrsi3_30-ashrsi3_table + .byte ashrsi3_31-ashrsi3_table + +ashrsi3_31: + rotcl r0 + rts + subc r0,r0 + +ashrsi3_30: + shar r0 +ashrsi3_29: + shar r0 +ashrsi3_28: + shar r0 +ashrsi3_27: + shar r0 +ashrsi3_26: + shar r0 +ashrsi3_25: + shar r0 +ashrsi3_24: + shlr16 r0 + shlr8 r0 + rts + exts.b r0,r0 + +ashrsi3_23: + shar r0 +ashrsi3_22: + shar r0 +ashrsi3_21: + shar r0 +ashrsi3_20: + shar r0 +ashrsi3_19: + shar r0 +ashrsi3_18: + shar r0 +ashrsi3_17: + shar r0 +ashrsi3_16: + shlr16 r0 + rts + exts.w r0,r0 + +ashrsi3_15: + shar r0 +ashrsi3_14: + shar r0 +ashrsi3_13: + shar r0 +ashrsi3_12: + shar r0 +ashrsi3_11: + shar r0 +ashrsi3_10: + shar r0 +ashrsi3_9: + shar r0 +ashrsi3_8: + shar r0 +ashrsi3_7: + shar r0 +ashrsi3_6: + shar r0 +ashrsi3_5: + shar r0 +ashrsi3_4: + shar r0 +ashrsi3_3: + shar r0 +ashrsi3_2: + shar r0 +ashrsi3_1: + rts + shar r0 + +ashrsi3_0: + rts + nop diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index 69b5ca4508..519a4fbae7 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -165,13 +165,10 @@ char *str_init_seq_done = "\n\rInit sequence done...\r\n\r\n"; void board_init_f(ulong bootflag) { - cmd_tbl_t *cmdtp; bd_t *bd; unsigned char *s; init_fnc_t **init_fnc_ptr; int j; - int i; - char *e; #ifndef CONFIG_SYS_NO_FLASH ulong flash_size; diff --git a/arch/sparc/lib/bootm.c b/arch/sparc/lib/bootm.c index 4c226a3a75..e5b933d1d6 100644 --- a/arch/sparc/lib/bootm.c +++ b/arch/sparc/lib/bootm.c @@ -97,8 +97,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t * im char *bootargs; ulong initrd_start, initrd_end; ulong rd_len; - unsigned int data, len, checksum; - unsigned int initrd_addr, kernend; void (*kernel) (struct linux_romvec *, void *); struct lmb *lmb = &images->lmb; int ret; diff --git a/arch/x86/config.mk b/arch/x86/config.mk index fe9083f626..23cacffded 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -41,3 +41,10 @@ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions LDFLAGS_FINAL += --gc-sections -pie +LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 +LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 + +NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) +PREFIXED_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/$(shell basename $(NORMAL_LIBGCC)) + +export USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC)) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index cac12c088c..61d0b69416 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -37,6 +37,7 @@ #include <asm/processor.h> #include <asm/processor-flags.h> #include <asm/interrupt.h> +#include <linux/compiler.h> /* * Constructor for a conventional segment GDT (or LDT) entry @@ -52,7 +53,7 @@ struct gdt_ptr { u16 len; u32 ptr; -} __attribute__((packed)); +} __packed; static void reload_gdt(void) { @@ -115,14 +116,14 @@ int x86_cpu_init_r(void) reload_gdt(); /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts (); + cpu_init_interrupts(); return 0; } int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - printf ("resetting ...\n"); + printf("resetting ...\n"); /* wait 50 ms */ udelay(50000); @@ -133,7 +134,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -void flush_cache (unsigned long dummy1, unsigned long dummy2) +void flush_cache(unsigned long dummy1, unsigned long dummy2) { asm("wbinvd\n"); } @@ -142,16 +143,16 @@ void __attribute__ ((regparm(0))) generate_gpf(void); /* segment 0x70 is an arbitrary segment which does not exist */ asm(".globl generate_gpf\n" - ".hidden generate_gpf\n" - ".type generate_gpf, @function\n" - "generate_gpf:\n" - "ljmp $0x70, $0x47114711\n"); + ".hidden generate_gpf\n" + ".type generate_gpf, @function\n" + "generate_gpf:\n" + "ljmp $0x70, $0x47114711\n"); void __reset_cpu(ulong addr) { printf("Resetting using x86 Triple Fault\n"); - set_vector(13, generate_gpf); /* general protection fault handler */ - set_vector(8, generate_gpf); /* double fault handler */ - generate_gpf(); /* start the show */ + set_vector(13, generate_gpf); /* general protection fault handler */ + set_vector(8, generate_gpf); /* double fault handler */ + generate_gpf(); /* start the show */ } void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu"))); diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index c6e72eaa63..e0958eb67f 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -31,6 +31,7 @@ #include <asm/interrupt.h> #include <asm/io.h> #include <asm/processor-flags.h> +#include <linux/compiler.h> #define DECLARE_INTERRUPT(x) \ ".globl irq_"#x"\n" \ @@ -83,22 +84,22 @@ static inline unsigned long get_debugreg(int regno) switch (regno) { case 0: - asm("mov %%db0, %0" :"=r" (val)); + asm("mov %%db0, %0" : "=r" (val)); break; case 1: - asm("mov %%db1, %0" :"=r" (val)); + asm("mov %%db1, %0" : "=r" (val)); break; case 2: - asm("mov %%db2, %0" :"=r" (val)); + asm("mov %%db2, %0" : "=r" (val)); break; case 3: - asm("mov %%db3, %0" :"=r" (val)); + asm("mov %%db3, %0" : "=r" (val)); break; case 6: - asm("mov %%db6, %0" :"=r" (val)); + asm("mov %%db6, %0" : "=r" (val)); break; case 7: - asm("mov %%db7, %0" :"=r" (val)); + asm("mov %%db7, %0" : "=r" (val)); break; default: val = 0; @@ -120,7 +121,8 @@ void dump_regs(struct irq_regs *regs) printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n", regs->esi, regs->edi, regs->ebp, regs->esp); printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n", - (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss); + (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, + (u16)regs->xgs, (u16)regs->xss); cr0 = read_cr0(); cr2 = read_cr2(); @@ -164,21 +166,21 @@ struct idt_entry { u8 res; u8 access; u16 base_high; -} __attribute__ ((packed)); +} __packed; struct desc_ptr { unsigned short size; unsigned long address; unsigned short segment; -} __attribute__((packed)); +} __packed; -struct idt_entry idt[256]; +struct idt_entry idt[256] __attribute__((aligned(16))); struct desc_ptr idt_ptr; static inline void load_idt(const struct desc_ptr *dtr) { - asm volatile("cs lidt %0"::"m" (*dtr)); + asm volatile("cs lidt %0" : : "m" (*dtr)); } void set_vector(u8 intnum, void *routine) @@ -187,6 +189,11 @@ void set_vector(u8 intnum, void *routine) idt[intnum].base_low = (u16)((u32)(routine) & 0xffff); } +/* + * Ideally these would be defined static to avoid a checkpatch warning, but + * the compiler cannot see them in the inline asm and complains that they + * aren't defined + */ void irq_0(void); void irq_1(void); @@ -201,7 +208,7 @@ int cpu_init_interrupts(void) disable_interrupts(); /* Setup the IDT */ - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { idt[i].access = 0x8e; idt[i].res = 0; idt[i].selector = 0x10; @@ -238,7 +245,7 @@ int disable_interrupts(void) asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : ); - return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */ + return flags & X86_EFLAGS_IF; } /* IRQ Low-Level Service Routine */ @@ -255,7 +262,7 @@ void irq_llsr(struct irq_regs *regs) case 0x00: printf("Divide Error (Division by zero)\n"); dump_regs(regs); - while(1); + hang(); break; case 0x01: printf("Debug Interrupt (Single step)\n"); @@ -272,32 +279,32 @@ void irq_llsr(struct irq_regs *regs) case 0x04: printf("Overflow\n"); dump_regs(regs); - while(1); + hang(); break; case 0x05: printf("BOUND Range Exceeded\n"); dump_regs(regs); - while(1); + hang(); break; case 0x06: printf("Invalid Opcode (UnDefined Opcode)\n"); dump_regs(regs); - while(1); + hang(); break; case 0x07: printf("Device Not Available (No Math Coprocessor)\n"); dump_regs(regs); - while(1); + hang(); break; case 0x08: printf("Double fault\n"); dump_regs(regs); - while(1); + hang(); break; case 0x09: printf("Co-processor segment overrun\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0a: printf("Invalid TSS\n"); @@ -306,12 +313,12 @@ void irq_llsr(struct irq_regs *regs) case 0x0b: printf("Segment Not Present\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0c: printf("Stack Segment Fault\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0d: printf("General Protection\n"); @@ -320,7 +327,7 @@ void irq_llsr(struct irq_regs *regs) case 0x0e: printf("Page fault\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0f: printf("Floating-Point Error (Math Fault)\n"); diff --git a/arch/x86/cpu/sc520/asm-offsets.c b/arch/x86/cpu/sc520/asm-offsets.c new file mode 100644 index 0000000000..794f00cdb9 --- /dev/null +++ b/arch/x86/cpu/sc520/asm-offsets.c @@ -0,0 +1,45 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/sc520.h> + +#include <linux/kbuild.h> + +int main(void) +{ + DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off)); + + DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0])); + DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1])); + DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2])); + DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3])); + DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4])); + DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5])); + DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6])); + DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7])); + DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8])); + DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9])); + DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10])); + DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11])); + DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12])); + DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13])); + DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14])); + DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15])); + + return 0; +} diff --git a/arch/x86/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c index 4892c0153f..3fe85e7648 100644 --- a/arch/x86/cpu/sc520/sc520.c +++ b/arch/x86/cpu/sc520/sc520.c @@ -49,7 +49,7 @@ int cpu_init_f(void) asm("movl $0x2000, %%ecx\n" "0: pushl %%ecx\n" "popl %%ecx\n" - "loop 0b\n": : : "ecx"); + "loop 0b\n" : : : "ecx"); return x86_cpu_init_f(); } diff --git a/arch/x86/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S index 7cac4d1def..c04cc1f116 100644 --- a/arch/x86/cpu/sc520/sc520_car.S +++ b/arch/x86/cpu/sc520/sc520_car.S @@ -24,6 +24,7 @@ #include <config.h> #include <asm/processor-flags.h> #include <asm/arch/sc520.h> +#include <generated/asm-offsets.h> .section .text @@ -55,7 +56,7 @@ car_init: /* Configure Cache-As-RAM PAR */ movl $CONFIG_SYS_SC520_CAR_PAR, %eax - movl $SC520_PAR2, %edi + movl $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi movl %eax, (%edi) /* Trash the cache then turn it on */ diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c index e26793ab1b..52d07c119a 100644 --- a/arch/x86/cpu/sc520/sc520_pci.c +++ b/arch/x86/cpu/sc520/sc520_pci.c @@ -70,26 +70,28 @@ int pci_sc520_set_irq(int pci_pin, int irq) debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); - if (irq < 0 || irq > 15) { + if (irq < 0 || irq > 15) return -1; /* illegal irq */ - } - if (pci_pin < 0 || pci_pin > 15) { + if (pci_pin < 0 || pci_pin > 15) return -1; /* illegal pci int pin */ - } /* first disable any non-pci interrupt source that use * this level */ /* PCI interrupt mapping (A through D)*/ - for (i=0; i<=3 ;i++) { - if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority) + for (i = 0; i <= 3 ; i++) { + tmpb = readb(&sc520_mmcr->pci_int_map[i]); + + if (tmpb == sc520_irq[irq].priority) writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]); } /* GP IRQ interrupt mapping */ - for (i=0; i<=10 ;i++) { - if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority) + for (i = 0; i <= 10 ; i++) { + tmpb = readb(&sc520_mmcr->gp_int_map[i]); + + if (tmpb == sc520_irq[irq].priority) writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]); } @@ -102,10 +104,12 @@ int pci_sc520_set_irq(int pci_pin, int irq) if (pci_pin < 4) { /* PCI INTA-INTD */ /* route the interrupt */ - writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]); + writeb(sc520_irq[irq].priority, + &sc520_mmcr->pci_int_map[pci_pin]); } else { /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]); + writeb(sc520_irq[irq].priority, + &sc520_mmcr->gp_int_map[pci_pin - 4]); /* also set the polarity in this case */ tmpw = readw(&sc520_mmcr->intpinpol); @@ -126,9 +130,7 @@ void pci_sc520_init(struct pci_controller *hose) hose->last_busno = 0xff; hose->region_count = pci_set_regions(hose); - pci_setup_type1(hose, - SC520_REG_ADDR, - SC520_REG_DATA); + pci_setup_type1(hose); pci_register_hose(hose); diff --git a/arch/x86/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c index 57e4e7ddc3..9dc13342e3 100644 --- a/arch/x86/cpu/sc520/sc520_sdram.c +++ b/arch/x86/cpu/sc520/sc520_sdram.c @@ -40,9 +40,6 @@ static void sc520_set_dram_timing(void); static void sc520_set_dram_refresh_rate(void); static void sc520_enable_dram_refresh(void); static void sc520_enable_sdram(void); -#if CONFIG_SYS_SDRAM_ECC_ENABLE -static void sc520_enable_ecc(void) -#endif int dram_init_f(void) { @@ -51,9 +48,6 @@ int dram_init_f(void) sc520_set_dram_refresh_rate(); sc520_enable_dram_refresh(); sc520_enable_sdram(); -#if CONFIG_SYS_SDRAM_ECC_ENABLE - sc520_enable_ecc(); -#endif return 0; } @@ -426,53 +420,6 @@ static void sc520_sizemem(void) writel(0x00000000, &sc520_mmcr->par[4]); } -#if CONFIG_SYS_SDRAM_ECC_ENABLE -static void sc520_enable_ecc(void) - - /* A nominal memory test: just a byte at each address line */ - movl %eax, %ecx - shrl $0x1, %ecx - movl $0x1, %edi -memtest0: - movb $0xa5, (%edi) - cmpb $0xa5, (%edi) - jne out - shrl $0x1, %ecx - andl %ecx, %ecx - jz set_ecc - shll $0x1, %edi - jmp memtest0 - -set_ecc: - /* clear all ram with a memset */ - movl %eax, %ecx - xorl %esi, %esi - xorl %edi, %edi - xorl %eax, %eax - shrl $0x2, %ecx - cld - rep stosl - - /* enable read, write buffers */ - movb $0x11, %al - movl $DBCTL, %edi - movb %al, (%edi) - - /* enable NMI mapping for ECC */ - movl $ECCINT, %edi - movb $0x10, %al - movb %al, (%edi) - - /* Turn on ECC */ - movl $ECCCTL, %edi - movb $0x05, %al - movb %al,(%edi) - -out: - jmp init_ecc_ret -} -#endif - int dram_init(void) { ulong dram_ctrl; diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c index 3a6a858091..cc601e56e4 100644 --- a/arch/x86/cpu/sc520/sc520_ssi.c +++ b/arch/x86/cpu/sc520/sc520_ssi.c @@ -28,37 +28,33 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) { - u8 temp=0; + u8 temp = 0; - if (freq >= 8192) { + if (freq >= 8192) temp |= CTL_CLK_SEL_4; - } else if (freq >= 4096) { + else if (freq >= 4096) temp |= CTL_CLK_SEL_8; - } else if (freq >= 2048) { + else if (freq >= 2048) temp |= CTL_CLK_SEL_16; - } else if (freq >= 1024) { + else if (freq >= 1024) temp |= CTL_CLK_SEL_32; - } else if (freq >= 512) { + else if (freq >= 512) temp |= CTL_CLK_SEL_64; - } else if (freq >= 256) { + else if (freq >= 256) temp |= CTL_CLK_SEL_128; - } else if (freq >= 128) { + else if (freq >= 128) temp |= CTL_CLK_SEL_256; - } else { + else temp |= CTL_CLK_SEL_512; - } - if (!lsb_first) { + if (!lsb_first) temp |= MSBF_ENB; - } - if (inv_clock) { + if (inv_clock) temp |= CLK_INV_ENB; - } - if (inv_phase) { + if (inv_phase) temp |= PHS_INV_ENB; - } writeb(temp, &sc520_mmcr->ssictl); @@ -68,9 +64,11 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) u8 ssi_txrx_byte(u8 data) { writeb(data, &sc520_mmcr->ssixmit); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; return readb(&sc520_mmcr->ssircv); } @@ -78,15 +76,18 @@ u8 ssi_txrx_byte(u8 data) void ssi_tx_byte(u8 data) { writeb(data, &sc520_mmcr->ssixmit); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd); } u8 ssi_rx_byte(void) { - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; return readb(&sc520_mmcr->ssircv); } diff --git a/arch/x86/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c index 05bc9c1103..495a69459b 100644 --- a/arch/x86/cpu/sc520/sc520_timer.c +++ b/arch/x86/cpu/sc520/sc520_timer.c @@ -38,7 +38,7 @@ void sc520_timer_isr(void) int timer_init(void) { /* Register the SC520 specific timer interrupt handler */ - register_timer_isr (sc520_timer_isr); + register_timer_isr(sc520_timer_isr); /* Install interrupt handler for GP Timer 1 */ irq_install_handler (0, timer_isr, NULL); @@ -62,7 +62,7 @@ int timer_init(void) writew(100, &sc520_mmcr->gptmr1maxcmpa); writew(0xe009, &sc520_mmcr->gptmr1ctl); - unmask_irq (0); + unmask_irq(0); /* Clear the GP Timer 1 status register to get the show rolling*/ writeb(0x02, &sc520_mmcr->gptmrsta); diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 306fb49617..f87633b561 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -30,6 +30,7 @@ #include <version.h> #include <asm/global_data.h> #include <asm/processor-flags.h> +#include <generated/asm-offsets.h> .section .text .code32 @@ -47,14 +48,12 @@ _x86boot_start: cli cld - /* Turn of cache (this might require a 486-class CPU) */ + /* Turn off cache (this might require a 486-class CPU) */ movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 wbinvd - /* Tell 32-bit code it is being entered from an in-RAM copy */ - movw $GD_FLG_WARM_BOOT, %bx _start: /* This is the 32-bit cold-reset entry point */ @@ -114,7 +113,7 @@ relocate_code: /* Setup call address of in-RAM copy of board_init_r() */ movl $board_init_r, %ebp - addl (GD_RELOC_OFF * 4)(%edx), %ebp + addl (GENERATED_GD_RELOC_OFF)(%edx), %ebp /* Setup parameters to board_init_r() */ movl %edx, %eax @@ -123,10 +122,31 @@ relocate_code: /* Jump to in-RAM copy of board_init_r() */ call *%ebp -die: hlt +die: + hlt jmp die hlt blank_idt_ptr: .word 0 /* limit */ .long 0 /* base */ + + .p2align 2 /* force 4-byte alignment */ + +multiboot_header: + /* magic */ + .long 0x1BADB002 + /* flags */ + .long (1 << 16) + /* checksum */ + .long -0x1BADB002 - (1 << 16) + /* header addr */ + .long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE + /* load addr */ + .long CONFIG_SYS_TEXT_BASE + /* load end addr */ + .long 0 + /* bss end addr */ + .long 0 + /* entry addr */ + .long CONFIG_SYS_TEXT_BASE diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 9dabff2b9f..33e53cdb3b 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -37,9 +37,6 @@ .code16 .globl start16 start16: - /* Set the Cold Boot / Hard Reset flag */ - movl $GD_FLG_COLD_BOOT, %ebx - /* * First we let the BSP do some early initialization * this code have to map the flash to its final position diff --git a/arch/x86/include/asm/arch-sc520/sc520.h b/arch/x86/include/asm/arch-sc520/sc520.h index 5ac9bb81d4..9dc29d39bc 100644 --- a/arch/x86/include/asm/arch-sc520/sc520.h +++ b/arch/x86/include/asm/arch-sc520/sc520.h @@ -259,32 +259,6 @@ extern sc520_mmcr_t *sc520_mmcr; /* Memory Mapped Control Registers (MMCR) Base Address */ #define SC520_MMCR_BASE 0xfffef000 -/* MMCR Addresses (required for assembler code) */ -#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010) -#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012) -#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014) -#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018) -#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020) -#define SC520_DBCTL (SC520_MMCR_BASE + 0x040) -#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18) - -#define SC520_PAR0 (SC520_MMCR_BASE + 0x088) -#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1)) -#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2)) -#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3)) -#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4)) -#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5)) -#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6)) -#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7)) -#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8)) -#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9)) -#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10)) -#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11)) -#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12)) -#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13)) -#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14)) -#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15)) - /* * PARs for maximum allowable 256MB of SDRAM @ 0x00000000 * Two PARs are required due to maximum PAR size of 128MB diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index f177a4fa3b..05a2139d00 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -61,25 +61,6 @@ extern gd_t *gd; #endif -/* Word Offsets into Global Data - MUST match struct gd_t */ -#define GD_BD 0 -#define GD_FLAGS 1 -#define GD_BAUDRATE 2 -#define GD_HAVE_CONSOLE 3 -#define GD_RELOC_OFF 4 -#define GD_LOAD_OFF 5 -#define GD_ENV_ADDR 6 -#define GD_ENV_VALID 7 -#define GD_CPU_CLK 8 -#define GD_BUS_CLK 9 -#define GD_RELOC_ADDR 10 -#define GD_START_ADDR_SP 11 -#define GD_RAM_SIZE 12 -#define GD_RESET_STATUS 13 -#define GD_JT 14 - -#define GD_SIZE 15 - /* * Global Data Flags */ @@ -91,8 +72,6 @@ extern gd_t *gd; #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ #define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ -#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ -#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */ #if 0 #define DECLARE_GLOBAL_DATA_PTR diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 85f60d77f0..37cc7e3a0f 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -26,7 +26,10 @@ #ifndef _PCI_I386_H_ #define _PCI_I386_H_ 1 -void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); +#define DEFINE_PCI_DEVICE_TABLE(_table) \ + const struct pci_device_id _table[] + +void pci_setup_type1(struct pci_controller *hose); int pci_enable_legacy_video_ports(struct pci_controller* hose); int pci_shadow_rom(pci_dev_t dev, unsigned char *dest); void pci_remove_rom_window(struct pci_controller* hose, u32 addr); diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h index c62310e3cd..0f12a893b4 100644 --- a/arch/x86/include/asm/realmode.h +++ b/arch/x86/include/asm/realmode.h @@ -25,6 +25,10 @@ #define __ASM_REALMODE_H_ #include <asm/ptrace.h> +extern ulong __realmode_start; +extern ulong __realmode_size; +extern char realmode_enter; + int bios_setup(void); int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out); int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out); diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index 3643a79fdf..3aa6c1131b 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -23,7 +23,7 @@ extern void * memmove(void *, const void *, __kernel_size_t); #undef __HAVE_ARCH_MEMCHR extern void * memchr(const void *, int, __kernel_size_t); -#undef __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_MEMSET extern void * memset(void *, int, __kernel_size_t); #undef __HAVE_ARCH_MEMZERO diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index d3e2f4c492..755f88af04 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -24,6 +24,14 @@ #ifndef _U_BOOT_I386_H_ #define _U_BOOT_I386_H_ 1 +/* Exports from the Linker Script */ +extern ulong __text_start; +extern ulong __data_end; +extern ulong __rel_dyn_start; +extern ulong __rel_dyn_end; +extern ulong __bss_start; +extern ulong __bss_end; + /* cpu/.../cpu.c */ int x86_cpu_init_r(void); int cpu_init_r(void); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 71e94f76f3..d584aa4a80 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -25,23 +25,25 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o -SOBJS-y += bios.o -SOBJS-y += bios_pci.o -SOBJS-y += realmode_switch.o +SOBJS-$(CONFIG_SYS_PC_BIOS) += bios.o +SOBJS-$(CONFIG_SYS_PCI_BIOS) += bios_pci.o +SOBJS-$(CONFIG_SYS_X86_REALMODE) += realmode_switch.o -COBJS-y += bios_setup.o +COBJS-$(CONFIG_SYS_PC_BIOS) += bios_setup.o COBJS-y += board.o COBJS-y += bootm.o +COBJS-y += gcc.o COBJS-y += interrupts.o COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_PCI) += pci_type1.o -COBJS-y += realmode.o -COBJS-y += timer.o -COBJS-y += video_bios.o -COBJS-y += video.o -COBJS-y += zimage.o +COBJS-$(CONFIG_SYS_X86_REALMODE) += realmode.o +COBJS-y += string.o +COBJS-$(CONFIG_SYS_X86_ISR_TIMER) += timer.o +COBJS-$(CONFIG_VIDEO) += video_bios.o +COBJS-$(CONFIG_VIDEO) += video.o +COBJS-$(CONFIG_CMD_ZBOOT) += zimage.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) @@ -49,6 +51,11 @@ OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(PREFIXED_LIBGCC): $(NORMAL_LIBGCC) + $(OBJCOPY) $< $@ --prefix-symbols=__normal_ + +$(LIB): $(PREFIXED_LIBGCC) + ######################################################################### # defines $(obj).depend target diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h index 4a9cdb591b..a220983df1 100644 --- a/arch/x86/lib/bios.h +++ b/arch/x86/lib/bios.h @@ -24,69 +24,150 @@ #ifndef _BIOS_H_ #define _BIOS_H_ -#define OFFS_ES 0 /* 16bit */ -#define OFFS_GS 2 /* 16bit */ -#define OFFS_DS 4 /* 16bit */ -#define OFFS_EDI 6 /* 32bit */ -#define OFFS_DI 6 /* low 16 bits of EDI */ -#define OFFS_ESI 10 /* 32bit */ -#define OFFS_SI 10 /* low 16 bits of ESI */ -#define OFFS_EBP 14 /* 32bit */ -#define OFFS_BP 14 /* low 16 bits of EBP */ -#define OFFS_ESP 18 /* 32bit */ -#define OFFS_SP 18 /* low 16 bits of ESP */ -#define OFFS_EBX 22 /* 32bit */ -#define OFFS_BX 22 /* low 16 bits of EBX */ -#define OFFS_BL 22 /* low 8 bits of BX */ -#define OFFS_BH 23 /* high 8 bits of BX */ -#define OFFS_EDX 26 /* 32bit */ -#define OFFS_DX 26 /* low 16 bits of EBX */ -#define OFFS_DL 26 /* low 8 bits of BX */ -#define OFFS_DH 27 /* high 8 bits of BX */ -#define OFFS_ECX 30 /* 32bit */ -#define OFFS_CX 30 /* low 16 bits of EBX */ -#define OFFS_CL 30 /* low 8 bits of BX */ -#define OFFS_CH 31 /* high 8 bits of BX */ -#define OFFS_EAX 34 /* 32bit */ -#define OFFS_AX 34 /* low 16 bits of EBX */ -#define OFFS_AL 34 /* low 8 bits of BX */ -#define OFFS_AH 35 /* high 8 bits of BX */ -#define OFFS_VECTOR 38 /* 16bit */ -#define OFFS_IP 40 /* 16bit */ -#define OFFS_CS 42 /* 16bit */ -#define OFFS_FLAGS 44 /* 16bit */ +#define OFFS_ES 0 /* 16bit */ +#define OFFS_GS 2 /* 16bit */ +#define OFFS_DS 4 /* 16bit */ +#define OFFS_EDI 6 /* 32bit */ +#define OFFS_DI 6 /* low 16 bits of EDI */ +#define OFFS_ESI 10 /* 32bit */ +#define OFFS_SI 10 /* low 16 bits of ESI */ +#define OFFS_EBP 14 /* 32bit */ +#define OFFS_BP 14 /* low 16 bits of EBP */ +#define OFFS_ESP 18 /* 32bit */ +#define OFFS_SP 18 /* low 16 bits of ESP */ +#define OFFS_EBX 22 /* 32bit */ +#define OFFS_BX 22 /* low 16 bits of EBX */ +#define OFFS_BL 22 /* low 8 bits of BX */ +#define OFFS_BH 23 /* high 8 bits of BX */ +#define OFFS_EDX 26 /* 32bit */ +#define OFFS_DX 26 /* low 16 bits of EBX */ +#define OFFS_DL 26 /* low 8 bits of BX */ +#define OFFS_DH 27 /* high 8 bits of BX */ +#define OFFS_ECX 30 /* 32bit */ +#define OFFS_CX 30 /* low 16 bits of EBX */ +#define OFFS_CL 30 /* low 8 bits of BX */ +#define OFFS_CH 31 /* high 8 bits of BX */ +#define OFFS_EAX 34 /* 32bit */ +#define OFFS_AX 34 /* low 16 bits of EBX */ +#define OFFS_AL 34 /* low 8 bits of BX */ +#define OFFS_AH 35 /* high 8 bits of BX */ +#define OFFS_VECTOR 38 /* 16bit */ +#define OFFS_IP 40 /* 16bit */ +#define OFFS_CS 42 /* 16bit */ +#define OFFS_FLAGS 44 /* 16bit */ -#define SEGMENT 0x40 -#define STACK 0x800 /* stack at 0x40:0x800 -> 0x800 */ +/* stack at 0x40:0x800 -> 0x800 */ +#define SEGMENT 0x40 +#define STACK 0x800 -/* save general registers */ -/* save some segments */ -/* save callers stack segment .. */ -/* ... in gs */ - /* setup my segments */ - /* setup BIOS stackpointer */ - -#define MAKE_BIOS_STACK \ - pushal; \ - pushw %ds; \ - pushw %gs; \ - pushw %es; \ - pushw %ss; \ - popw %gs; \ - movw $SEGMENT, %ax; \ - movw %ax, %ds; \ - movw %ax, %es; \ - movw %ax, %ss; \ - movw %sp, %bp; \ +/* + * save general registers + * save some segments + * save callers stack segment + * setup BIOS segments + * setup BIOS stackpointer + */ +#define MAKE_BIOS_STACK \ + pushal; \ + pushw %ds; \ + pushw %gs; \ + pushw %es; \ + pushw %ss; \ + popw %gs; \ + movw $SEGMENT, %ax; \ + movw %ax, %ds; \ + movw %ax, %es; \ + movw %ax, %ss; \ + movw %sp, %bp; \ movw $STACK, %sp -#define RESTORE_CALLERS_STACK \ - pushw %gs; /* restore callers stack segment */ \ - popw %ss; \ - movw %bp, %sp; /* restore stackpointer */ \ - popw %es; /* restore segment selectors */ \ - popw %gs; \ - popw %ds; \ - popal /* restore GP registers */ +/* + * restore callers stack segment + * restore some segments + * restore general registers + */ +#define RESTORE_CALLERS_STACK \ + pushw %gs; \ + popw %ss; \ + movw %bp, %sp; \ + popw %es; \ + popw %gs; \ + popw %ds; \ + popal + +#ifndef __ASSEMBLY__ +#define BIOS_DATA ((char *)0x400) +#define BIOS_DATA_SIZE 256 +#define BIOS_BASE ((char *)0xf0000) +#define BIOS_CS 0xf000 + +extern ulong __bios_start; +extern ulong __bios_size; + +/* these are defined in a 16bit segment and needs + * to be accessed with the RELOC_16_xxxx() macros below + */ +extern u16 ram_in_64kb_chunks; +extern u16 bios_equipment; +extern u8 pci_last_bus; + +extern void *rm_int00; +extern void *rm_int01; +extern void *rm_int02; +extern void *rm_int03; +extern void *rm_int04; +extern void *rm_int05; +extern void *rm_int06; +extern void *rm_int07; +extern void *rm_int08; +extern void *rm_int09; +extern void *rm_int0a; +extern void *rm_int0b; +extern void *rm_int0c; +extern void *rm_int0d; +extern void *rm_int0e; +extern void *rm_int0f; +extern void *rm_int10; +extern void *rm_int11; +extern void *rm_int12; +extern void *rm_int13; +extern void *rm_int14; +extern void *rm_int15; +extern void *rm_int16; +extern void *rm_int17; +extern void *rm_int18; +extern void *rm_int19; +extern void *rm_int1a; +extern void *rm_int1b; +extern void *rm_int1c; +extern void *rm_int1d; +extern void *rm_int1e; +extern void *rm_int1f; +extern void *rm_def_int; + +extern void *realmode_reset; +extern void *realmode_pci_bios_call_entry; + +#define RELOC_16_LONG(seg, off) (*(u32 *)(seg << 4 | (u32)&off)) +#define RELOC_16_WORD(seg, off) (*(u16 *)(seg << 4 | (u32)&off)) +#define RELOC_16_BYTE(seg, off) (*(u8 *)(seg << 4 | (u32)&off)) + +#ifdef PCI_BIOS_DEBUG +extern u32 num_pci_bios_present; +extern u32 num_pci_bios_find_device; +extern u32 num_pci_bios_find_class; +extern u32 num_pci_bios_generate_special_cycle; +extern u32 num_pci_bios_read_cfg_byte; +extern u32 num_pci_bios_read_cfg_word; +extern u32 num_pci_bios_read_cfg_dword; +extern u32 num_pci_bios_write_cfg_byte; +extern u32 num_pci_bios_write_cfg_word; +extern u32 num_pci_bios_write_cfg_dword; +extern u32 num_pci_bios_get_irq_routing; +extern u32 num_pci_bios_set_irq; +extern u32 num_pci_bios_unknown_function; +#endif + +#endif #endif diff --git a/arch/x86/lib/bios_pci.S b/arch/x86/lib/bios_pci.S index 53d2ea047a..47c478b27d 100644 --- a/arch/x86/lib/bios_pci.S +++ b/arch/x86/lib/bios_pci.S @@ -80,11 +80,15 @@ cs incl num_pci_bios_present #endif movl $0x20494350, %eax gs movl %eax, OFFS_EDX(%bp) + + /* We support cfg type 1 version 2.10 */ movb $0x01, %al -gs movb %al, OFFS_AL(%bp) /* We support cfg type 1 */ - movw $0x0210, %ax /* version 2.10 */ +gs movb %al, OFFS_AL(%bp) + movw $0x0210, %ax gs movw %ax, OFFS_BX(%bp) -cs movb pci_last_bus, %al /* last bus number */ + + /* last bus number */ +cs movb pci_last_bus, %al gs movb %al, OFFS_CL(%bp) jmp clear_carry @@ -97,16 +101,22 @@ cs incl num_pci_bios_find_device #endif gs movw OFFS_CX(%bp), %di shll $16, %edi -gs movw OFFS_DX(%bp), %di /* edi now holds device in upper 16 - * bits and vendor in lower 16 bits */ +gs movw OFFS_DX(%bp), %di + /* edi now holds device in upper 16 bits and vendor in lower 16 bits */ + gs movw OFFS_SI(%bp), %si - xorw %bx, %bx /* start at bus 0 dev 0 function 0 */ + + /* start at bus 0 dev 0 function 0 */ + xorw %bx, %bx pfd_loop: - xorw %ax, %ax /* dword 0 is vendor/device */ + /* dword 0 is vendor/device */ + xorw %ax, %ax call __pci_bios_select_register movw $0xcfc, %dx inl %dx, %eax - cmpl %edi, %eax /* our device ? */ + + /* our device ? */ + cmpl %edi, %eax je pfd_found_one pfd_next_dev: /* check for multi function devices */ @@ -120,13 +130,16 @@ pfd_next_dev: andb $0x80, %al jz pfd_not_multi_function pfd_function_not_zero: - incw %bx /* next function, overflows in to - * device number, then bus number */ + /* next function, overflows in to device number, then bus number */ + incw %bx jmp pfd_check_bus pfd_not_multi_function: - andw $0xfff8, %bx /* remove function bits */ - addw $0x0008, %bx /* next device, overflows in to bus number */ + /* remove function bits */ + andw $0xfff8, %bx + + /* next device, overflows in to bus number */ + addw $0x0008, %bx pfd_check_bus: cs movb pci_last_bus, %ah cmpb %ah, %bh @@ -142,7 +155,8 @@ gs movw %bx, OFFS_BX(%bp) jmp clear_carry pfd_not_found: - movb $0x86, %ah /* device not found */ + /* device not found */ + movb $0x86, %ah jmp set_carry /*****************************************************************************/ @@ -152,17 +166,24 @@ pci_bios_find_class: cs incl num_pci_bios_find_class #endif gs movl OFFS_ECX(%bp), %edi - andl $0x00ffffff, %edi /* edi now holds class-code in lower 24 bits */ + + /* edi now holds class-code in lower 24 bits */ + andl $0x00ffffff, %edi gs movw OFFS_SI(%bp), %si - xorw %bx, %bx /* start at bus 0 dev 0 function 0 */ + + /* start at bus 0 dev 0 function 0 */ + xorw %bx, %bx pfc_loop: - movw $8, %ax /* dword 8 is class-code high 24bits */ + /* dword 8 is class-code high 24bits */ + movw $8, %ax call __pci_bios_select_register movw $0xcfc, %dx inl %dx, %eax shrl $8, %eax andl $0x00ffffff, %eax - cmpl %edi, %eax /* our device ? */ + + /* our device ? */ + cmpl %edi, %eax je pfc_found_one pfc_next_dev: /* check for multi function devices */ @@ -175,13 +196,16 @@ pfc_next_dev: andb $0x80, %al jz pfc_not_multi_function pfc_function_not_zero: - incw %bx /* next function, overflows in to - * device number, then bus number */ + /* next function, overflows in to device number, then bus number */ + incw %bx jmp pfc_check_bus pfc_not_multi_function: - andw $0xfff8, %bx /* remove function bits */ - addw $0x0008, %bx /* next device, overflows in to bus number */ + /* remove function bits */ + andw $0xfff8, %bx + + /* next device, overflows in to bus number */ + addw $0x0008, %bx pfc_check_bus: cs movb pci_last_bus, %ah cmpb %ah, %bh @@ -197,7 +221,8 @@ gs movw %bx, OFFS_BX(%bp) jmp clear_carry pfc_not_found: - movb $0x86, %ah /* device not found */ + /* device not found */ + movb $0x86, %ah jmp set_carry /*****************************************************************************/ @@ -206,7 +231,8 @@ pci_bios_generate_special_cycle: #ifdef PCI_BIOS_DEBUG cs incl num_pci_bios_generate_special_cycle #endif - movb $0x81, %ah /* function not supported */ + /* function not supported */ + movb $0x81, %ah jmp set_carry /*****************************************************************************/ @@ -296,7 +322,8 @@ pci_bios_get_irq_routing: #ifdef PCI_BIOS_DEBUG cs incl num_pci_bios_get_irq_routing #endif - movb $0x81, %ah /* function not supported */ + /* function not supported */ + movb $0x81, %ah jmp set_carry /*****************************************************************************/ @@ -305,7 +332,8 @@ pci_bios_set_irq: #ifdef PCI_BIOS_DEBUG cs incl num_pci_bios_set_irq #endif - movb $0x81, %ah /* function not supported */ + /* function not supported */ + movb $0x81, %ah jmp set_carry /*****************************************************************************/ @@ -314,7 +342,8 @@ unknown_function: #ifdef PCI_BIOS_DEBUG cs incl num_pci_bios_unknown_function #endif - movb $0x81, %ah /* function not supported */ + /* function not supported */ + movb $0x81, %ah jmp set_carry /*****************************************************************************/ @@ -323,7 +352,8 @@ pci_bios_select_register: gs movw OFFS_BX(%bp), %bx gs movw OFFS_DI(%bp), %ax /* destroys eax, dx */ -__pci_bios_select_register: /* BX holds device id, AX holds register index */ +__pci_bios_select_register: + /* BX holds device id, AX holds register index */ pushl %ebx andl $0xfc, %eax andl $0xffff, %ebx @@ -338,7 +368,9 @@ __pci_bios_select_register: /* BX holds device id, AX holds regist clear_carry: gs movw OFFS_FLAGS(%bp), %ax - andw $0xfffe, %ax /* clear carry -- function succeeded */ + + /* clear carry -- function succeeded */ + andw $0xfffe, %ax gs movw %ax, OFFS_FLAGS(%bp) xorw %ax, %ax gs movb %ah, OFFS_AH(%bp) @@ -347,7 +379,9 @@ gs movb %ah, OFFS_AH(%bp) set_carry: gs movb %ah, OFFS_AH(%bp) gs movw OFFS_FLAGS(%bp), %ax - orw $1, %ax /* return carry -- function not supported */ + + /* return carry -- function not supported */ + orw $1, %ax gs movw %ax, OFFS_FLAGS(%bp) movw $-1, %ax ret diff --git a/arch/x86/lib/bios_setup.c b/arch/x86/lib/bios_setup.c index 9bf7e5872f..265f7d671e 100644 --- a/arch/x86/lib/bios_setup.c +++ b/arch/x86/lib/bios_setup.c @@ -34,74 +34,22 @@ #include <pci.h> #include <asm/realmode.h> #include <asm/io.h> +#include "bios.h" DECLARE_GLOBAL_DATA_PTR; #define NUMVECTS 256 -#define BIOS_DATA ((char*)0x400) -#define BIOS_DATA_SIZE 256 -#define BIOS_BASE ((char*)0xf0000) -#define BIOS_CS 0xf000 - -extern ulong __bios_start; -extern ulong __bios_size; - -/* these are defined in a 16bit segment and needs - * to be accessed with the RELOC_16_xxxx() macros below - */ -extern u16 ram_in_64kb_chunks; -extern u16 bios_equipment; -extern u8 pci_last_bus; - -extern void *rm_int00; -extern void *rm_int01; -extern void *rm_int02; -extern void *rm_int03; -extern void *rm_int04; -extern void *rm_int05; -extern void *rm_int06; -extern void *rm_int07; -extern void *rm_int08; -extern void *rm_int09; -extern void *rm_int0a; -extern void *rm_int0b; -extern void *rm_int0c; -extern void *rm_int0d; -extern void *rm_int0e; -extern void *rm_int0f; -extern void *rm_int10; -extern void *rm_int11; -extern void *rm_int12; -extern void *rm_int13; -extern void *rm_int14; -extern void *rm_int15; -extern void *rm_int16; -extern void *rm_int17; -extern void *rm_int18; -extern void *rm_int19; -extern void *rm_int1a; -extern void *rm_int1b; -extern void *rm_int1c; -extern void *rm_int1d; -extern void *rm_int1e; -extern void *rm_int1f; -extern void *rm_def_int; - -extern void *realmode_reset; -extern void *realmode_pci_bios_call_entry; - static int set_jmp_vector(int entry_point, void *target) { - if (entry_point & ~0xffff) { + if (entry_point & ~0xffff) return -1; - } - if (((u32)target-0xf0000) & ~0xffff) { + if (((u32)target - 0xf0000) & ~0xffff) return -1; - } + printf("set_jmp_vector: 0xf000:%04x -> %p\n", - entry_point, target); + entry_point, target); /* jmp opcode */ writeb(0xea, 0xf0000 + entry_point); @@ -115,51 +63,42 @@ static int set_jmp_vector(int entry_point, void *target) return 0; } - -/* - ************************************************************ - * Install an interrupt vector - ************************************************************ - */ - +/* Install an interrupt vector */ static void setvector(int vector, u16 segment, void *handler) { - u16 *ptr = (u16*)(vector*4); - ptr[0] = ((u32)handler - (segment << 4))&0xffff; + u16 *ptr = (u16 *)(vector * 4); + ptr[0] = ((u32)handler - (segment << 4)) & 0xffff; ptr[1] = segment; #if 0 printf("setvector: int%02x -> %04x:%04x\n", - vector, ptr[1], ptr[0]); + vector, ptr[1], ptr[0]); #endif } -#define RELOC_16_LONG(seg, off) *(u32*)(seg << 4 | (u32)&off) -#define RELOC_16_WORD(seg, off) *(u16*)(seg << 4 | (u32)&off) -#define RELOC_16_BYTE(seg, off) *(u8*)(seg << 4 | (u32)&off) - int bios_setup(void) { - ulong bios_start = (ulong)&__bios_start + gd->reloc_off; + /* The BIOS section is not relocated and still in the ROM. */ + ulong bios_start = (ulong)&__bios_start; ulong bios_size = (ulong)&__bios_size; - static int done=0; + static int done; int vector; #ifdef CONFIG_PCI struct pci_controller *pri_hose; #endif - if (done) { + if (done) return 0; - } + done = 1; if (bios_size > 65536) { printf("BIOS too large (%ld bytes, max is 65536)\n", - bios_size); + bios_size); return -1; } - memcpy(BIOS_BASE, (void*)bios_start, bios_size); + memcpy(BIOS_BASE, (void *)bios_start, bios_size); /* clear bda */ memset(BIOS_DATA, 0, BIOS_DATA_SIZE); @@ -178,9 +117,8 @@ int bios_setup(void) /* setup realmode interrupt vectors */ - for (vector = 0; vector < NUMVECTS; vector++) { + for (vector = 0; vector < NUMVECTS; vector++) setvector(vector, BIOS_CS, &rm_def_int); - } setvector(0x00, BIOS_CS, &rm_int00); setvector(0x01, BIOS_CS, &rm_int01); diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index 8963580808..d742fec928 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -56,15 +56,6 @@ #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); - -/* Exports from the Linker Script */ -extern ulong __text_start; -extern ulong __data_end; -extern ulong __rel_dyn_start; -extern ulong __rel_dyn_end; -extern ulong __bss_start; -extern ulong __bss_end; - /************************************************************************ * Init Utilities * ************************************************************************ @@ -72,49 +63,41 @@ extern ulong __bss_end; * or dropped completely, * but let's get it working (again) first... */ -static int init_baudrate (void) +static int init_baudrate(void) { gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); return 0; } -static int display_banner (void) +static int display_banner(void) { - printf ("\n\n%s\n\n", version_string); -/* - printf ("U-Boot code: %08lX -> %08lX data: %08lX -> %08lX\n" - " BSS: %08lX -> %08lX stack: %08lX -> %08lX\n", - i386boot_start, i386boot_romdata_start-1, - i386boot_romdata_dest, i386boot_romdata_dest+i386boot_romdata_size-1, - i386boot_bss_start, i386boot_bss_start+i386boot_bss_size-1, - i386boot_bss_start+i386boot_bss_size, - i386boot_bss_start+i386boot_bss_size+CONFIG_SYS_STACK_SIZE-1); - -*/ + printf("\n\n%s\n\n", version_string); - return (0); + return 0; } -static int display_dram_config (void) +static int display_dram_config(void) { int i; - puts ("DRAM Configuration:\n"); + puts("DRAM Configuration:\n"); - for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) { - printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); - print_size (gd->bd->bi_dram[i].size, "\n"); + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); + print_size(gd->bd->bi_dram[i].size, "\n"); } - return (0); + return 0; } -static void display_flash_config (ulong size) +#ifndef CONFIG_SYS_NO_FLASH +static void display_flash_config(ulong size) { - puts ("Flash: "); - print_size (size, "\n"); + puts("Flash: "); + print_size(size, "\n"); } +#endif /* * Breath some life into the board... @@ -178,19 +161,26 @@ gd_t *gd; static int calculate_relocation_address(void) { - void *text_start = &__text_start; - void *bss_end = &__bss_end; - void *dest_addr; + ulong text_start = (ulong)&__text_start; + ulong bss_end = (ulong)&__bss_end; + ulong dest_addr; ulong rel_offset; /* Calculate destination RAM Address and relocation offset */ - dest_addr = (void *)gd->ram_size; + dest_addr = gd->ram_size; dest_addr -= CONFIG_SYS_STACK_SIZE; dest_addr -= (bss_end - text_start); + + /* + * Round destination address down to 16-byte boundary to keep + * IDT and GDT 16-byte aligned + */ + dest_addr &= ~15; + rel_offset = dest_addr - text_start; gd->start_addr_sp = gd->ram_size; - gd->relocaddr = (ulong)dest_addr; + gd->relocaddr = dest_addr; gd->reloc_off = rel_offset; return 0; @@ -214,7 +204,7 @@ static int clear_bss(void) void *bss_end = &__bss_end; ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off); - ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);; + ulong *end_addr = (ulong *)(bss_end + gd->reloc_off); while (dst_addr < end_addr) *dst_addr++ = 0x00000000; @@ -227,10 +217,30 @@ static int do_elf_reloc_fixups(void) Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start); Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end); + Elf32_Addr *offset_ptr_rom; + Elf32_Addr *offset_ptr_ram; + + /* The size of the region of u-boot that runs out of RAM. */ + uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; + do { - if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE) - if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) >= CONFIG_SYS_TEXT_BASE) - *(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) += gd->reloc_off; + /* Get the location from the relocation entry */ + offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; + + /* Check that the location of the relocation is in .text */ + if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE) { + + /* Switch to the in-RAM version */ + offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom + + gd->reloc_off); + + /* Check that the target points into .text */ + if (*offset_ptr_ram >= CONFIG_SYS_TEXT_BASE && + *offset_ptr_ram < + (CONFIG_SYS_TEXT_BASE + size)) { + *offset_ptr_ram += gd->reloc_off; + } + } } while (re_src++ < re_end); return 0; @@ -254,13 +264,18 @@ void board_init_f(ulong boot_flags) relocate_code(gd->start_addr_sp, gd, gd->relocaddr); /* NOTREACHED - relocate_code() does not return */ - while(1); + while (1) + ; } void board_init_r(gd_t *id, ulong dest_addr) { +#if defined(CONFIG_CMD_NET) char *s; +#endif +#ifndef CONFIG_SYS_NO_FLASH ulong size; +#endif static bd_t bd_data; static gd_t gd_data; init_fnc_t **init_fnc_ptr; @@ -272,10 +287,10 @@ void board_init_r(gd_t *id, ulong dest_addr) memcpy(gd, id, sizeof(gd_t)); /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); + __asm__ __volatile__("" : : : "memory"); gd->bd = &bd_data; - memset (gd->bd, 0, sizeof (bd_t)); + memset(gd->bd, 0, sizeof(bd_t)); show_boot_progress(0x22); gd->baudrate = CONFIG_BAUDRATE; @@ -285,28 +300,31 @@ void board_init_r(gd_t *id, ulong dest_addr) for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) - hang (); + hang(); } show_boot_progress(0x23); #ifdef CONFIG_SERIAL_MULTI serial_initialize(); #endif + +#ifndef CONFIG_SYS_NO_FLASH /* configure available FLASH banks */ size = flash_init(); display_flash_config(size); show_boot_progress(0x24); +#endif show_boot_progress(0x25); /* initialize environment */ - env_relocate (); + env_relocate(); show_boot_progress(0x26); #ifdef CONFIG_CMD_NET /* IP Address */ - bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr"); + bd_data.bi_ip_addr = getenv_IPaddr("ipaddr"); #endif #if defined(CONFIG_PCI) @@ -319,9 +337,9 @@ void board_init_r(gd_t *id, ulong dest_addr) show_boot_progress(0x27); - stdio_init (); + stdio_init(); - jumptable_init (); + jumptable_init(); /* Initialize the console (after the relocation and devices init) */ console_init_r(); @@ -333,7 +351,7 @@ void board_init_r(gd_t *id, ulong dest_addr) #if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE) WATCHDOG_RESET(); - puts ("PCMCIA:"); + puts("PCMCIA:"); pcmcia_init(); #endif @@ -348,7 +366,7 @@ void board_init_r(gd_t *id, ulong dest_addr) show_boot_progress(0x28); #ifdef CONFIG_STATUS_LED - status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); + status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); #endif udelay(20); @@ -356,9 +374,10 @@ void board_init_r(gd_t *id, ulong dest_addr) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); #if defined(CONFIG_CMD_NET) - if ((s = getenv ("bootfile")) != NULL) { - copy_filename (BootFile, s, sizeof (BootFile)); - } + s = getenv("bootfile"); + + if (s != NULL) + copy_filename(BootFile, s, sizeof(BootFile)); #endif WATCHDOG_RESET(); @@ -390,10 +409,10 @@ void board_init_r(gd_t *id, ulong dest_addr) eth_initialize(gd->bd); #endif -#if ( defined(CONFIG_CMD_NET)) && (0) +#if (defined(CONFIG_CMD_NET)) && (0) WATCHDOG_RESET(); # ifdef DEBUG - puts ("Reset Ethernet PHY\n"); + puts("Reset Ethernet PHY\n"); # endif reset_phy(); #endif @@ -410,27 +429,27 @@ void board_init_r(gd_t *id, ulong dest_addr) #ifdef CONFIG_POST - post_run (NULL, POST_RAM | post_bootmode_get(0)); + post_run(NULL, POST_RAM | post_bootmode_get(0)); #endif - show_boot_progress(0x29); /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { + for (;;) main_loop(); - } /* NOTREACHED - no way out of command loop except booting */ } -void hang (void) +void hang(void) { - puts ("### ERROR ### Please RESET the board ###\n"); - for (;;); + puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; } -unsigned long do_go_exec (ulong (*entry)(int, char * const []), int argc, char * const argv[]) +unsigned long do_go_exec(ulong (*entry)(int, char * const []), + int argc, char * const argv[]) { unsigned long ret = 0; char **argv_tmp; diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index a21a21f1f7..bac7b4f0cf 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -32,9 +32,10 @@ #include <asm/zimage.h> /*cmd_boot.c*/ -int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) +int do_bootm_linux(int flag, int argc, char * const argv[], + bootm_headers_t *images) { - void *base_ptr; + void *base_ptr = NULL; ulong os_data, os_len; image_header_t *hdr; @@ -48,41 +49,43 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima if (images->legacy_hdr_valid) { hdr = images->legacy_hdr_os; - if (image_check_type (hdr, IH_TYPE_MULTI)) { + if (image_check_type(hdr, IH_TYPE_MULTI)) { /* if multi-part image, we need to get first subimage */ - image_multi_getimg (hdr, 0, &os_data, &os_len); + image_multi_getimg(hdr, 0, &os_data, &os_len); } else { /* otherwise get image data */ - os_data = image_get_data (hdr); - os_len = image_get_data_size (hdr); + os_data = image_get_data(hdr); + os_len = image_get_data_size(hdr); } #if defined(CONFIG_FIT) } else if (images->fit_uname_os) { - ret = fit_image_get_data (images->fit_hdr_os, + ret = fit_image_get_data(images->fit_hdr_os, images->fit_noffset_os, &data, &len); if (ret) { - puts ("Can't get image data/size!\n"); + puts("Can't get image data/size!\n"); goto error; } os_data = (ulong)data; os_len = (ulong)len; #endif } else { - puts ("Could not find kernel image!\n"); + puts("Could not find kernel image!\n"); goto error; } - base_ptr = load_zimage ((void*)os_data, os_len, +#ifdef CONFIG_CMD_ZBOOT + base_ptr = load_zimage((void *)os_data, os_len, images->rd_start, images->rd_end - images->rd_start, 0); +#endif if (NULL == base_ptr) { - printf ("## Kernel loading failed ...\n"); + printf("## Kernel loading failed ...\n"); goto error; } #ifdef DEBUG - printf ("## Transferring control to Linux (at address %08x) ...\n", + printf("## Transferring control to Linux (at address %08x) ...\n", (u32)base_ptr); #endif diff --git a/arch/x86/lib/gcc.c b/arch/x86/lib/gcc.c new file mode 100644 index 0000000000..4043431eca --- /dev/null +++ b/arch/x86/lib/gcc.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or later of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifdef __GNUC__ + +/* + * GCC's libgcc handling is quite broken. While the libgcc functions + * are always regparm(0) the code that calls them uses whatever the + * compiler call specifies. Therefore we need a wrapper around those + * functions. See gcc bug PR41055 for more information. + */ +#define WRAP_LIBGCC_CALL(type, name) \ + type __normal_##name(type a, type b) __attribute__((regparm(0))); \ + type __wrap_##name(type a, type b); \ + type __wrap_##name(type a, type b) { return __normal_##name(a, b); } + +WRAP_LIBGCC_CALL(long long, __divdi3) +WRAP_LIBGCC_CALL(unsigned long long, __udivdi3) +WRAP_LIBGCC_CALL(long long, __moddi3) +WRAP_LIBGCC_CALL(unsigned long long, __umoddi3) + +#endif diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index 04a9c79f9f..76fbe9dc7f 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -56,8 +56,8 @@ struct irq_action { }; static struct irq_action irq_handlers[CONFIG_SYS_NUM_IRQS] = { {0} }; -static int spurious_irq_cnt = 0; -static int spurious_irq = 0; +static int spurious_irq_cnt; +static int spurious_irq; void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg) { @@ -70,10 +70,10 @@ void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg) if (irq_handlers[irq].handler != NULL) printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", - (ulong) handler, - (ulong) irq_handlers[irq].handler); + (ulong) handler, + (ulong) irq_handlers[irq].handler); - status = disable_interrupts (); + status = disable_interrupts(); irq_handlers[irq].handler = handler; irq_handlers[irq].arg = arg; @@ -96,7 +96,7 @@ void irq_free_handler(int irq) return; } - status = disable_interrupts (); + status = disable_interrupts(); mask_irq(irq); @@ -141,14 +141,14 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int irq; printf("Spurious IRQ: %u, last unknown IRQ: %d\n", - spurious_irq_cnt, spurious_irq); + spurious_irq_cnt, spurious_irq); - printf ("Interrupt-Information:\n"); - printf ("Nr Routine Arg Count\n"); + printf("Interrupt-Information:\n"); + printf("Nr Routine Arg Count\n"); for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) { if (irq_handlers[irq].handler != NULL) { - printf ("%02d %08lx %08lx %d\n", + printf("%02d %08lx %08lx %d\n", irq, (ulong)irq_handlers[irq].handler, (ulong)irq_handlers[irq].arg, diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c index 2caae208eb..5dac4989fe 100644 --- a/arch/x86/lib/pcat_interrupts.c +++ b/arch/x86/lib/pcat_interrupts.c @@ -76,7 +76,7 @@ int interrupt_init(void) * Enable cascaded interrupts by unmasking the cascade IRQ pin of * the master PIC */ - unmask_irq (2); + unmask_irq(2); enable_interrupts(); diff --git a/arch/x86/lib/pcat_timer.c b/arch/x86/lib/pcat_timer.c index f2a54223af..6b3db69447 100644 --- a/arch/x86/lib/pcat_timer.c +++ b/arch/x86/lib/pcat_timer.c @@ -30,7 +30,7 @@ #define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */ #define TIMER2_VALUE 0x0a8e /* 440Hz */ -static int timer_init_done = 0; +static int timer_init_done; int timer_init(void) { @@ -42,18 +42,18 @@ int timer_init(void) * (to stasrt a beep: write 3 to port 0x61, * to stop it again: write 0) */ - outb (PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2, - PIT_BASE + PIT_COMMAND); - outb (TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0); - outb (TIMER0_VALUE >> 8, PIT_BASE + PIT_T0); + outb(PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2, + PIT_BASE + PIT_COMMAND); + outb(TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0); + outb(TIMER0_VALUE >> 8, PIT_BASE + PIT_T0); - outb (PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, - PIT_BASE + PIT_COMMAND); - outb (TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2); - outb (TIMER2_VALUE >> 8, PIT_BASE + PIT_T2); + outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, + PIT_BASE + PIT_COMMAND); + outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2); + outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2); - irq_install_handler (0, timer_isr, NULL); - unmask_irq (0); + irq_install_handler(0, timer_isr, NULL); + unmask_irq(0); timer_init_done = 1; @@ -64,21 +64,20 @@ static u16 read_pit(void) { u8 low; - outb (PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND); - low = inb (PIT_BASE + PIT_T0); + outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND); + low = inb(PIT_BASE + PIT_T0); - return ((inb (PIT_BASE + PIT_T0) << 8) | low); + return (inb(PIT_BASE + PIT_T0) << 8) | low; } /* this is not very exact */ -void __udelay (unsigned long usec) +void __udelay(unsigned long usec) { int counter; int wraps; - if (timer_init_done) - { - counter = read_pit (); + if (timer_init_done) { + counter = read_pit(); wraps = usec / 1000; usec = usec % 1000; @@ -92,7 +91,7 @@ void __udelay (unsigned long usec) } while (1) { - int new_count = read_pit (); + int new_count = read_pit(); if (((new_count < usec) && !wraps) || wraps < 0) break; diff --git a/arch/x86/lib/pci.c b/arch/x86/lib/pci.c index 593a7db75f..71878dd7dc 100644 --- a/arch/x86/lib/pci.c +++ b/arch/x86/lib/pci.c @@ -42,11 +42,13 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) u16 device; u32 class_code; + u32 pci_data; + hose = pci_bus_to_hose(PCI_BUS(dev)); -#if 0 - printf("pci_shadow_rom() asked to shadow device %x to %x\n", + + debug("pci_shadow_rom() asked to shadow device %x to %x\n", dev, (u32)dest); -#endif + pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); pci_read_config_word(dev, PCI_DEVICE_ID, &device); pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_code); @@ -67,7 +69,7 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) return -1; } - size = (~(addr_reg&PCI_ROM_ADDRESS_MASK))+1; + size = (~(addr_reg&PCI_ROM_ADDRESS_MASK)) + 1; debug("ROM is %d bytes\n", size); @@ -80,27 +82,25 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) |PCI_ROM_ADDRESS_ENABLE); - for (i=rom_addr;i<rom_addr+size; i+=512) { - - + for (i = rom_addr; i < rom_addr + size; i += 512) { if (readw(i) == 0xaa55) { - u32 pci_data; #ifdef PCI_ROM_SCAN_VERBOSE printf("ROM signature found\n"); #endif - pci_data = readw(0x18+i); + pci_data = readw(0x18 + i); pci_data += i; - if (0==memcmp((void*)pci_data, "PCIR", 4)) { + if (0 == memcmp((void *)pci_data, "PCIR", 4)) { #ifdef PCI_ROM_SCAN_VERBOSE - printf("Fount PCI rom image at offset %d\n", i-rom_addr); + printf("Fount PCI rom image at offset %d\n", + i - rom_addr); printf("Vendor %04x device %04x class %06x\n", - readw(pci_data+4), readw(pci_data+6), - readl(pci_data+0x0d)&0xffffff); + readw(pci_data + 4), readw(pci_data + 6), + readl(pci_data + 0x0d) & 0xffffff); printf("%s\n", - (readw(pci_data+0x15) &0x80)? - "Last image":"More images follow"); - switch (readb(pci_data+0x14)) { + (readw(pci_data + 0x15) & 0x80) ? + "Last image" : "More images follow"); + switch (readb(pci_data + 0x14)) { case 0: printf("X86 code\n"); break; @@ -111,35 +111,38 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) printf("PARISC code\n"); break; } - printf("Image size %d\n", readw(pci_data+0x10) * 512); + printf("Image size %d\n", + readw(pci_data + 0x10) * 512); #endif - /* FixMe: I think we should compare the class code - * bytes as well but I have no reference on the - * exact order of these bytes in the PCI ROM header */ - if (readw(pci_data+4) == vendor && - readw(pci_data+6) == device && - /* (readl(pci_data+0x0d)&0xffffff) == class_code && */ - readb(pci_data+0x14) == 0 /* x86 code image */ ) { + /* + * FixMe: I think we should compare the class + * code bytes as well but I have no reference + * on the exact order of these bytes in the PCI + * ROM header + */ + if (readw(pci_data + 4) == vendor && + readw(pci_data + 6) == device && + readb(pci_data + 0x14) == 0) { #ifdef PCI_ROM_SCAN_VERBOSE - printf("Suitable ROM image found, copying\n"); + printf("Suitable ROM image found\n"); #endif - memmove(dest, (void*)rom_addr, readw(pci_data+0x10) * 512); + memmove(dest, (void *)rom_addr, + readw(pci_data + 0x10) * 512); res = 0; break; } - if (readw(pci_data+0x15) &0x80) { + + if (readw(pci_data + 0x15) & 0x80) break; - } } } } #ifdef PCI_ROM_SCAN_VERBOSE - if (res) { + if (res) printf("No suitable image found\n"); - } #endif /* disable PAR register and PCI device ROM address devocer */ pci_remove_rom_window(hose, rom_addr); @@ -148,3 +151,38 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) return res; } + +#ifdef PCI_BIOS_DEBUG + +void print_bios_bios_stat(void) +{ + printf("16 bit functions:\n"); + printf("pci_bios_present: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_present)); + printf("pci_bios_find_device: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_find_device)); + printf("pci_bios_find_class: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_find_class)); + printf("pci_bios_generate_special_cycle: %d\n", + RELOC_16_LONG(0xf000, + num_pci_bios_generate_special_cycle)); + printf("pci_bios_read_cfg_byte: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_byte)); + printf("pci_bios_read_cfg_word: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_word)); + printf("pci_bios_read_cfg_dword: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_read_cfg_dword)); + printf("pci_bios_write_cfg_byte: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_byte)); + printf("pci_bios_write_cfg_word: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_word)); + printf("pci_bios_write_cfg_dword: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_write_cfg_dword)); + printf("pci_bios_get_irq_routing: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_get_irq_routing)); + printf("pci_bios_set_irq: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_set_irq)); + printf("pci_bios_unknown_function: %d\n", + RELOC_16_LONG(0xf000, num_pci_bios_unknown_function)); +} +#endif diff --git a/arch/x86/lib/pci_type1.c b/arch/x86/lib/pci_type1.c index da1d3566ad..a25fa051d5 100644 --- a/arch/x86/lib/pci_type1.c +++ b/arch/x86/lib/pci_type1.c @@ -29,7 +29,7 @@ #include <asm/io.h> #include <pci.h> -#define cfg_read(val, addr, op) *val = op((int)(addr)) +#define cfg_read(val, addr, op) (*val = op((int)(addr))) #define cfg_write(val, addr, op) op((val), (int)(addr)) #define TYPE1_PCI_OP(rw, size, type, op, mask) \ @@ -42,7 +42,6 @@ type1_##rw##_config_##size(struct pci_controller *hose, \ return 0; \ } - TYPE1_PCI_OP(read, byte, u8 *, inb, 3) TYPE1_PCI_OP(read, word, u16 *, inw, 2) TYPE1_PCI_OP(read, dword, u32 *, inl, 0) @@ -51,7 +50,11 @@ TYPE1_PCI_OP(write, byte, u8, outb, 3) TYPE1_PCI_OP(write, word, u16, outw, 2) TYPE1_PCI_OP(write, dword, u32, outl, 0) -void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) +/* bus mapping constants (used for PCI core initialization) */ +#define PCI_REG_ADDR 0x00000cf8 +#define PCI_REG_DATA 0x00000cfc + +void pci_setup_type1(struct pci_controller *hose) { pci_set_ops(hose, type1_read_config_byte, @@ -61,6 +64,6 @@ void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) type1_write_config_word, type1_write_config_dword); - hose->cfg_addr = (unsigned int *) cfg_addr; - hose->cfg_data = (unsigned char *) cfg_data; + hose->cfg_addr = (unsigned int *)PCI_REG_ADDR; + hose->cfg_data = (unsigned char *)PCI_REG_DATA; } diff --git a/arch/x86/lib/realmode.c b/arch/x86/lib/realmode.c index 6aa0f23a1a..75511b2bdf 100644 --- a/arch/x86/lib/realmode.c +++ b/arch/x86/lib/realmode.c @@ -26,15 +26,12 @@ #include <asm/ptrace.h> #include <asm/realmode.h> -#define REALMODE_MAILBOX ((char*)0xe00) - -extern ulong __realmode_start; -extern ulong __realmode_size; -extern char realmode_enter; +#define REALMODE_MAILBOX ((char *)0xe00) int realmode_setup(void) { - ulong realmode_start = (ulong)&__realmode_start + gd->reloc_off; + /* The realmode section is not relocated and still in the ROM. */ + ulong realmode_start = (ulong)&__realmode_start; ulong realmode_size = (ulong)&__realmode_size; /* copy the realmode switch code */ @@ -63,15 +60,14 @@ int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out) in->eip = off; in->xcs = seg; - if (3>(in->esp & 0xffff)) { + if ((in->esp & 0xffff) < 4) printf("Warning: entering realmode with sp < 4 will fail\n"); - } memcpy(REALMODE_MAILBOX, in, sizeof(struct pt_regs)); asm("wbinvd\n"); __asm__ volatile ( - "lcall $0x20,%0\n" : : "i" (&realmode_enter) ); + "lcall $0x20,%0\n" : : "i" (&realmode_enter)); asm("wbinvd\n"); memcpy(out, REALMODE_MAILBOX, sizeof(struct pt_regs)); @@ -79,9 +75,10 @@ int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out) return out->eax; } - -/* This code is supposed to access a realmode interrupt - * it does currently not work for me */ +/* + * This code is supposed to access a realmode interrupt + * it does currently not work for me + */ int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out) { /* place two instructions at 0x700 */ @@ -92,5 +89,5 @@ int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out) enter_realmode(0x00, 0x700, in, out); - return out->eflags&1; + return out->eflags & 0x00000001; } diff --git a/arch/x86/lib/string.c b/arch/x86/lib/string.c new file mode 100644 index 0000000000..f2ea7e4e33 --- /dev/null +++ b/arch/x86/lib/string.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc. + * This file is part of the GNU C Library. + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* From glibc-2.14, sysdeps/i386/memset.c */ + +#include <compiler.h> +#include <asm/string.h> +#include <linux/types.h> + +typedef uint32_t op_t; + +void *memset(void *dstpp, int c, size_t len) +{ + int d0; + unsigned long int dstp = (unsigned long int) dstpp; + + /* This explicit register allocation improves code very much indeed. */ + register op_t x asm("ax"); + + x = (unsigned char) c; + + /* Clear the direction flag, so filling will move forward. */ + asm volatile("cld"); + + /* This threshold value is optimal. */ + if (len >= 12) { + /* Fill X with four copies of the char we want to fill with. */ + x |= (x << 8); + x |= (x << 16); + + /* Adjust LEN for the bytes handled in the first loop. */ + len -= (-dstp) % sizeof(op_t); + + /* + * There are at least some bytes to set. No need to test for + * LEN == 0 in this alignment loop. + */ + + /* Fill bytes until DSTP is aligned on a longword boundary. */ + asm volatile( + "rep\n" + "stosb" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) : + "memory"); + + /* Fill longwords. */ + asm volatile( + "rep\n" + "stosl" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" (len / sizeof(op_t)), "a" (x) : + "memory"); + len %= sizeof(op_t); + } + + /* Write the last few bytes. */ + asm volatile( + "rep\n" + "stosb" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" (len), "a" (x) : + "memory"); + + return dstpp; +} diff --git a/arch/x86/lib/timer.c b/arch/x86/lib/timer.c index 8b1bde708c..fd7032e92c 100644 --- a/arch/x86/lib/timer.c +++ b/arch/x86/lib/timer.c @@ -35,15 +35,15 @@ struct timer_isr_function { timer_fnc_t *isr_func; }; -static struct timer_isr_function *first_timer_isr = NULL; -static volatile unsigned long system_ticks = 0; +static struct timer_isr_function *first_timer_isr; +static unsigned long system_ticks; /* * register_timer_isr() allows multiple architecture and board specific * functions to be called every millisecond. Keep the execution time of * each function as low as possible */ -int register_timer_isr (timer_fnc_t *isr_func) +int register_timer_isr(timer_fnc_t *isr_func) { struct timer_isr_function *new_func; struct timer_isr_function *temp; @@ -61,7 +61,7 @@ int register_timer_isr (timer_fnc_t *isr_func) * Don't allow timer interrupts while the * linked list is being modified */ - flag = disable_interrupts (); + flag = disable_interrupts(); if (first_timer_isr == NULL) { first_timer_isr = new_func; @@ -73,7 +73,7 @@ int register_timer_isr (timer_fnc_t *isr_func) } if (flag) - enable_interrupts (); + enable_interrupts(); return 0; } @@ -89,12 +89,12 @@ void timer_isr(void *unused) /* Execute each registered function */ while (temp != NULL) { - temp->isr_func (); + temp->isr_func(); temp = temp->next; } } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { - return (system_ticks - base); + return system_ticks - base; } diff --git a/arch/x86/lib/video.c b/arch/x86/lib/video.c index 0efcf3f453..3d6b24d620 100644 --- a/arch/x86/lib/video.c +++ b/arch/x86/lib/video.c @@ -123,7 +123,7 @@ static void __video_putc(const char c, int *x, int *y) static void video_putc(const char c) { - int x,y,pos; + int x, y, pos; x = orig_x; y = orig_y; @@ -142,7 +142,7 @@ static void video_putc(const char c) static void video_puts(const char *s) { - int x,y,pos; + int x, y, pos; char c; x = orig_x; @@ -187,7 +187,7 @@ int video_init(void) printf("pos %x %d %d\n", pos, orig_x, orig_y); #endif if (orig_y > lines) - orig_x = orig_y =0; + orig_x = orig_y = 0; memset(&vga_dev, 0, sizeof(vga_dev)); strcpy(vga_dev.name, "vga"); diff --git a/arch/x86/lib/video_bios.c b/arch/x86/lib/video_bios.c index 7574f771fd..1e06759d9e 100644 --- a/arch/x86/lib/video_bios.c +++ b/arch/x86/lib/video_bios.c @@ -28,86 +28,55 @@ #include <asm/realmode.h> #include <asm/io.h> #include <asm/pci.h> +#include "bios.h" #undef PCI_BIOS_DEBUG #undef VGA_BIOS_DEBUG #ifdef VGA_BIOS_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) +#define PRINTF(fmt, args...) printf(fmt, ##args) #else -#define PRINTF(fmt,args...) +#define PRINTF(fmt, args...) #endif -#ifdef CONFIG_PCI +#define PCI_CLASS_VIDEO 3 +#define PCI_CLASS_VIDEO_STD 0 +#define PCI_CLASS_VIDEO_PROG_IF_VGA 0 -#ifdef PCI_BIOS_DEBUG -#define RELOC_16(seg, off) *(u32*)(seg << 4 | (u32)&off) -extern u32 num_pci_bios_present; -extern u32 num_pci_bios_find_device; -extern u32 num_pci_bios_find_class; -extern u32 num_pci_bios_generate_special_cycle; -extern u32 num_pci_bios_read_cfg_byte; -extern u32 num_pci_bios_read_cfg_word; -extern u32 num_pci_bios_read_cfg_dword; -extern u32 num_pci_bios_write_cfg_byte; -extern u32 num_pci_bios_write_cfg_word; -extern u32 num_pci_bios_write_cfg_dword; -extern u32 num_pci_bios_get_irq_routing; -extern u32 num_pci_bios_set_irq; -extern u32 num_pci_bios_unknown_function; - -void print_bios_bios_stat(void) -{ - printf("16 bit functions:\n"); - printf("pci_bios_present: %d\n", RELOC_16(0xf000, num_pci_bios_present)); - printf("pci_bios_find_device: %d\n", RELOC_16(0xf000, num_pci_bios_find_device)); - printf("pci_bios_find_class: %d\n", RELOC_16(0xf000, num_pci_bios_find_class)); - printf("pci_bios_generate_special_cycle: %d\n", RELOC_16(0xf000, num_pci_bios_generate_special_cycle)); - printf("pci_bios_read_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_byte)); - printf("pci_bios_read_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_word)); - printf("pci_bios_read_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_dword)); - printf("pci_bios_write_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_byte)); - printf("pci_bios_write_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_word)); - printf("pci_bios_write_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_dword)); - printf("pci_bios_get_irq_routing: %d\n", RELOC_16(0xf000, num_pci_bios_get_irq_routing)); - printf("pci_bios_set_irq: %d\n", RELOC_16(0xf000, num_pci_bios_set_irq)); - printf("pci_bios_unknown_function: %d\n", RELOC_16(0xf000, num_pci_bios_unknown_function)); - -} -#endif - -#ifdef CONFIG_VIDEO - -#define PCI_CLASS_VIDEO 3 -#define PCI_CLASS_VIDEO_STD 0 -#define PCI_CLASS_VIDEO_PROG_IF_VGA 0 - -static struct pci_device_id supported[] = { +DEFINE_PCI_DEVICE_TABLE(supported) = { {PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID}, {} }; static u32 probe_pci_video(void) { - pci_dev_t devbusfn; + struct pci_controller *hose; + pci_dev_t devbusfn = pci_find_devices(supported, 0); - if ((devbusfn = pci_find_devices(supported, 0) != -1)) { + if ((devbusfn != -1)) { u32 old; u32 addr; /* PCI video device detected */ printf("Found PCI VGA device at %02x.%02x.%x\n", - PCI_BUS(devbusfn), PCI_DEV(devbusfn), PCI_FUNC(devbusfn)); + PCI_BUS(devbusfn), + PCI_DEV(devbusfn), + PCI_FUNC(devbusfn)); /* Enable I/O decoding as well, PCI viudeo boards * support I/O accesses, but they provide no * bar register for this since the ports are fixed. */ - pci_write_config_word(devbusfn, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER); + pci_write_config_word(devbusfn, + PCI_COMMAND, + PCI_COMMAND_MEMORY | + PCI_COMMAND_IO | + PCI_COMMAND_MASTER); /* Test the ROM decoder, do the device support a rom? */ pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old); - pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK); + pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, + (u32)PCI_ROM_ADDRESS_MASK); pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr); pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old); @@ -117,13 +86,14 @@ static u32 probe_pci_video(void) } /* device have a rom */ - if (pci_shadow_rom(devbusfn, (void*)0xc0000)) { + if (pci_shadow_rom(devbusfn, (void *)0xc0000)) { printf("Shadowing of PCI VGA BIOS failed\n"); return 0; } /* Now enable lagacy VGA port access */ - if (pci_enable_legacy_video_ports(pci_bus_to_hose(PCI_BUS(devbusfn)))) { + hose = pci_bus_to_hose(PCI_BUS(devbusfn)); + if (pci_enable_legacy_video_ports(hose)) { printf("PCI VGA enable failed\n"); return 0; } @@ -131,7 +101,7 @@ static u32 probe_pci_video(void) /* return the pci device info, that we'll need later */ return PCI_BUS(devbusfn) << 8 | - PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn)&7); + PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn) & 7); } return 0; @@ -142,13 +112,17 @@ static int probe_isa_video(void) u32 ptr; char *buf; - if (0 == (ptr = isa_map_rom(0xc0000, 0x8000))) { + ptr = isa_map_rom(0xc0000, 0x8000); + + if (!ptr) return -1; - } - if (NULL == (buf=malloc(0x8000))) { + + buf = malloc(0x8000); + if (!buf) { isa_unmap_rom(ptr); return -1; } + if (readw(ptr) != 0xaa55) { free(buf); isa_unmap_rom(ptr); @@ -156,9 +130,9 @@ static int probe_isa_video(void) } /* shadow the rom */ - memcpy(buf, (void*)ptr, 0x8000); + memcpy(buf, (void *)ptr, 0x8000); isa_unmap_rom(ptr); - memcpy((void*)0xc0000, buf, 0x8000); + memcpy((void *)0xc0000, buf, 0x8000); free(buf); @@ -168,35 +142,35 @@ static int probe_isa_video(void) int video_bios_init(void) { struct pt_regs regs; + int size; + int i; + u8 sum; /* clear the video bios area in case we warmbooted */ - memset((void*)0xc0000, 0, 0x8000); + memset((void *)0xc0000, 0, 0x8000); memset(®s, 0, sizeof(struct pt_regs)); - if (probe_isa_video()) { + if (probe_isa_video()) /* No ISA board found, try the PCI bus */ regs.eax = probe_pci_video(); - } /* Did we succeed in mapping any video bios */ if (readw(0xc0000) == 0xaa55) { - int size; - int i; - u8 sum; - PRINTF("Found video bios signature\n"); - size = 512*readb(0xc0002); + size = readb(0xc0002) * 512; PRINTF("size %d\n", size); - sum=0; - for (i=0;i<size;i++) { + sum = 0; + + for (i = 0; i < size; i++) sum += readb(0xc0000 + i); - } - PRINTF("Checksum is %sOK\n",sum?"NOT ":""); - if (sum) { + + PRINTF("Checksum is %sOK\n", sum ? "NOT " : ""); + + if (sum) return 1; - } - /* some video bioses (ATI Mach64) seem to think that + /* + * Some video bioses (ATI Mach64) seem to think that * the original int 10 handler is always at * 0xf000:0xf065 , place an iret instruction there */ @@ -205,18 +179,18 @@ int video_bios_init(void) regs.esp = 0x8000; regs.xss = 0x2000; enter_realmode(0xc000, 3, ®s, ®s); + PRINTF("INT 0x10 vector after: %04x:%04x\n", readw(0x42), readw(0x40)); - PRINTF("BIOS returned %scarry\n", regs.eflags & 1?"":"NOT "); + PRINTF("BIOS returned %scarry\n", + regs.eflags & 0x00000001 ? "" : "NOT "); #ifdef PCI_BIOS_DEBUG print_bios_bios_stat(); #endif - return (regs.eflags & 1); + return regs.eflags & 0x00000001; } return 1; } -#endif -#endif diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index d2dd6fd449..8b42b5cafa 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -45,11 +45,11 @@ * 0x8000-0x8FFF Stack and heap * 0x9000-0x90FF Kernel command line */ -#define DEFAULT_SETUP_BASE 0x90000 -#define COMMAND_LINE_OFFSET 0x9000 -#define HEAP_END_OFFSET 0x8e00 +#define DEFAULT_SETUP_BASE 0x90000 +#define COMMAND_LINE_OFFSET 0x9000 +#define HEAP_END_OFFSET 0x8e00 -#define COMMAND_LINE_SIZE 2048 +#define COMMAND_LINE_SIZE 2048 static void build_command_line(char *command_line, int auto_boot) { @@ -60,23 +60,20 @@ static void build_command_line(char *command_line, int auto_boot) env_command_line = getenv("bootargs"); /* set console= argument if we use a serial console */ - if (NULL == strstr(env_command_line, "console=")) { - if (0==strcmp(getenv("stdout"), "serial")) { + if (!strstr(env_command_line, "console=")) { + if (!strcmp(getenv("stdout"), "serial")) { /* We seem to use serial console */ sprintf(command_line, "console=ttyS0,%s ", - getenv("baudrate")); + getenv("baudrate")); } } - if (auto_boot) { + if (auto_boot) strcat(command_line, "auto "); - } - if (NULL != env_command_line) { + if (env_command_line) strcat(command_line, env_command_line); - } - printf("Kernel command line: \"%s\"\n", command_line); } @@ -90,14 +87,16 @@ void *load_zimage(char *image, unsigned long kernel_size, int bootproto; int big_image; void *load_address; + struct setup_header *hdr; - struct setup_header *hdr = (struct setup_header *)(image + SETUP_SECTS_OFF); + hdr = (struct setup_header *)(image + SETUP_SECTS_OFF); - setup_base = (void*)DEFAULT_SETUP_BASE; /* base address for real-mode segment */ + /* base address for real-mode segment */ + setup_base = (void *)DEFAULT_SETUP_BASE; if (KERNEL_MAGIC != hdr->boot_flag) { printf("Error: Invalid Boot Flag (found 0x%04x, expected 0x%04x)\n", - hdr->boot_flag, KERNEL_MAGIC); + hdr->boot_flag, KERNEL_MAGIC); return 0; } else { printf("Valid Boot Flag\n"); @@ -124,43 +123,50 @@ void *load_zimage(char *image, unsigned long kernel_size, printf("Setup Size = 0x%8.8lx\n", (ulong)setup_size); - if (setup_size > SETUP_MAX_SIZE) { + if (setup_size > SETUP_MAX_SIZE) printf("Error: Setup is too large (%d bytes)\n", setup_size); - } /* Determine image type */ - big_image = (bootproto >= 0x0200) && (hdr->loadflags & BIG_KERNEL_FLAG); + big_image = (bootproto >= 0x0200) && + (hdr->loadflags & BIG_KERNEL_FLAG); /* Determine load address */ - load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR : ZIMAGE_LOAD_ADDR); + load_address = (void *)(big_image ? + BZIMAGE_LOAD_ADDR : + ZIMAGE_LOAD_ADDR); /* load setup */ - printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n", (ulong)setup_base, setup_size); + printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n", + (ulong)setup_base, setup_size); memmove(setup_base, image, setup_size); printf("Using boot protocol version %x.%02x\n", (bootproto & 0xff00) >> 8, bootproto & 0xff); if (bootproto == 0x0100) { + *(u16 *)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; + *(u16 *)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; - *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; - *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; - - /* A very old kernel MUST have its real-mode code - * loaded at 0x90000 */ - + /* + * A very old kernel MUST have its real-mode code + * loaded at 0x90000 + */ if ((u32)setup_base != 0x90000) { /* Copy the real-mode kernel */ - memmove((void*)0x90000, setup_base, setup_size); + memmove((void *)0x90000, setup_base, setup_size); + /* Copy the command line */ - memmove((void*)0x99000, setup_base+COMMAND_LINE_OFFSET, - COMMAND_LINE_SIZE); + memmove((void *)0x99000, + setup_base + COMMAND_LINE_OFFSET, + COMMAND_LINE_SIZE); - setup_base = (void*)0x90000; /* Relocated */ + /* Relocated */ + setup_base = (void *)0x90000; } /* It is recommended to clear memory up to the 32K mark */ - memset((void*)0x90000 + setup_size, 0, SETUP_MAX_SIZE-setup_size); + memset((void *)0x90000 + setup_size, 0, + SETUP_MAX_SIZE-setup_size); } /* We are now setting up the real-mode version of the header */ @@ -170,8 +176,9 @@ void *load_zimage(char *image, unsigned long kernel_size, hdr->type_of_loader = 8; if (hdr->setup_sects >= 15) - printf("Linux kernel version %s\n", (char *) - (setup_base + (hdr->kernel_version + 0x200))); + printf("Linux kernel version %s\n", + (char *)(setup_base + + (hdr->kernel_version + 0x200))); else printf("Setup Sectors < 15 - Cannot print kernel version.\n"); @@ -193,8 +200,8 @@ void *load_zimage(char *image, unsigned long kernel_size, hdr->cmd_line_ptr = (u32)setup_base + COMMAND_LINE_OFFSET; } else if (bootproto >= 0x0200) { - *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; - *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; + *(u16 *)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; + *(u16 *)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; hdr->setup_move_size = 0x9100; } @@ -221,8 +228,8 @@ void *load_zimage(char *image, unsigned long kernel_size, /* build command line at COMMAND_LINE_OFFSET */ build_command_line(setup_base + COMMAND_LINE_OFFSET, auto_boot); - printf("Loading %czImage at address 0x%08x (%ld bytes)\n", big_image ? 'b' : ' ', - (u32)load_address, kernel_size); + printf("Loading %czImage at address 0x%08x (%ld bytes)\n", + big_image ? 'b' : ' ', (u32)load_address, kernel_size); memmove(load_address, image + setup_size, kernel_size); @@ -241,10 +248,11 @@ void boot_zimage(void *setup_base) regs.xss = regs.xds; regs.esp = 0x9000; regs.eflags = 0; - enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s, ®s); + enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s, + ®s); } -int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { void *base_ptr; void *bzImage_addr = NULL; @@ -270,12 +278,12 @@ int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bzImage_size = simple_strtoul(argv[2], NULL, 16); /* Lets look for*/ - base_ptr = load_zimage (bzImage_addr, bzImage_size, 0, 0, 0); + base_ptr = load_zimage(bzImage_addr, bzImage_size, 0, 0, 0); - if (NULL == base_ptr) { - printf ("## Kernel loading failed ...\n"); + if (!base_ptr) { + printf("## Kernel loading failed ...\n"); } else { - printf ("## Transferring control to Linux (at address %08x) ...\n", + printf("## Transferring control to Linux (at address %08x) ...\n", (u32)base_ptr); /* we assume that the kernel is in place */ |
