diff options
Diffstat (limited to 'arch/x86/include')
25 files changed, 946 insertions, 144 deletions
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059131..4e8987ce5c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/arch-ivybridge/microcode.h index b868283761..67f32cc38f 100644 --- a/arch/x86/include/asm/arch-ivybridge/microcode.h +++ b/arch/x86/include/asm/arch-ivybridge/microcode.h @@ -7,9 +7,6 @@ #ifndef __ASM_ARCH_MICROCODE_H #define __ASM_ARCH_MICROCODE_H -/* Length of the public header on Intel microcode blobs */ -#define UCODE_HEADER_LEN 0x30 - #ifndef __ASSEMBLY__ /** diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h index 7b4f2e790b..d2f9006093 100644 --- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -37,7 +37,6 @@ #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_POWER_CTL 0x1fc #define MSR_PKGC3_IRTL 0x60a #define MSR_PKGC6_IRTL 0x60b @@ -63,7 +62,6 @@ #define MSR_PP1_CURRENT_CONFIG 0x602 #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ -#define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_SKU 0x614 #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index ceb583e3f0..6dd02fd31e 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -21,6 +21,13 @@ /* Port 0x03: Host Bridge Message Port Registers */ +/* Host Miscellaneous Controls 2 */ +#define HMISC2 0x03 + +#define HMISC2_SEGE 0x00000002 +#define HMISC2_SEGF 0x00000004 +#define HMISC2_SEGAB 0x00000010 + /* Host Memory I/O Boundary */ #define HM_BOUND 0x08 diff --git a/arch/x86/include/asm/arch-queensbay/device.h b/arch/x86/include/asm/arch-queensbay/device.h new file mode 100644 index 0000000000..953b48f15c --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/device.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _QUEENSBAY_DEVICE_H_ +#define _QUEENSBAY_DEVICE_H_ + +#include <pci.h> + +/* TunnelCreek PCI Devices */ +#define TNC_HOST_BRIDGE_DEV 0 +#define TNC_HOST_BRIDGE_FUNC 0 +#define TNC_IGD_DEV 2 +#define TNC_IGD_FUNC 0 +#define TNC_SDVO_DEV 3 +#define TNC_SDVO_FUNC 0 +#define TNC_PCIE0_DEV 23 +#define TNC_PCIE0_FUNC 0 +#define TNC_PCIE1_DEV 24 +#define TNC_PCIE1_FUNC 0 +#define TNC_PCIE2_DEV 25 +#define TNC_PCIE2_FUNC 0 +#define TNC_PCIE3_DEV 26 +#define TNC_PCIE3_FUNC 0 +#define TNC_HDA_DEV 27 +#define TNC_HDA_FUNC 0 +#define TNC_LPC_DEV 31 +#define TNC_LPC_FUNC 0 + +#define TNC_HOST_BRIDGE \ + PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC) +#define TNC_IGD \ + PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC) +#define TNC_SDVO \ + PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC) +#define TNC_PCIE0 \ + PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC) +#define TNC_PCIE1 \ + PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC) +#define TNC_PCIE2 \ + PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC) +#define TNC_PCIE3 \ + PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC) +#define TNC_HDA \ + PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC) +#define TNC_LPC \ + PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC) + +/* Topcliff IOH PCI Devices */ +#define TCF_PCIE_PORT_DEV 0 +#define TCF_PCIE_PORT_FUNC 0 + +#define TCF_DEV_0 0 +#define TCF_PKT_HUB_FUNC 0 +#define TCF_GBE_FUNC 1 +#define TCF_GPIO_FUNC 2 + +#define TCF_DEV_2 2 +#define TCF_USB1_OHCI0_FUNC 0 +#define TCF_USB1_OHCI1_FUNC 1 +#define TCF_USB1_OHCI2_FUNC 2 +#define TCF_USB1_EHCI_FUNC 3 +#define TCF_USB_DEVICE_FUNC 4 + +#define TCF_DEV_4 4 +#define TCF_SDIO0_FUNC 0 +#define TCF_SDIO1_FUNC 1 + +#define TCF_DEV_6 6 +#define TCF_SATA_FUNC 0 + +#define TCF_DEV_8 8 +#define TCF_USB2_OHCI0_FUNC 0 +#define TCF_USB2_OHCI1_FUNC 1 +#define TCF_USB2_OHCI2_FUNC 2 +#define TCF_USB2_EHCI_FUNC 3 + +#define TCF_DEV_10 10 +#define TCF_DMA1_FUNC 0 +#define TCF_UART0_FUNC 1 +#define TCF_UART1_FUNC 2 +#define TCF_UART2_FUNC 3 +#define TCF_UART3_FUNC 4 + +#define TCF_DEV_12 12 +#define TCF_DMA2_FUNC 0 +#define TCF_SPI_FUNC 1 +#define TCF_I2C_FUNC 2 +#define TCF_CAN_FUNC 3 +#define TCF_1588_FUNC 4 + +#endif /* _QUEENSBAY_DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-queensbay/irq.h b/arch/x86/include/asm/arch-queensbay/irq.h new file mode 100644 index 0000000000..e7f861623e --- /dev/null +++ b/arch/x86/include/asm/arch-queensbay/irq.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ARCH_IRQ_H_ +#define _ARCH_IRQ_H_ + +enum pci_int_pin { + INTX, + INTA, + INTB, + INTC, + INTD +}; + +enum pirq_pin { + PIRQA, + PIRQB, + PIRQC, + PIRQD, + PIRQE, + PIRQF, + PIRQG, + PIRQH +}; + +/* PIRQ link number and value conversion */ +#define LINK_V2N(link) (link - 0x60) +#define LINK_N2V(link) (link + 0x60) + +#define PIRQ_BITMAP 0xdee0 + +struct irq_info; + +/** + * board_fill_irq_info() - Board-specific irq_info fill routine + * + * This fills the irq_info table for any board-specific add-in cards. + * + * @slot: pointer to the struct irq_info that is to be filled in + * @return: number of entries were written to the struct irq_info + */ +int board_fill_irq_info(struct irq_info *slot); + +/** + * pirq_init() - Initialize platform PIRQ routing + * + * This initializes the PIRQ routing on the platform and configures all PCI + * devices' interrupt line register to a working IRQ number on the 8259 PIC. + */ +void pirq_init(void); + +#endif /* _ARCH_IRQ_H_ */ diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h index 67c5e0586c..ad9a6c4892 100644 --- a/arch/x86/include/asm/arch-queensbay/tnc.h +++ b/arch/x86/include/asm/arch-queensbay/tnc.h @@ -7,9 +7,43 @@ #ifndef _X86_ARCH_TNC_H_ #define _X86_ARCH_TNC_H_ -#include <pci.h> +/* Memory BAR Enable */ +#define MEM_BAR_EN 0x00000001 -/* PCI Configuration Space (D31:F0): LPC */ -#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) +/* LPC PCI Configuration Registers */ +#define LPC_RCBA 0xf0 + +/* Root Complex Register Block */ +struct tnc_rcba { + u32 rctl; + u32 esd; + u32 rsvd1[2]; + u32 hdd; + u32 rsvd2; + u32 hdba; + u32 rsvd3[3129]; + u32 d31ip; + u32 rsvd4[3]; + u32 d27ip; + u32 rsvd5; + u32 d02ip; + u32 rsvd6; + u32 d26ip; + u32 d25ip; + u32 d24ip; + u32 d23ip; + u32 d03ip; + u32 rsvd7[3]; + u16 d31ir; + u16 rsvd8[3]; + u16 d27ir; + u16 d26ir; + u16 d25ir; + u16 d24ir; + u16 d23ir; + u16 rsvd9[7]; + u16 d02ir; + u16 d03ir; +}; #endif /* _X86_ARCH_TNC_H_ */ diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h new file mode 100644 index 0000000000..806f787381 --- /dev/null +++ b/arch/x86/include/asm/atomic.h @@ -0,0 +1,115 @@ +#ifndef _ASM_X86_ATOMIC_H +#define _ASM_X86_ATOMIC_H + +#include <linux/compiler.h> +#include <linux/types.h> +#include <asm/processor.h> + +typedef struct { volatile int counter; } atomic_t; + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + */ + +#define ATOMIC_INIT(i) { (i) } + +/** + * atomic_read - read atomic variable + * @v: pointer of type atomic_t + * + * Atomically reads the value of @v. + */ +static inline int atomic_read(const atomic_t *v) +{ + return ACCESS_ONCE((v)->counter); +} + +/** + * atomic_set - set atomic variable + * @v: pointer of type atomic_t + * @i: required value + * + * Atomically sets the value of @v to @i. + */ +static inline void atomic_set(atomic_t *v, int i) +{ + v->counter = i; +} + +/** + * atomic_add - add integer to atomic variable + * @i: integer value to add + * @v: pointer of type atomic_t + * + * Atomically adds @i to @v. + */ +static inline void atomic_add(int i, atomic_t *v) +{ + asm volatile(LOCK_PREFIX "addl %1,%0" + : "+m" (v->counter) + : "ir" (i)); +} + +/** + * atomic_sub - subtract integer from atomic variable + * @i: integer value to subtract + * @v: pointer of type atomic_t + * + * Atomically subtracts @i from @v. + */ +static inline void atomic_sub(int i, atomic_t *v) +{ + asm volatile(LOCK_PREFIX "subl %1,%0" + : "+m" (v->counter) + : "ir" (i)); +} + +/** + * atomic_inc - increment atomic variable + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1. + */ +static inline void atomic_inc(atomic_t *v) +{ + asm volatile(LOCK_PREFIX "incl %0" + : "+m" (v->counter)); +} + +/** + * atomic_dec - decrement atomic variable + * @v: pointer of type atomic_t + * + * Atomically decrements @v by 1. + */ +static inline void atomic_dec(atomic_t *v) +{ + asm volatile(LOCK_PREFIX "decl %0" + : "+m" (v->counter)); +} + +/** + * atomic_inc_short - increment of a short integer + * @v: pointer to type int + * + * Atomically adds 1 to @v + * Returns the new value of @u + */ +static inline short int atomic_inc_short(short int *v) +{ + asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v)); + return *v; +} + +/* These are x86-specific, used by some header files */ +#define atomic_clear_mask(mask, addr) \ + asm volatile(LOCK_PREFIX "andl %0,%1" \ + : : "r" (~(mask)), "m" (*(addr)) : "memory") + +#define atomic_set_mask(mask, addr) \ + asm volatile(LOCK_PREFIX "orl %0,%1" \ + : : "r" ((unsigned)(mask)), "m" (*(addr)) \ + : "memory") + +#endif /* _ASM_X86_ATOMIC_H */ diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index c8392915f1..ebc74adbc3 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -151,6 +151,11 @@ static inline int flag_is_changeable_p(uint32_t flag) return ((f1^f2) & flag) != 0; } +static inline void mfence(void) +{ + __asm__ __volatile__("mfence" : : : "memory"); +} + /** * cpu_enable_paging_pae() - Enable PAE-paging * @@ -192,6 +197,20 @@ const char *cpu_vendor_name(int vendor); char *cpu_get_name(char *name); /** + * +* x86_cpu_get_desc() - Get a description string for an x86 CPU +* +* This uses cpu_get_name() and is suitable to use as the get_desc() method for +* the CPU uclass. +* +* @dev: Device to check (UCLASS_CPU) +* @buf: Buffer to place string +* @size: Size of string space +* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error +*/ +int x86_cpu_get_desc(struct udevice *dev, char *buf, int size); + +/** * cpu_call64() - Jump to a 64-bit Linux kernel (internal function) * * The kernel is uncompressed and the 64-bit entry point is expected to be diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index d155ce9cee..21bc63339e 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -1,43 +1,7 @@ #ifndef _ASM_X86_E820_H #define _ASM_X86_E820_H -#define E820MAP 0x2d0 /* our map */ -#define E820MAX 128 /* number of entries in E820MAP */ -/* - * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the - * constrained space in the zeropage. If we have more nodes than - * that, and if we've booted off EFI firmware, then the EFI tables - * passed us from the EFI firmware can list more nodes. Size our - * internal memory map tables to have room for these additional - * nodes, based on up to three entries per node for which the - * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT), - * plus E820MAX, allowing space for the possible duplicate E820 - * entries that might need room in the same arrays, prior to the - * call to sanitize_e820_map() to remove duplicates. The allowance - * of three memory map entries per node is "enough" entries for - * the initial hardware platform motivating this mechanism to make - * use of additional EFI map entries. Future platforms may want - * to allow more than three entries per node or otherwise refine - * this size. - */ - -/* - * Odd: 'make headers_check' complains about numa.h if I try - * to collapse the next two #ifdef lines to a single line: - * #if defined(__KERNEL__) && defined(CONFIG_EFI) - */ -#ifdef __KERNEL__ -#ifdef CONFIG_EFI -#include <linux/numa.h> -#define E820_X_MAX (E820MAX + 3 * MAX_NUMNODES) -#else /* ! CONFIG_EFI */ -#define E820_X_MAX E820MAX -#endif -#else /* ! __KERNEL__ */ -#define E820_X_MAX E820MAX -#endif - -#define E820NR 0x1e8 /* # entries in E820MAP */ +#define E820MAX 128 /* number of entries in E820MAP */ #define E820_RAM 1 #define E820_RESERVED 2 @@ -45,111 +9,18 @@ #define E820_NVS 4 #define E820_UNUSABLE 5 -/* reserved RAM used by kernel itself */ -#define E820_RESERVED_KERN 128 - #ifndef __ASSEMBLY__ #include <linux/types.h> + struct e820entry { __u64 addr; /* start of memory segment */ __u64 size; /* size of memory segment */ __u32 type; /* type of memory segment */ } __attribute__((packed)); -struct e820map { - __u32 nr_map; - struct e820entry map[E820_X_MAX]; -}; - #define ISA_START_ADDRESS 0xa0000 #define ISA_END_ADDRESS 0x100000 -#define BIOS_BEGIN 0x000a0000 -#define BIOS_END 0x00100000 - -#ifdef __KERNEL__ -/* see comment in arch/x86/kernel/e820.c */ -extern struct e820map e820; -extern struct e820map e820_saved; - -extern unsigned long pci_mem_start; -extern int e820_any_mapped(u64 start, u64 end, unsigned type); -extern int e820_all_mapped(u64 start, u64 end, unsigned type); -extern void e820_add_region(u64 start, u64 size, int type); -extern void e820_print_map(char *who); -extern int -sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, u32 *pnr_map); -extern u64 e820_update_range(u64 start, u64 size, unsigned old_type, - unsigned new_type); -extern u64 e820_remove_range(u64 start, u64 size, unsigned old_type, - int checktype); -extern void update_e820(void); -extern void e820_setup_gap(void); -extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize, - unsigned long start_addr, unsigned long long end_addr); -struct setup_data; -extern void parse_e820_ext(struct setup_data *data, unsigned long pa_data); - -#if defined(CONFIG_X86_64) || \ - (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION)) -extern void e820_mark_nosave_regions(unsigned long limit_pfn); -#else -static inline void e820_mark_nosave_regions(unsigned long limit_pfn) -{ -} -#endif - -#ifdef CONFIG_MEMTEST -extern void early_memtest(unsigned long start, unsigned long end); -#else -static inline void early_memtest(unsigned long start, unsigned long end) -{ -} -#endif - -extern unsigned long end_user_pfn; - -extern u64 find_e820_area(u64 start, u64 end, u64 size, u64 align); -extern u64 find_e820_area_size(u64 start, u64 *sizep, u64 align); -extern void reserve_early(u64 start, u64 end, char *name); -extern void reserve_early_overlap_ok(u64 start, u64 end, char *name); -extern void free_early(u64 start, u64 end); -extern void early_res_to_bootmem(u64 start, u64 end); -extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align); - -extern unsigned long e820_end_of_ram_pfn(void); -extern unsigned long e820_end_of_low_ram_pfn(void); -extern int e820_find_active_region(const struct e820entry *ei, - unsigned long start_pfn, - unsigned long last_pfn, - unsigned long *ei_startpfn, - unsigned long *ei_endpfn); -extern void e820_register_active_regions(int nid, unsigned long start_pfn, - unsigned long end_pfn); -extern u64 e820_hole_size(u64 start, u64 end); -extern void finish_e820_parsing(void); -extern void e820_reserve_resources(void); -extern void e820_reserve_resources_late(void); -extern void setup_memory_map(void); -extern char *default_machine_specific_memory_setup(void); - -/* - * Returns true iff the specified range [s,e) is completely contained inside - * the ISA region. - */ -/* -static inline bool is_ISA_range(u64 s, u64 e) -{ - return s >= ISA_START_ADDRESS && e <= ISA_END_ADDRESS; -} -*/ -#endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ -#ifdef __KERNEL__ -/* #include <linux/ioport.h> */ - -#define HIGH_MEMORY (1024*1024) -#endif /* __KERNEL__ */ - #endif /* _ASM_X86_E820_H */ diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 5ee06eb70d..4d9eac676e 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -68,6 +68,7 @@ struct arch_global_data { /* MRC training data to save for the next boot */ char *mrc_output; unsigned int mrc_output_len; + void *gdt; /* Global descriptor table */ }; #endif diff --git a/arch/x86/include/asm/ibmpc.h b/arch/x86/include/asm/ibmpc.h index c3b5187c22..678cde4c86 100644 --- a/arch/x86/include/asm/ibmpc.h +++ b/arch/x86/include/asm/ibmpc.h @@ -21,4 +21,7 @@ #define UART0_BASE 0x3f8 #define UART1_BASE 0x2f8 +#define UART0_IRQ 4 +#define UART1_IRQ 3 + #endif diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index 25abde7be6..0a75f89d95 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -38,4 +38,6 @@ extern char exception_stack[]; */ void configure_irq_trigger(int int_num, bool is_level_triggered); +void *x86_get_idt(void); + #endif diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h new file mode 100644 index 0000000000..c0930fd0c6 --- /dev/null +++ b/arch/x86/include/asm/mp.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + * + * Taken from coreboot file of the same name + */ + +#ifndef _X86_MP_H_ +#define _X86_MP_H_ + +#include <asm/atomic.h> + +typedef int (*mp_callback_t)(struct udevice *cpu, void *arg); + +/* + * A mp_flight_record details a sequence of calls for the APs to perform + * along with the BSP to coordinate sequencing. Each flight record either + * provides a barrier for each AP before calling the callback or the APs + * are allowed to perform the callback without waiting. Regardless, each + * record has the cpus_entered field incremented for each record. When + * the BSP observes that the cpus_entered matches the number of APs + * the bsp_call is called with bsp_arg and upon returning releases the + * barrier allowing the APs to make further progress. + * + * Note that ap_call() and bsp_call() can be NULL. In the NULL case the + * callback will just not be called. + */ +struct mp_flight_record { + atomic_t barrier; + atomic_t cpus_entered; + mp_callback_t ap_call; + void *ap_arg; + mp_callback_t bsp_call; + void *bsp_arg; +} __attribute__((aligned(ARCH_DMA_MINALIGN))); + +#define MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \ + { \ + .barrier = ATOMIC_INIT(barrier_), \ + .cpus_entered = ATOMIC_INIT(0), \ + .ap_call = ap_func_, \ + .ap_arg = ap_arg_, \ + .bsp_call = bsp_func_, \ + .bsp_arg = bsp_arg_, \ + } + +#define MP_FR_BLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \ + MP_FLIGHT_RECORD(0, ap_func, ap_arg, bsp_func, bsp_arg) + +#define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \ + MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg) + +/* + * The mp_params structure provides the arguments to the mp subsystem + * for bringing up APs. + * + * At present this is overkill for U-Boot, but it may make it easier to add + * SMM support. + */ +struct mp_params { + int num_cpus; /* Total cpus include BSP */ + int parallel_microcode_load; + const void *microcode_pointer; + /* Flight plan for APs and BSP */ + struct mp_flight_record *flight_plan; + int num_records; +}; + +/* + * mp_init() will set up the SIPI vector and bring up the APs according to + * mp_params. Each flight record will be executed according to the plan. Note + * that the MP infrastructure uses SMM default area without saving it. It's + * up to the chipset or mainboard to either e820 reserve this area or save this + * region prior to calling mp_init() and restoring it after mp_init returns. + * + * At the time mp_init() is called the MTRR MSRs are mirrored into APs then + * caching is enabled before running the flight plan. + * + * The MP init has the following properties: + * 1. APs are brought up in parallel. + * 2. The ordering of cpu number and APIC ids is not deterministic. + * Therefore, one cannot rely on this property or the order of devices in + * the device tree unless the chipset or mainboard know the APIC ids + * a priori. + * + * mp_init() returns < 0 on error, 0 on success. + */ +int mp_init(struct mp_params *params); + +/* Probes the CPU device */ +int mp_init_cpu(struct udevice *cpu, void *unused); + +#endif /* _X86_MP_H_ */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 2cbb270089..38dbb3137a 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -53,10 +53,17 @@ #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) +#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd #define MSR_PLATFORM_INFO 0x000000ce +#define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 +#define SINGLE_PCTL (1 << 11) + #define MSR_MTRRcap 0x000000fe #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e +#define MSR_POWER_MISC 0x00000120 +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 @@ -66,6 +73,7 @@ #define MSR_IA32_MCG_STATUS 0x0000017a #define MSR_IA32_MCG_CTL 0x0000017b +#define MSR_IA32_MISC_ENABLES 0x000001a0 #define MSR_OFFCORE_RSP_0 0x000001a6 #define MSR_OFFCORE_RSP_1 0x000001a7 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad @@ -73,6 +81,7 @@ #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 +#define MSR_POWER_CTL 0x000001fc #define MSR_LBR_NHM_FROM 0x00000680 #define MSR_LBR_NHM_TO 0x000006c0 #define MSR_LBR_CORE_FROM 0x00000040 @@ -136,7 +145,7 @@ /* Run Time Average Power Limiting (RAPL) Interface */ -#define MSR_RAPL_POWER_UNIT 0x00000606 +#define MSR_PKG_POWER_SKU_UNIT 0x00000606 #define MSR_PKG_POWER_LIMIT 0x00000610 #define MSR_PKG_ENERGY_STATUS 0x00000611 @@ -158,6 +167,16 @@ #define MSR_PP1_POLICY 0x00000642 #define MSR_CORE_C1_RES 0x00000660 +#define MSR_IACORE_RATIOS 0x0000066a +#define MSR_IACORE_TURBO_RATIOS 0x0000066c +#define MSR_IACORE_VIDS 0x0000066b +#define MSR_IACORE_TURBO_VIDS 0x0000066d +#define MSR_PKG_TURBO_CFG1 0x00000670 +#define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 +#define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 +#define MSR_CPU_THERM_CFG1 0x00000673 +#define MSR_CPU_THERM_CFG2 0x00000674 +#define MSR_CPU_THERM_SENS_CFG 0x00000675 #define MSR_AMD64_MC0_MASK 0xc0010044 @@ -348,6 +367,7 @@ #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) #define MSR_IA32_MISC_ENABLE 0x000001a0 +#define H_MISC_DISABLE_TURBO (1 << 6) #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 1955a752b9..c480920d25 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -128,6 +128,34 @@ static inline void wrmsr(unsigned msr, unsigned low, unsigned high) #define wrmsrl(msr, val) \ native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) +static inline void msr_clrsetbits_64(unsigned msr, u64 clear, u64 set) +{ + u64 val; + + val = native_read_msr(msr); + val &= ~clear; + val |= set; + wrmsrl(msr, val); +} + +static inline void msr_setbits_64(unsigned msr, u64 set) +{ + u64 val; + + val = native_read_msr(msr); + val |= set; + wrmsrl(msr, val); +} + +static inline void msr_clrbits_64(unsigned msr, u64 clear) +{ + u64 val; + + val = native_read_msr(msr); + val &= ~clear; + wrmsrl(msr, val); +} + /* rdmsr with exception handling */ #define rdmsr_safe(msr, p1, p2) \ ({ \ diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index fda4eae10d..3ad617cb4a 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -34,6 +34,22 @@ /* Number of MTRRs supported */ #define MTRR_COUNT 8 +#define NUM_FIXED_MTRRS 11 +#define RANGES_PER_FIXED_MTRR 8 +#define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) + +#define MTRR_FIX_64K_00000_MSR 0x250 +#define MTRR_FIX_16K_80000_MSR 0x258 +#define MTRR_FIX_16K_A0000_MSR 0x259 +#define MTRR_FIX_4K_C0000_MSR 0x268 +#define MTRR_FIX_4K_C8000_MSR 0x269 +#define MTRR_FIX_4K_D0000_MSR 0x26a +#define MTRR_FIX_4K_D8000_MSR 0x26b +#define MTRR_FIX_4K_E0000_MSR 0x26c +#define MTRR_FIX_4K_E8000_MSR 0x26d +#define MTRR_FIX_4K_F0000_MSR 0x26e +#define MTRR_FIX_4K_F8000_MSR 0x26f + #if !defined(__ASSEMBLER__) /** diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index a1969ede27..56eaa25b0c 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -64,6 +64,20 @@ int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size); +/** + * Assign IRQ number to a PCI device + * + * This function assigns IRQ for a PCI device. If the device does not exist + * or does not require interrupts then this function has no effect. + * + * @bus: PCI bus number + * @device: PCI device number + * @func: PCI function number + * @irq: An array of IRQ numbers that are assigned to INTA through + * INTD of this PCI device. + */ +void pci_assign_irqs(int bus, int device, int func, u8 irq[4]); + #endif /* __ASSEMBLY__ */ #endif /* _PCI_I386_H_ */ diff --git a/arch/x86/include/asm/pirq_routing.h b/arch/x86/include/asm/pirq_routing.h new file mode 100644 index 0000000000..ddc08e11d5 --- /dev/null +++ b/arch/x86/include/asm/pirq_routing.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * Ported from coreboot src/arch/x86/include/arch/pirq_routing.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PIRQ_ROUTING_H_ +#define _PIRQ_ROUTING_H_ + +/* + * This is the maximum number on interrupt entries that a PCI device may have. + * This is NOT the number of slots or devices in the system + * This is NOT the number of entries in the PIRQ table + * + * This tells us that in the PIRQ table, we are going to have 4 link-bitmap + * entries per PCI device which is fixed at 4: INTA, INTB, INTC, and INTD. + * + * CAUTION: If you change this, PIRQ routing will not work correctly. + */ +#define MAX_INTX_ENTRIES 4 + +#define PIRQ_SIGNATURE \ + (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) +#define PIRQ_VERSION 0x0100 + +struct __packed irq_info { + u8 bus; /* Bus number */ + u8 devfn; /* Device and function number */ + struct __packed { + u8 link; /* IRQ line ID, 0=not routed */ + u16 bitmap; /* Available IRQs */ + } irq[MAX_INTX_ENTRIES]; + u8 slot; /* Slot number, 0=onboard */ + u8 rfu; +}; + +struct __packed irq_routing_table { + u32 signature; /* PIRQ_SIGNATURE */ + u16 version; /* PIRQ_VERSION */ + u16 size; /* Table size in bytes */ + u8 rtr_bus; /* busno of the interrupt router */ + u8 rtr_devfn; /* devfn of the interrupt router */ + u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ + u16 rtr_vendor; /* Vendor ID of the interrupt router */ + u16 rtr_device; /* Device ID of the interrupt router */ + u32 miniport_data; + u8 rfu[11]; + u8 checksum; /* Modulo 256 checksum must give zero */ + struct irq_info slots[CONFIG_IRQ_SLOT_COUNT]; +}; + +/** + * get_irq_slot_count() - Get the number of entries in the irq_info table + * + * This calculates the number of entries for the irq_info table. + * + * @rt: pointer to the base address of the struct irq_info + * @return: number of entries + */ +static inline int get_irq_slot_count(struct irq_routing_table *rt) +{ + return (rt->size - 32) / sizeof(struct irq_info); +} + +/** + * pirq_check_irq_routed() - Check whether an IRQ is routed to 8259 PIC + * + * This function checks whether an IRQ is routed to 8259 PIC for a given link. + * + * Note: this function should be provided by the platform codes, as the + * implementation of interrupt router may be different. + * + * @link: link number which represents a PIRQ + * @irq: the 8259 IRQ number + * @return: true if the irq is already routed to 8259 for a given link, + * false elsewise + */ +bool pirq_check_irq_routed(int link, u8 irq); + +/** + * pirq_translate_link() - Translate a link value + * + * This function translates a platform-specific link value to a link number. + * On Intel platforms, the link value is normally a offset into the PCI + * configuration space into the legacy bridge. + * + * Note: this function should be provided by the platform codes, as the + * implementation of interrupt router may be different. + * + * @link: platform-specific link value + * @return: link number which represents a PIRQ + */ +int pirq_translate_link(int link); + +/** + * pirq_assign_irq() - Assign an IRQ to a PIRQ link + * + * This function assigns the IRQ to a PIRQ link so that the PIRQ is routed to + * the 8259 PIC. + * + * Note: this function should be provided by the platform codes, as the + * implementation of interrupt router may be different. + * + * @link: link number which represents a PIRQ + * @irq: IRQ to which the PIRQ is routed + */ +void pirq_assign_irq(int link, u8 irq); + +/** + * pirq_route_irqs() - Route PIRQs to 8259 PIC + * + * This function configures all PCI devices' interrupt pins and maps them to + * PIRQs and finally 8259 PIC. The routed irq number is written to interrupt + * line register in the configuration space of the PCI device for OS to use. + * The configuration source is taken from a struct irq_info table, the format + * of which is defined in PIRQ routing table spec and PCI BIOS spec. + * + * @irq: pointer to the base address of the struct irq_info + * @num: number of entries in the struct irq_info + */ +void pirq_route_irqs(struct irq_info *irq, int num); + +/** + * copy_pirq_routing_table() - Copy a PIRQ routing table + * + * This helper function copies the given PIRQ routing table to a given address. + * Before copying, it does several sanity tests against the PIRQ routing table. + * It also fixes up the table checksum and align the given address to a 16 byte + * boundary to meet the PIRQ routing table spec requirements. + * + * @addr: address to store the copied PIRQ routing table + * @rt: pointer to the PIRQ routing table to copy from + * @return: end address of the copied PIRQ routing table + */ +u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt); + +#endif /* _PIRQ_ROUTING_H_ */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 3e26202aa5..7c77b90485 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -23,10 +23,32 @@ #define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) +/* Length of the public header on Intel microcode blobs */ +#define UCODE_HEADER_LEN 0x30 + #ifndef __ASSEMBLY__ +/* + * This register is documented in (for example) the Intel Atom Processor E3800 + * Product Family Datasheet in "PCU - Power Management Controller (PMC)". + * + * RST_CNT: Reset Control Register (RST_CNT) Offset cf9. + * + * The naming follows Intel's naming. + */ #define PORT_RESET 0xcf9 +enum { + SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */ + RST_CPU = 1 << 2, /* initiate reset */ + FULL_RST = 1 << 3, /* full power cycle */ +}; + +/** + * x86_full_reset() - reset everything: perform a full power cycle + */ +void x86_full_reset(void); + static inline __attribute__((always_inline)) void cpu_hlt(void) { asm("hlt"); diff --git a/arch/x86/include/asm/sfi.h b/arch/x86/include/asm/sfi.h new file mode 100644 index 0000000000..d1f0f0cb6b --- /dev/null +++ b/arch/x86/include/asm/sfi.h @@ -0,0 +1,137 @@ +/* + * Copyright(c) 2009 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#ifndef _LINUX_SFI_H +#define _LINUX_SFI_H + +#include <errno.h> +#include <linux/types.h> + +/* Table signatures reserved by the SFI specification */ +#define SFI_SIG_SYST "SYST" +#define SFI_SIG_FREQ "FREQ" +#define SFI_SIG_CPUS "CPUS" +#define SFI_SIG_MTMR "MTMR" +#define SFI_SIG_MRTC "MRTC" +#define SFI_SIG_MMAP "MMAP" +#define SFI_SIG_APIC "APIC" +#define SFI_SIG_XSDT "XSDT" +#define SFI_SIG_WAKE "WAKE" +#define SFI_SIG_DEVS "DEVS" +#define SFI_SIG_GPIO "GPIO" + +#define SFI_SIGNATURE_SIZE 4 +#define SFI_OEM_ID_SIZE 6 +#define SFI_OEM_TABLE_ID_SIZE 8 + +#define SFI_NAME_LEN 16 +#define SFI_TABLE_MAX_ENTRIES 16 + +#define SFI_GET_NUM_ENTRIES(ptable, entry_type) \ + ((ptable->header.len - sizeof(struct sfi_table_header)) / \ + (sizeof(entry_type))) +/* + * Table structures must be byte-packed to match the SFI specification, + * as they are provided by the BIOS. + */ +struct __packed sfi_table_header { + char sig[SFI_SIGNATURE_SIZE]; + u32 len; + u8 rev; + u8 csum; + char oem_id[SFI_OEM_ID_SIZE]; + char oem_table_id[SFI_OEM_TABLE_ID_SIZE]; +}; + +struct __packed sfi_table_simple { + struct sfi_table_header header; + u64 pentry[1]; +}; + +/* Comply with UEFI spec 2.1 */ +struct __packed sfi_mem_entry { + u32 type; + u64 phys_start; + u64 virt_start; + u64 pages; + u64 attrib; +}; + +struct __packed sfi_cpu_table_entry { + u32 apic_id; +}; + +struct __packed sfi_cstate_table_entry { + u32 hint; /* MWAIT hint */ + u32 latency; /* latency in ms */ +}; + +struct __packed sfi_apic_table_entry { + u64 phys_addr; /* phy base addr for APIC reg */ +}; + +struct __packed sfi_freq_table_entry { + u32 freq_mhz; /* in MHZ */ + u32 latency; /* transition latency in ms */ + u32 ctrl_val; /* value to write to PERF_CTL */ +}; + +struct __packed sfi_wake_table_entry { + u64 phys_addr; /* pointer to where the wake vector locates */ +}; + +struct __packed sfi_timer_table_entry { + u64 phys_addr; /* phy base addr for the timer */ + u32 freq_hz; /* in HZ */ + u32 irq; +}; + +struct __packed sfi_rtc_table_entry { + u64 phys_addr; /* phy base addr for the RTC */ + u32 irq; +}; + +struct __packed sfi_device_table_entry { + u8 type; /* bus type, I2C, SPI or ...*/ + u8 host_num; /* attached to host 0, 1...*/ + u16 addr; + u8 irq; + u32 max_freq; + char name[SFI_NAME_LEN]; +}; + +enum { + SFI_DEV_TYPE_SPI = 0, + SFI_DEV_TYPE_I2C, + SFI_DEV_TYPE_UART, + SFI_DEV_TYPE_HSI, + SFI_DEV_TYPE_IPC, + SFI_DEV_TYPE_SD, +}; + +struct __packed sfi_gpio_table_entry { + char controller_name[SFI_NAME_LEN]; + u16 pin_no; + char pin_name[SFI_NAME_LEN]; +}; + +struct sfi_xsdt_header { + uint32_t oem_revision; + uint32_t creator_id; + uint32_t creator_revision; +}; + +typedef int (*sfi_table_handler) (struct sfi_table_header *table); + +/** + * write_sfi_table() - Write Simple Firmware Interface tables + * + * @base: Address to write table to + * @return address to use for the next table + */ +u32 write_sfi_table(u32 base); + +#endif /*_LINUX_SFI_H */ diff --git a/arch/x86/include/asm/sipi.h b/arch/x86/include/asm/sipi.h new file mode 100644 index 0000000000..25d7d311d2 --- /dev/null +++ b/arch/x86/include/asm/sipi.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2015 Gooogle, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_SIPI_H +#define _ASM_SIPI_H + +#define AP_DEFAULT_BASE 0x30000 +#define AP_DEFAULT_SIZE 0x10000 + +#ifndef __ASSEMBLER__ + +/** + * struct sipi_params_16bit - 16-bit SIPI entry-point parameters + * + * These are set up in the same space as the SIPI 16-bit code so that each AP + * can access the parameters when it boots. + * + * Each of these must be set up for the AP to boot, except @segment which is + * set in the assembly code. + * + * @ap_start: 32-bit SIPI entry point for U-Boot + * @segment: Code segment for U-Boot + * @pad: Padding (not used) + * @gdt_limit: U-Boot GDT limit (X86_GDT_SIZE - 1) + * @gdt: U-Boot GDT (gd->arch.gdt) + * @unused: Not used + */ +struct __packed sipi_params_16bit { + u32 ap_start; + u16 segment; + u16 pad; + u16 gdt_limit; + u32 gdt; + u16 unused; +}; + +/** + * struct sipi_params - 32-bit SIP entry-point parameters + * + * These are used by the AP init code and must be set up before the APs start. + * + * The stack area extends down from @stack_top, with @stack_size allocated + * for each AP. + * + * @idt_ptr: Interrupt descriptor table pointer + * @stack_top: Top of the AP stack area + * @stack_size: Size of each AP's stack + * @microcode_lock: Used to ensure only one AP loads microcode at once + * 0xffffffff enables parallel loading. + * @microcode_ptr: Pointer to microcode, or 0 if none + * @msr_table_ptr: Pointer to saved MSRs, a list of struct saved_msr + * @msr_count: Number of saved MSRs + * @c_handler: C function to call once early init is complete + * @ap_count: Shared atomic value to allocate CPU indexes + */ +struct sipi_params { + u32 idt_ptr; + u32 stack_top; + u32 stack_size; + u32 microcode_lock; + u32 microcode_ptr; + u32 msr_table_ptr; + u32 msr_count; + u32 c_handler; + atomic_t ap_count; +}; + +/* 16-bit AP entry point */ +void ap_start16(void); + +/* end of 16-bit code/data, marks the region to be copied to SIP vector */ +void ap_start16_code_end(void); + +/* 32-bit AP entry point */ +void ap_start(void); + +extern char sipi_params_16bit[]; +extern char sipi_params[]; + +#endif /* __ASSEMBLER__ */ + +#endif diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h new file mode 100644 index 0000000000..8146ba39b2 --- /dev/null +++ b/arch/x86/include/asm/tables.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_TABLES_H_ +#define _X86_TABLES_H_ + +/* + * All x86 tables happen to like the address range from 0xf0000 to 0x100000. + * We use 0xf0000 as the starting address to store those tables, including + * PIRQ routing table, Multi-Processor table and ACPI table. + */ +#define ROM_TABLE_ADDR 0xf0000 + +/** + * table_compute_checksum() - Compute a table checksum + * + * This computes an 8-bit checksum for the configuration table. + * All bytes in the configuration table, including checksum itself and + * reserved bytes must add up to zero. + * + * @v: configuration table base address + * @len: configuration table size + * @return: the 8-bit checksum + */ +u8 table_compute_checksum(void *v, int len); + +/** + * write_tables() - Write x86 configuration tables + * + * This writes x86 configuration tables, including PIRQ routing table, + * Multi-Processor table and ACPI table. Whether a specific type of + * configuration table is written is controlled by a Kconfig option. + */ +void write_tables(void); + +/** + * write_pirq_routing_table() - Write PIRQ routing table + * + * This writes PIRQ routing table at a given address. + * + * @start: start address to write PIRQ routing table + * @return: end address of PIRQ routing table + */ +u32 write_pirq_routing_table(u32 start); + +#endif /* _X86_TABLES_H_ */ diff --git a/arch/x86/include/asm/turbo.h b/arch/x86/include/asm/turbo.h index bb0d4b4354..21b910bbf0 100644 --- a/arch/x86/include/asm/turbo.h +++ b/arch/x86/include/asm/turbo.h @@ -12,9 +12,6 @@ #define CPUID_LEAF_PM 6 #define PM_CAP_TURBO_MODE (1 << 1) -#define MSR_IA32_MISC_ENABLES 0x1a0 -#define H_MISC_DISABLE_TURBO (1 << 6) - enum { TURBO_UNKNOWN, TURBO_UNAVAILABLE, diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index c743efd60b..be103c055c 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -53,6 +53,8 @@ int video_bios_init(void); void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); void board_init_f_r(void) __attribute__ ((noreturn)); +int arch_misc_init(void); + /* Read the time stamp counter */ static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void) { @@ -67,6 +69,8 @@ uint64_t timer_get_tsc(void); void quick_ram_check(void); +int x86_init_cpus(void); + #define PCI_VGA_RAM_IMAGE_START 0xc0000 #endif /* _U_BOOT_I386_H_ */ |
