diff options
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/cpu.c | 23 | ||||
| -rw-r--r-- | arch/x86/cpu/interrupts.c | 53 | ||||
| -rw-r--r-- | arch/x86/cpu/sc520/asm-offsets.c | 45 | ||||
| -rw-r--r-- | arch/x86/cpu/sc520/sc520.c | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/sc520/sc520_car.S | 3 | ||||
| -rw-r--r-- | arch/x86/cpu/sc520/sc520_pci.c | 28 | ||||
| -rw-r--r-- | arch/x86/cpu/sc520/sc520_sdram.c | 53 | ||||
| -rw-r--r-- | arch/x86/cpu/sc520/sc520_ssi.c | 43 | ||||
| -rw-r--r-- | arch/x86/cpu/sc520/sc520_timer.c | 4 | ||||
| -rw-r--r-- | arch/x86/cpu/start.S | 30 | ||||
| -rw-r--r-- | arch/x86/cpu/start16.S | 3 |
11 files changed, 154 insertions, 133 deletions
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index cac12c088c..61d0b69416 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -37,6 +37,7 @@ #include <asm/processor.h> #include <asm/processor-flags.h> #include <asm/interrupt.h> +#include <linux/compiler.h> /* * Constructor for a conventional segment GDT (or LDT) entry @@ -52,7 +53,7 @@ struct gdt_ptr { u16 len; u32 ptr; -} __attribute__((packed)); +} __packed; static void reload_gdt(void) { @@ -115,14 +116,14 @@ int x86_cpu_init_r(void) reload_gdt(); /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts (); + cpu_init_interrupts(); return 0; } int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - printf ("resetting ...\n"); + printf("resetting ...\n"); /* wait 50 ms */ udelay(50000); @@ -133,7 +134,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -void flush_cache (unsigned long dummy1, unsigned long dummy2) +void flush_cache(unsigned long dummy1, unsigned long dummy2) { asm("wbinvd\n"); } @@ -142,16 +143,16 @@ void __attribute__ ((regparm(0))) generate_gpf(void); /* segment 0x70 is an arbitrary segment which does not exist */ asm(".globl generate_gpf\n" - ".hidden generate_gpf\n" - ".type generate_gpf, @function\n" - "generate_gpf:\n" - "ljmp $0x70, $0x47114711\n"); + ".hidden generate_gpf\n" + ".type generate_gpf, @function\n" + "generate_gpf:\n" + "ljmp $0x70, $0x47114711\n"); void __reset_cpu(ulong addr) { printf("Resetting using x86 Triple Fault\n"); - set_vector(13, generate_gpf); /* general protection fault handler */ - set_vector(8, generate_gpf); /* double fault handler */ - generate_gpf(); /* start the show */ + set_vector(13, generate_gpf); /* general protection fault handler */ + set_vector(8, generate_gpf); /* double fault handler */ + generate_gpf(); /* start the show */ } void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu"))); diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index c6e72eaa63..e0958eb67f 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -31,6 +31,7 @@ #include <asm/interrupt.h> #include <asm/io.h> #include <asm/processor-flags.h> +#include <linux/compiler.h> #define DECLARE_INTERRUPT(x) \ ".globl irq_"#x"\n" \ @@ -83,22 +84,22 @@ static inline unsigned long get_debugreg(int regno) switch (regno) { case 0: - asm("mov %%db0, %0" :"=r" (val)); + asm("mov %%db0, %0" : "=r" (val)); break; case 1: - asm("mov %%db1, %0" :"=r" (val)); + asm("mov %%db1, %0" : "=r" (val)); break; case 2: - asm("mov %%db2, %0" :"=r" (val)); + asm("mov %%db2, %0" : "=r" (val)); break; case 3: - asm("mov %%db3, %0" :"=r" (val)); + asm("mov %%db3, %0" : "=r" (val)); break; case 6: - asm("mov %%db6, %0" :"=r" (val)); + asm("mov %%db6, %0" : "=r" (val)); break; case 7: - asm("mov %%db7, %0" :"=r" (val)); + asm("mov %%db7, %0" : "=r" (val)); break; default: val = 0; @@ -120,7 +121,8 @@ void dump_regs(struct irq_regs *regs) printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n", regs->esi, regs->edi, regs->ebp, regs->esp); printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n", - (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss); + (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, + (u16)regs->xgs, (u16)regs->xss); cr0 = read_cr0(); cr2 = read_cr2(); @@ -164,21 +166,21 @@ struct idt_entry { u8 res; u8 access; u16 base_high; -} __attribute__ ((packed)); +} __packed; struct desc_ptr { unsigned short size; unsigned long address; unsigned short segment; -} __attribute__((packed)); +} __packed; -struct idt_entry idt[256]; +struct idt_entry idt[256] __attribute__((aligned(16))); struct desc_ptr idt_ptr; static inline void load_idt(const struct desc_ptr *dtr) { - asm volatile("cs lidt %0"::"m" (*dtr)); + asm volatile("cs lidt %0" : : "m" (*dtr)); } void set_vector(u8 intnum, void *routine) @@ -187,6 +189,11 @@ void set_vector(u8 intnum, void *routine) idt[intnum].base_low = (u16)((u32)(routine) & 0xffff); } +/* + * Ideally these would be defined static to avoid a checkpatch warning, but + * the compiler cannot see them in the inline asm and complains that they + * aren't defined + */ void irq_0(void); void irq_1(void); @@ -201,7 +208,7 @@ int cpu_init_interrupts(void) disable_interrupts(); /* Setup the IDT */ - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { idt[i].access = 0x8e; idt[i].res = 0; idt[i].selector = 0x10; @@ -238,7 +245,7 @@ int disable_interrupts(void) asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : ); - return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */ + return flags & X86_EFLAGS_IF; } /* IRQ Low-Level Service Routine */ @@ -255,7 +262,7 @@ void irq_llsr(struct irq_regs *regs) case 0x00: printf("Divide Error (Division by zero)\n"); dump_regs(regs); - while(1); + hang(); break; case 0x01: printf("Debug Interrupt (Single step)\n"); @@ -272,32 +279,32 @@ void irq_llsr(struct irq_regs *regs) case 0x04: printf("Overflow\n"); dump_regs(regs); - while(1); + hang(); break; case 0x05: printf("BOUND Range Exceeded\n"); dump_regs(regs); - while(1); + hang(); break; case 0x06: printf("Invalid Opcode (UnDefined Opcode)\n"); dump_regs(regs); - while(1); + hang(); break; case 0x07: printf("Device Not Available (No Math Coprocessor)\n"); dump_regs(regs); - while(1); + hang(); break; case 0x08: printf("Double fault\n"); dump_regs(regs); - while(1); + hang(); break; case 0x09: printf("Co-processor segment overrun\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0a: printf("Invalid TSS\n"); @@ -306,12 +313,12 @@ void irq_llsr(struct irq_regs *regs) case 0x0b: printf("Segment Not Present\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0c: printf("Stack Segment Fault\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0d: printf("General Protection\n"); @@ -320,7 +327,7 @@ void irq_llsr(struct irq_regs *regs) case 0x0e: printf("Page fault\n"); dump_regs(regs); - while(1); + hang(); break; case 0x0f: printf("Floating-Point Error (Math Fault)\n"); diff --git a/arch/x86/cpu/sc520/asm-offsets.c b/arch/x86/cpu/sc520/asm-offsets.c new file mode 100644 index 0000000000..794f00cdb9 --- /dev/null +++ b/arch/x86/cpu/sc520/asm-offsets.c @@ -0,0 +1,45 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/sc520.h> + +#include <linux/kbuild.h> + +int main(void) +{ + DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off)); + + DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0])); + DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1])); + DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2])); + DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3])); + DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4])); + DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5])); + DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6])); + DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7])); + DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8])); + DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9])); + DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10])); + DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11])); + DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12])); + DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13])); + DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14])); + DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15])); + + return 0; +} diff --git a/arch/x86/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c index 4892c0153f..3fe85e7648 100644 --- a/arch/x86/cpu/sc520/sc520.c +++ b/arch/x86/cpu/sc520/sc520.c @@ -49,7 +49,7 @@ int cpu_init_f(void) asm("movl $0x2000, %%ecx\n" "0: pushl %%ecx\n" "popl %%ecx\n" - "loop 0b\n": : : "ecx"); + "loop 0b\n" : : : "ecx"); return x86_cpu_init_f(); } diff --git a/arch/x86/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S index 7cac4d1def..c04cc1f116 100644 --- a/arch/x86/cpu/sc520/sc520_car.S +++ b/arch/x86/cpu/sc520/sc520_car.S @@ -24,6 +24,7 @@ #include <config.h> #include <asm/processor-flags.h> #include <asm/arch/sc520.h> +#include <generated/asm-offsets.h> .section .text @@ -55,7 +56,7 @@ car_init: /* Configure Cache-As-RAM PAR */ movl $CONFIG_SYS_SC520_CAR_PAR, %eax - movl $SC520_PAR2, %edi + movl $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi movl %eax, (%edi) /* Trash the cache then turn it on */ diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c index e26793ab1b..52d07c119a 100644 --- a/arch/x86/cpu/sc520/sc520_pci.c +++ b/arch/x86/cpu/sc520/sc520_pci.c @@ -70,26 +70,28 @@ int pci_sc520_set_irq(int pci_pin, int irq) debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); - if (irq < 0 || irq > 15) { + if (irq < 0 || irq > 15) return -1; /* illegal irq */ - } - if (pci_pin < 0 || pci_pin > 15) { + if (pci_pin < 0 || pci_pin > 15) return -1; /* illegal pci int pin */ - } /* first disable any non-pci interrupt source that use * this level */ /* PCI interrupt mapping (A through D)*/ - for (i=0; i<=3 ;i++) { - if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority) + for (i = 0; i <= 3 ; i++) { + tmpb = readb(&sc520_mmcr->pci_int_map[i]); + + if (tmpb == sc520_irq[irq].priority) writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]); } /* GP IRQ interrupt mapping */ - for (i=0; i<=10 ;i++) { - if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority) + for (i = 0; i <= 10 ; i++) { + tmpb = readb(&sc520_mmcr->gp_int_map[i]); + + if (tmpb == sc520_irq[irq].priority) writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]); } @@ -102,10 +104,12 @@ int pci_sc520_set_irq(int pci_pin, int irq) if (pci_pin < 4) { /* PCI INTA-INTD */ /* route the interrupt */ - writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]); + writeb(sc520_irq[irq].priority, + &sc520_mmcr->pci_int_map[pci_pin]); } else { /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]); + writeb(sc520_irq[irq].priority, + &sc520_mmcr->gp_int_map[pci_pin - 4]); /* also set the polarity in this case */ tmpw = readw(&sc520_mmcr->intpinpol); @@ -126,9 +130,7 @@ void pci_sc520_init(struct pci_controller *hose) hose->last_busno = 0xff; hose->region_count = pci_set_regions(hose); - pci_setup_type1(hose, - SC520_REG_ADDR, - SC520_REG_DATA); + pci_setup_type1(hose); pci_register_hose(hose); diff --git a/arch/x86/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c index 57e4e7ddc3..9dc13342e3 100644 --- a/arch/x86/cpu/sc520/sc520_sdram.c +++ b/arch/x86/cpu/sc520/sc520_sdram.c @@ -40,9 +40,6 @@ static void sc520_set_dram_timing(void); static void sc520_set_dram_refresh_rate(void); static void sc520_enable_dram_refresh(void); static void sc520_enable_sdram(void); -#if CONFIG_SYS_SDRAM_ECC_ENABLE -static void sc520_enable_ecc(void) -#endif int dram_init_f(void) { @@ -51,9 +48,6 @@ int dram_init_f(void) sc520_set_dram_refresh_rate(); sc520_enable_dram_refresh(); sc520_enable_sdram(); -#if CONFIG_SYS_SDRAM_ECC_ENABLE - sc520_enable_ecc(); -#endif return 0; } @@ -426,53 +420,6 @@ static void sc520_sizemem(void) writel(0x00000000, &sc520_mmcr->par[4]); } -#if CONFIG_SYS_SDRAM_ECC_ENABLE -static void sc520_enable_ecc(void) - - /* A nominal memory test: just a byte at each address line */ - movl %eax, %ecx - shrl $0x1, %ecx - movl $0x1, %edi -memtest0: - movb $0xa5, (%edi) - cmpb $0xa5, (%edi) - jne out - shrl $0x1, %ecx - andl %ecx, %ecx - jz set_ecc - shll $0x1, %edi - jmp memtest0 - -set_ecc: - /* clear all ram with a memset */ - movl %eax, %ecx - xorl %esi, %esi - xorl %edi, %edi - xorl %eax, %eax - shrl $0x2, %ecx - cld - rep stosl - - /* enable read, write buffers */ - movb $0x11, %al - movl $DBCTL, %edi - movb %al, (%edi) - - /* enable NMI mapping for ECC */ - movl $ECCINT, %edi - movb $0x10, %al - movb %al, (%edi) - - /* Turn on ECC */ - movl $ECCCTL, %edi - movb $0x05, %al - movb %al,(%edi) - -out: - jmp init_ecc_ret -} -#endif - int dram_init(void) { ulong dram_ctrl; diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c index 3a6a858091..cc601e56e4 100644 --- a/arch/x86/cpu/sc520/sc520_ssi.c +++ b/arch/x86/cpu/sc520/sc520_ssi.c @@ -28,37 +28,33 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) { - u8 temp=0; + u8 temp = 0; - if (freq >= 8192) { + if (freq >= 8192) temp |= CTL_CLK_SEL_4; - } else if (freq >= 4096) { + else if (freq >= 4096) temp |= CTL_CLK_SEL_8; - } else if (freq >= 2048) { + else if (freq >= 2048) temp |= CTL_CLK_SEL_16; - } else if (freq >= 1024) { + else if (freq >= 1024) temp |= CTL_CLK_SEL_32; - } else if (freq >= 512) { + else if (freq >= 512) temp |= CTL_CLK_SEL_64; - } else if (freq >= 256) { + else if (freq >= 256) temp |= CTL_CLK_SEL_128; - } else if (freq >= 128) { + else if (freq >= 128) temp |= CTL_CLK_SEL_256; - } else { + else temp |= CTL_CLK_SEL_512; - } - if (!lsb_first) { + if (!lsb_first) temp |= MSBF_ENB; - } - if (inv_clock) { + if (inv_clock) temp |= CLK_INV_ENB; - } - if (inv_phase) { + if (inv_phase) temp |= PHS_INV_ENB; - } writeb(temp, &sc520_mmcr->ssictl); @@ -68,9 +64,11 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) u8 ssi_txrx_byte(u8 data) { writeb(data, &sc520_mmcr->ssixmit); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; return readb(&sc520_mmcr->ssircv); } @@ -78,15 +76,18 @@ u8 ssi_txrx_byte(u8 data) void ssi_tx_byte(u8 data) { writeb(data, &sc520_mmcr->ssixmit); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd); } u8 ssi_rx_byte(void) { - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd); - while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY) + ; return readb(&sc520_mmcr->ssircv); } diff --git a/arch/x86/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c index 05bc9c1103..495a69459b 100644 --- a/arch/x86/cpu/sc520/sc520_timer.c +++ b/arch/x86/cpu/sc520/sc520_timer.c @@ -38,7 +38,7 @@ void sc520_timer_isr(void) int timer_init(void) { /* Register the SC520 specific timer interrupt handler */ - register_timer_isr (sc520_timer_isr); + register_timer_isr(sc520_timer_isr); /* Install interrupt handler for GP Timer 1 */ irq_install_handler (0, timer_isr, NULL); @@ -62,7 +62,7 @@ int timer_init(void) writew(100, &sc520_mmcr->gptmr1maxcmpa); writew(0xe009, &sc520_mmcr->gptmr1ctl); - unmask_irq (0); + unmask_irq(0); /* Clear the GP Timer 1 status register to get the show rolling*/ writeb(0x02, &sc520_mmcr->gptmrsta); diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 306fb49617..f87633b561 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -30,6 +30,7 @@ #include <version.h> #include <asm/global_data.h> #include <asm/processor-flags.h> +#include <generated/asm-offsets.h> .section .text .code32 @@ -47,14 +48,12 @@ _x86boot_start: cli cld - /* Turn of cache (this might require a 486-class CPU) */ + /* Turn off cache (this might require a 486-class CPU) */ movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 wbinvd - /* Tell 32-bit code it is being entered from an in-RAM copy */ - movw $GD_FLG_WARM_BOOT, %bx _start: /* This is the 32-bit cold-reset entry point */ @@ -114,7 +113,7 @@ relocate_code: /* Setup call address of in-RAM copy of board_init_r() */ movl $board_init_r, %ebp - addl (GD_RELOC_OFF * 4)(%edx), %ebp + addl (GENERATED_GD_RELOC_OFF)(%edx), %ebp /* Setup parameters to board_init_r() */ movl %edx, %eax @@ -123,10 +122,31 @@ relocate_code: /* Jump to in-RAM copy of board_init_r() */ call *%ebp -die: hlt +die: + hlt jmp die hlt blank_idt_ptr: .word 0 /* limit */ .long 0 /* base */ + + .p2align 2 /* force 4-byte alignment */ + +multiboot_header: + /* magic */ + .long 0x1BADB002 + /* flags */ + .long (1 << 16) + /* checksum */ + .long -0x1BADB002 - (1 << 16) + /* header addr */ + .long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE + /* load addr */ + .long CONFIG_SYS_TEXT_BASE + /* load end addr */ + .long 0 + /* bss end addr */ + .long 0 + /* entry addr */ + .long CONFIG_SYS_TEXT_BASE diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 9dabff2b9f..33e53cdb3b 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -37,9 +37,6 @@ .code16 .globl start16 start16: - /* Set the Cold Boot / Hard Reset flag */ - movl $GD_FLG_COLD_BOOT, %ebx - /* * First we let the BSP do some early initialization * this code have to map the flash to its final position |
