diff options
Diffstat (limited to 'arch/arm/mach-mvebu/include/mach/soc.h')
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/soc.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index f2cbd71602..e27a36db1c 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -99,14 +99,24 @@ #if defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) + #define SAR_CPU_FREQ_OFFS 10 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) #define SAR_BOOT_DEVICE_OFFS 4 #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 4 +#define BOOT_DEV_SEL_MASK (0x1f << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x28 +#define BOOT_FROM_SPI 0x32 +#define BOOT_FROM_MMC 0x30 +#define BOOT_FROM_MMC_ALT 0x31 #else /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) + #define SAR_CPU_FREQ_OFFS 21 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) #define SAR_FFC_FREQ_OFFS 24 @@ -115,6 +125,12 @@ #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) #define SAR_BOOT_DEVICE_OFFS 5 #define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 5 +#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_UART 0x2 +#define BOOT_FROM_SPI 0x3 #endif #endif /* _MVEBU_SOC_H */ |
