diff options
Diffstat (limited to 'arch/arm/include/asm')
24 files changed, 850 insertions, 187 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 5e934da797..791551841c 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -97,8 +97,13 @@ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FSL_ERRATUM_A008378 #else #error SoC not defined #endif +#define FSL_IFC_COMPAT "fsl,ifc" +#define FSL_QSPI_COMPAT "fsl,ls1-qspi" +#define FSL_DSPI_COMPAT "fsl,vf610-dspi" + #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h new file mode 100644 index 0000000000..b7044362d3 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/gpio.h @@ -0,0 +1,15 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_LS102XA_GPIO_H_ +#define __ASM_ARCH_LS102XA_GPIO_H_ + +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 697d4ca489..f70d568d46 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -105,6 +105,8 @@ struct ccsr_gur { #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 +#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 +#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 @@ -456,6 +458,8 @@ struct ccsr_ddr { #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 #define CCI400_CTRLORD_EN_BARRIER 0 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h index 132d58c117..748b802546 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7790.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h @@ -28,6 +28,12 @@ #define MSTP10_BITS 0xFFFEFFE0 #define MSTP11_BITS 0x00000000 +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 + #define R8A7790_CUT_ES2X 2 #define IS_R8A7790_ES2() \ (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X) diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h index d2cbcd761d..1d06b651f4 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7791.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h @@ -17,6 +17,11 @@ /* SH-I2C */ #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 + #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 #define DBSC3_1_QOS_R2_BASE 0xE67A1200 diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793.h b/arch/arm/include/asm/arch-rmobile/r8a7793.h index 1abdeb7450..3efc62a1a9 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7793.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7793.h @@ -18,6 +18,11 @@ /* SH-I2C */ #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 + #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 #define DBSC3_1_QOS_R2_BASE 0xE67A1200 diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h index d7c9004772..6d11fa479b 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7794.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h @@ -27,4 +27,9 @@ #define MSTP10_BITS 0xFFFEFFE0 #define MSTP11_BITS 0x000001C0 +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 + #endif /* __ASM_ARCH_R8A7794_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h index 23c4bba6ed..d594cd77c1 100644 --- a/arch/arm/include/asm/arch-rmobile/rcar-base.h +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -82,6 +82,9 @@ #define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 #define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 +/* SDHI */ +#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 + #define S3C_BASE 0xE6784000 #define S3C_INT_BASE 0xE6784A00 #define S3C_MEDIA_BASE 0xE6784B00 diff --git a/arch/arm/include/asm/arch-rmobile/sh_sdhi.h b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h new file mode 100644 index 0000000000..057bf3f8bb --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h @@ -0,0 +1,168 @@ +/* + * drivers/mmc/sh-sdhi.h + * + * SD/MMC driver for Reneas rmobile ARM SoCs + * + * Copyright (C) 2013-2014 Renesas Electronics Corporation + * Copyright (C) 2008-2009 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _SH_SDHI_H +#define _SH_SDHI_H + +#define SDHI_CMD (0x0000 >> 1) +#define SDHI_PORTSEL (0x0004 >> 1) +#define SDHI_ARG0 (0x0008 >> 1) +#define SDHI_ARG1 (0x000C >> 1) +#define SDHI_STOP (0x0010 >> 1) +#define SDHI_SECCNT (0x0014 >> 1) +#define SDHI_RSP00 (0x0018 >> 1) +#define SDHI_RSP01 (0x001C >> 1) +#define SDHI_RSP02 (0x0020 >> 1) +#define SDHI_RSP03 (0x0024 >> 1) +#define SDHI_RSP04 (0x0028 >> 1) +#define SDHI_RSP05 (0x002C >> 1) +#define SDHI_RSP06 (0x0030 >> 1) +#define SDHI_RSP07 (0x0034 >> 1) +#define SDHI_INFO1 (0x0038 >> 1) +#define SDHI_INFO2 (0x003C >> 1) +#define SDHI_INFO1_MASK (0x0040 >> 1) +#define SDHI_INFO2_MASK (0x0044 >> 1) +#define SDHI_CLK_CTRL (0x0048 >> 1) +#define SDHI_SIZE (0x004C >> 1) +#define SDHI_OPTION (0x0050 >> 1) +#define SDHI_ERR_STS1 (0x0058 >> 1) +#define SDHI_ERR_STS2 (0x005C >> 1) +#define SDHI_BUF0 (0x0060 >> 1) +#define SDHI_SDIO_MODE (0x0068 >> 1) +#define SDHI_SDIO_INFO1 (0x006C >> 1) +#define SDHI_SDIO_INFO1_MASK (0x0070 >> 1) +#define SDHI_CC_EXT_MODE (0x01B0 >> 1) +#define SDHI_SOFT_RST (0x01C0 >> 1) +#define SDHI_VERSION (0x01C4 >> 1) +#define SDHI_HOST_MODE (0x01C8 >> 1) +#define SDHI_SDIF_MODE (0x01CC >> 1) +#define SDHI_EXT_SWAP (0x01E0 >> 1) +#define SDHI_SD_DMACR (0x0324 >> 1) + +/* SDHI CMD VALUE */ +#define CMD_MASK 0x0000ffff +#define SDHI_APP 0x0040 +#define SDHI_SD_APP_SEND_SCR 0x0073 +#define SDHI_SD_SWITCH 0x1C06 + +/* SDHI_PORTSEL */ +#define USE_1PORT (1 << 8) /* 1 port */ + +/* SDHI_ARG */ +#define ARG0_MASK 0x0000ffff +#define ARG1_MASK 0x0000ffff + +/* SDHI_STOP */ +#define STOP_SEC_ENABLE (1 << 8) + +/* SDHI_INFO1 */ +#define INFO1_RESP_END (1 << 0) +#define INFO1_ACCESS_END (1 << 2) +#define INFO1_CARD_RE (1 << 3) +#define INFO1_CARD_IN (1 << 4) +#define INFO1_ISD0CD (1 << 5) +#define INFO1_WRITE_PRO (1 << 7) +#define INFO1_DATA3_CARD_RE (1 << 8) +#define INFO1_DATA3_CARD_IN (1 << 9) +#define INFO1_DATA3 (1 << 10) + +/* SDHI_INFO2 */ +#define INFO2_CMD_ERROR (1 << 0) +#define INFO2_CRC_ERROR (1 << 1) +#define INFO2_END_ERROR (1 << 2) +#define INFO2_TIMEOUT (1 << 3) +#define INFO2_BUF_ILL_WRITE (1 << 4) +#define INFO2_BUF_ILL_READ (1 << 5) +#define INFO2_RESP_TIMEOUT (1 << 6) +#define INFO2_SDDAT0 (1 << 7) +#define INFO2_BRE_ENABLE (1 << 8) +#define INFO2_BWE_ENABLE (1 << 9) +#define INFO2_CBUSY (1 << 14) +#define INFO2_ILA (1 << 15) +#define INFO2_ALL_ERR (0x807f) + +/* SDHI_INFO1_MASK */ +#define INFO1M_RESP_END (1 << 0) +#define INFO1M_ACCESS_END (1 << 2) +#define INFO1M_CARD_RE (1 << 3) +#define INFO1M_CARD_IN (1 << 4) +#define INFO1M_DATA3_CARD_RE (1 << 8) +#define INFO1M_DATA3_CARD_IN (1 << 9) +#define INFO1M_ALL (0xffff) +#define INFO1M_SET (INFO1M_RESP_END | \ + INFO1M_ACCESS_END | \ + INFO1M_DATA3_CARD_RE | \ + INFO1M_DATA3_CARD_IN) + +/* SDHI_INFO2_MASK */ +#define INFO2M_CMD_ERROR (1 << 0) +#define INFO2M_CRC_ERROR (1 << 1) +#define INFO2M_END_ERROR (1 << 2) +#define INFO2M_TIMEOUT (1 << 3) +#define INFO2M_BUF_ILL_WRITE (1 << 4) +#define INFO2M_BUF_ILL_READ (1 << 5) +#define INFO2M_RESP_TIMEOUT (1 << 6) +#define INFO2M_BRE_ENABLE (1 << 8) +#define INFO2M_BWE_ENABLE (1 << 9) +#define INFO2M_ILA (1 << 15) +#define INFO2M_ALL (0xffff) +#define INFO2M_ALL_ERR (0x807f) + +/* SDHI_CLK_CTRL */ +#define CLK_ENABLE (1 << 8) + +/* SDHI_OPTION */ +#define OPT_BUS_WIDTH_1 (1 << 15) /* bus width = 1 bit */ + +/* SDHI_ERR_STS1 */ +#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \ + (1 << 8) | (1 << 5)) +#define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \ + (1 << 1) | (1 << 0)) + +/* SDHI_ERR_STS2 */ +#define ERR_STS2_RES_TIMEOUT (1 << 0) +#define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1)) +#define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \ + (1 << 3) | (1 << 2) | (1 << 1) | \ + (1 << 0)) + +/* SDHI_SDIO_MODE */ +#define SDIO_MODE_ON (1 << 0) +#define SDIO_MODE_OFF (0 << 0) + +/* SDHI_SDIO_INFO1 */ +#define SDIO_INFO1_IOIRQ (1 << 0) +#define SDIO_INFO1_EXPUB52 (1 << 14) +#define SDIO_INFO1_EXWT (1 << 15) + +/* SDHI_SDIO_INFO1_MASK */ +#define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2)) +#define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \ + (1 << 1) | (1 << 0)) + +/* SDHI_EXT_SWAP */ +#define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */ + +/* SDHI_SOFT_RST */ +#define SOFT_RST_ON (0 << 0) +#define SOFT_RST_OFF (1 << 0) + +#define CLKDEV_SD_DATA 25000000 /* 25 MHz */ +#define CLKDEV_HS_DATA 50000000 /* 50 MHz */ +#define CLKDEV_MMC_DATA 20000000 /* 20MHz */ +#define CLKDEV_INIT 400000 /* 100 - 400 KHz */ + +/* For quirk */ +#define SH_SDHI_QUIRK_16BIT_BUF (1) +int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks); + +#endif /* _SH_SDHI_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 505c363e46..3e5d999081 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -17,6 +17,8 @@ /* clock control module regs definition */ #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) #include <asm/arch/clock_sun6i.h> +#elif defined(CONFIG_MACH_SUN9I) +#include <asm/arch/clock_sun9i.h> #else #include <asm/arch/clock_sun4i.h> #endif @@ -24,10 +26,6 @@ #ifndef __ASSEMBLY__ int clock_init(void); int clock_twi_onoff(int port, int state); -void clock_set_pll1(unsigned int hz); -void clock_set_pll3(unsigned int hz); -unsigned int clock_get_pll5p(void); -unsigned int clock_get_pll6(void); void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); void clock_init_safe(void); void clock_init_uart(void); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 84a9a2bdbc..05fbad3e11 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -186,6 +186,7 @@ struct sunxi_ccm_reg { /* ahb clock gate bit offset (second register) */ #define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_DE_FE0 14 #define AHB_GATE_OFFSET_DE_BE0 12 #define AHB_GATE_OFFSET_HDMI 11 #define AHB_GATE_OFFSET_LCD1 5 @@ -266,7 +267,10 @@ struct sunxi_ccm_reg { #define CCM_MMC_CTRL_PLL5 (0x2 << 24) #define CCM_MMC_CTRL_ENABLE (0x1 << 31) +#define CCM_DRAM_GATE_OFFSET_DE_FE1 24 /* Note the order of FE1 and */ +#define CCM_DRAM_GATE_OFFSET_DE_FE0 25 /* FE0 is swapped ! */ #define CCM_DRAM_GATE_OFFSET_DE_BE0 26 +#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 #define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) #define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) @@ -320,4 +324,11 @@ struct sunxi_ccm_reg { #define CCM_DE_CTRL_RST (1 << 30) #define CCM_DE_CTRL_GATE (1 << 31) +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +void clock_set_pll3(unsigned int hz); +unsigned int clock_get_pll5p(void); +unsigned int clock_get_pll6(void); +#endif + #endif /* _SUNXI_CLOCK_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 4711260c1e..e101c54051 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -320,6 +320,11 @@ struct sunxi_ccm_reg { #define CCM_DE_CTRL_PLL10 (5 << 24) #define CCM_DE_CTRL_GATE (1 << 31) +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +void clock_set_pll3(unsigned int hz); void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); +unsigned int clock_get_pll6(void); +#endif #endif /* _SUNXI_CLOCK_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h new file mode 100644 index 0000000000..c506b0a98f --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -0,0 +1,139 @@ +/* + * sun9i clock register definitions + * + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN9I_H +#define _SUNXI_CLOCK_SUN9I_H + +struct sunxi_ccm_reg { + u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ + u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ + u32 pll3_audio_cfg; /* 0x08 audio pll configuration */ + u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */ + u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */ + u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */ + u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */ + u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */ + u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */ + u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */ + u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */ + u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */ + u8 reserved1[0x20]; /* 0x30 */ + u32 cpu_clk_source; /* 0x50 cpu clk source configuration */ + u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */ + u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */ + u32 gtbus_cfg; /* 0x5c gtbus clock configuration */ + u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */ + u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */ + u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */ + u8 reserved2[0x04]; /* 0x6c */ + u32 apb0_cfg; /* 0x70 apb0 clock configuration */ + u32 apb1_cfg; /* 0x74 apb1 clock configuration */ + u32 cci400_cfg; /* 0x78 cci400 clock configuration */ + u8 reserved3[0x04]; /* 0x7c */ + u32 ats_cfg; /* 0x80 ats clock configuration */ + u32 trace_cfg; /* 0x84 trace clock configuration */ + u8 reserved4[0xf8]; /* 0x88 */ + u32 clk_output_a; /* 0x180 clk_output_a */ + u32 clk_output_b; /* 0x184 clk_output_a */ + u8 reserved5[0x278]; /* 0x188 */ + + u32 nand0_clk_cfg0; /* 0x400 nand0 clock configuration0 */ + u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */ + u8 reserved6[0x08]; /* 0x408 */ + u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */ + u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */ + u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */ + u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */ + u8 reserved7[0x08]; /* 0x420 */ + u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */ + u32 ss_clk_cfg; /* 0x42c security system clock cfg */ + u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */ + u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */ + u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */ + u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */ + u8 reserved8[0x50]; /* 0x440 */ + u32 de_clk_cfg; /* 0x490 display engine clock configuration */ + u8 reserved9[0x04]; /* 0x494 */ + u32 mp_clk_cfg; /* 0x498 mp clock configuration */ + u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */ + u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */ + u8 reserved10[0x1c]; /* 0x4a4 */ + u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */ + u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */ + u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */ + u32 fd_clk_cfg; /* 0x4cc FD module clock */ + u32 ve_clk_cfg; /* 0x4d0 VE module clock */ + u32 avs_clk_cfg; /* 0x4d4 AVS module clock */ + u8 reserved11[0x18]; /* 0x4d8 */ + u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */ + u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */ + u8 reserved12[0x10]; /* 0x4fc */ + u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */ + u8 reserved13[0x70]; /* 0x510 */ + + u32 ahb_gate0; /* 0x580 AHB0 Gating Register */ + u32 ahb_gate1; /* 0x584 AHB1 Gating Register */ + u32 ahb_gate2; /* 0x588 AHB2 Gating Register */ + u8 reserved14[0x04]; /* 0x58c */ + u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */ + u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */ + u8 reserved15[0x08]; /* 0x598 */ + u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */ + u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ + u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */ + u8 reserved16[0x04]; /* 0x5ac */ + u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */ + u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */ +}; + +/* pll4_periph0_cfg */ +#define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */ + +#define CCM_PLL4_CTRL_N_SHIFT 8 +#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT) +#define CCM_PLL4_CTRL_P_SHIFT 16 +#define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT) +#define CCM_PLL4_CTRL_M_SHIFT 18 +#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT) + +/* sd#_clk_cfg fields */ +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0 << 24) +#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24) +#define CCM_MMC_CTRL_ENABLE (1 << 31) + +/* ahb_gate0 fields */ +/* On sun9i all sdc-s share their ahb gate, so ignore (x) */ +#define AHB_GATE_OFFSET_MMC(x) 8 + +/* apb1_gate fields */ +#define APB1_GATE_UART_SHIFT 16 +#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) +#define APB1_GATE_TWI_SHIFT 0 +#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) + +/* ahb_reset0_cfg fields */ +/* On sun9i all sdc-s share their ahb reset, so ignore (x) */ +#define AHB_RESET_OFFSET_MMC(x) 8 + +/* apb1_reset_cfg fields */ +#define APB1_RESET_UART_SHIFT 16 +#define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT) +#define APB1_RESET_TWI_SHIFT 0 +#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) + + +#ifndef __ASSEMBLY__ +unsigned int clock_get_pll4_periph0(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 82b3d4676f..73583ed445 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -1,7 +1,5 @@ /* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,146 +7,10 @@ #ifndef _SUNXI_CPU_H #define _SUNXI_CPU_H -#define SUNXI_SRAM_A1_BASE 0x00000000 -#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ - -#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ -#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ -#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ -#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ -#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ - -#define SUNXI_SRAMC_BASE 0x01c00000 -#define SUNXI_DRAMC_BASE 0x01c01000 -#define SUNXI_DMA_BASE 0x01c02000 -#define SUNXI_NFC_BASE 0x01c03000 -#define SUNXI_TS_BASE 0x01c04000 -#define SUNXI_SPI0_BASE 0x01c05000 -#define SUNXI_SPI1_BASE 0x01c06000 -#define SUNXI_MS_BASE 0x01c07000 -#define SUNXI_TVD_BASE 0x01c08000 -#define SUNXI_CSI0_BASE 0x01c09000 -#define SUNXI_TVE0_BASE 0x01c0a000 -#define SUNXI_EMAC_BASE 0x01c0b000 -#define SUNXI_LCD0_BASE 0x01c0C000 -#define SUNXI_LCD1_BASE 0x01c0d000 -#define SUNXI_VE_BASE 0x01c0e000 -#define SUNXI_MMC0_BASE 0x01c0f000 -#define SUNXI_MMC1_BASE 0x01c10000 -#define SUNXI_MMC2_BASE 0x01c11000 -#define SUNXI_MMC3_BASE 0x01c12000 -#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I -#define SUNXI_USB0_BASE 0x01c13000 -#define SUNXI_USB1_BASE 0x01c14000 -#endif -#define SUNXI_SS_BASE 0x01c15000 -#define SUNXI_HDMI_BASE 0x01c16000 -#define SUNXI_SPI2_BASE 0x01c17000 -#define SUNXI_SATA_BASE 0x01c18000 -#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I -#define SUNXI_PATA_BASE 0x01c19000 -#define SUNXI_ACE_BASE 0x01c1a000 -#define SUNXI_TVE1_BASE 0x01c1b000 -#define SUNXI_USB2_BASE 0x01c1c000 +#if defined(CONFIG_MACH_SUN9I) +#include <asm/arch/cpu_sun9i.h> #else -#define SUNXI_USB0_BASE 0x01c19000 -#define SUNXI_USB1_BASE 0x01c1a000 -#define SUNXI_USB2_BASE 0x01c1b000 +#include <asm/arch/cpu_sun4i.h> #endif -#define SUNXI_CSI1_BASE 0x01c1d000 -#define SUNXI_TZASC_BASE 0x01c1e000 -#define SUNXI_SPI3_BASE 0x01c1f000 - -#define SUNXI_CCM_BASE 0x01c20000 -#define SUNXI_INTC_BASE 0x01c20400 -#define SUNXI_PIO_BASE 0x01c20800 -#define SUNXI_TIMER_BASE 0x01c20c00 -#define SUNXI_SPDIF_BASE 0x01c21000 -#define SUNXI_AC97_BASE 0x01c21400 -#define SUNXI_IR0_BASE 0x01c21800 -#define SUNXI_IR1_BASE 0x01c21c00 - -#define SUNXI_IIS_BASE 0x01c22400 -#define SUNXI_LRADC_BASE 0x01c22800 -#define SUNXI_AD_DA_BASE 0x01c22c00 -#define SUNXI_KEYPAD_BASE 0x01c23000 -#define SUNXI_TZPC_BASE 0x01c23400 -#define SUNXI_SID_BASE 0x01c23800 -#define SUNXI_SJTAG_BASE 0x01c23c00 - -#define SUNXI_TP_BASE 0x01c25000 -#define SUNXI_PMU_BASE 0x01c25400 -#define SUN7I_CPUCFG_BASE 0x01c25c00 - -#define SUNXI_UART0_BASE 0x01c28000 -#define SUNXI_UART1_BASE 0x01c28400 -#define SUNXI_UART2_BASE 0x01c28800 -#define SUNXI_UART3_BASE 0x01c28c00 -#define SUNXI_UART4_BASE 0x01c29000 -#define SUNXI_UART5_BASE 0x01c29400 -#define SUNXI_UART6_BASE 0x01c29800 -#define SUNXI_UART7_BASE 0x01c29c00 -#define SUNXI_PS2_0_BASE 0x01c2a000 -#define SUNXI_PS2_1_BASE 0x01c2a400 - -#define SUNXI_TWI0_BASE 0x01c2ac00 -#define SUNXI_TWI1_BASE 0x01c2b000 -#define SUNXI_TWI2_BASE 0x01c2b400 - -#define SUNXI_CAN_BASE 0x01c2bc00 - -#define SUNXI_SCR_BASE 0x01c2c400 - -#ifndef CONFIG_MACH_SUN6I -#define SUNXI_GPS_BASE 0x01c30000 -#define SUNXI_MALI400_BASE 0x01c40000 -#define SUNXI_GMAC_BASE 0x01c50000 -#else -#define SUNXI_GMAC_BASE 0x01c30000 -#endif - -#define SUNXI_DRAM_COM_BASE 0x01c62000 -#define SUNXI_DRAM_CTL0_BASE 0x01c63000 -#define SUNXI_DRAM_CTL1_BASE 0x01c64000 -#define SUNXI_DRAM_PHY0_BASE 0x01c65000 -#define SUNXI_DRAM_PHY1_BASE 0x01c66000 - -/* module sram */ -#define SUNXI_SRAM_C_BASE 0x01d00000 - -#define SUNXI_DE_FE0_BASE 0x01e00000 -#define SUNXI_DE_FE1_BASE 0x01e20000 -#define SUNXI_DE_BE0_BASE 0x01e60000 -#define SUNXI_DE_BE1_BASE 0x01e40000 -#define SUNXI_MP_BASE 0x01e80000 -#define SUNXI_AVG_BASE 0x01ea0000 - -#define SUNXI_RTC_BASE 0x01f00000 -#define SUNXI_PRCM_BASE 0x01f01400 -#define SUN6I_CPUCFG_BASE 0x01f01c00 -#define SUNXI_R_UART_BASE 0x01f02800 -#define SUNXI_R_PIO_BASE 0x01f02c00 -#define SUN6I_P2WI_BASE 0x01f03400 -#define SUNXI_RSB_BASE 0x01f03400 - -/* CoreSight Debug Module */ -#define SUNXI_CSDM_BASE 0x3f500000 - -#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ - -#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ - -#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) - -/* SS bonding ids used for cpu identification */ -#define SUNXI_SS_BOND_ID_A31 4 -#define SUNXI_SS_BOND_ID_A31S 5 - -#ifndef __ASSEMBLY__ -void sunxi_board_init(void); -void sunxi_reset(void); -int sunxi_get_ss_bonding_id(void); -int sunxi_get_sid(unsigned int *sid); -#endif /* __ASSEMBLY__ */ -#endif /* _CPU_H */ +#endif /* _SUNXI_CPU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h new file mode 100644 index 0000000000..dae60696f9 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_SUN4I_H +#define _SUNXI_CPU_SUN4I_H + +#define SUNXI_SRAM_A1_BASE 0x00000000 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ +#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ + +#define SUNXI_SRAMC_BASE 0x01c00000 +#define SUNXI_DRAMC_BASE 0x01c01000 +#define SUNXI_DMA_BASE 0x01c02000 +#define SUNXI_NFC_BASE 0x01c03000 +#define SUNXI_TS_BASE 0x01c04000 +#define SUNXI_SPI0_BASE 0x01c05000 +#define SUNXI_SPI1_BASE 0x01c06000 +#define SUNXI_MS_BASE 0x01c07000 +#define SUNXI_TVD_BASE 0x01c08000 +#define SUNXI_CSI0_BASE 0x01c09000 +#define SUNXI_TVE0_BASE 0x01c0a000 +#define SUNXI_EMAC_BASE 0x01c0b000 +#define SUNXI_LCD0_BASE 0x01c0C000 +#define SUNXI_LCD1_BASE 0x01c0d000 +#define SUNXI_VE_BASE 0x01c0e000 +#define SUNXI_MMC0_BASE 0x01c0f000 +#define SUNXI_MMC1_BASE 0x01c10000 +#define SUNXI_MMC2_BASE 0x01c11000 +#define SUNXI_MMC3_BASE 0x01c12000 +#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I +#define SUNXI_USB0_BASE 0x01c13000 +#define SUNXI_USB1_BASE 0x01c14000 +#endif +#define SUNXI_SS_BASE 0x01c15000 +#define SUNXI_HDMI_BASE 0x01c16000 +#define SUNXI_SPI2_BASE 0x01c17000 +#define SUNXI_SATA_BASE 0x01c18000 +#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I +#define SUNXI_PATA_BASE 0x01c19000 +#define SUNXI_ACE_BASE 0x01c1a000 +#define SUNXI_TVE1_BASE 0x01c1b000 +#define SUNXI_USB2_BASE 0x01c1c000 +#else +#define SUNXI_USB0_BASE 0x01c19000 +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#endif +#define SUNXI_CSI1_BASE 0x01c1d000 +#define SUNXI_TZASC_BASE 0x01c1e000 +#define SUNXI_SPI3_BASE 0x01c1f000 + +#define SUNXI_CCM_BASE 0x01c20000 +#define SUNXI_INTC_BASE 0x01c20400 +#define SUNXI_PIO_BASE 0x01c20800 +#define SUNXI_TIMER_BASE 0x01c20c00 +#define SUNXI_SPDIF_BASE 0x01c21000 +#define SUNXI_AC97_BASE 0x01c21400 +#define SUNXI_IR0_BASE 0x01c21800 +#define SUNXI_IR1_BASE 0x01c21c00 + +#define SUNXI_IIS_BASE 0x01c22400 +#define SUNXI_LRADC_BASE 0x01c22800 +#define SUNXI_AD_DA_BASE 0x01c22c00 +#define SUNXI_KEYPAD_BASE 0x01c23000 +#define SUNXI_TZPC_BASE 0x01c23400 +#define SUNXI_SID_BASE 0x01c23800 +#define SUNXI_SJTAG_BASE 0x01c23c00 + +#define SUNXI_TP_BASE 0x01c25000 +#define SUNXI_PMU_BASE 0x01c25400 +#define SUN7I_CPUCFG_BASE 0x01c25c00 + +#define SUNXI_UART0_BASE 0x01c28000 +#define SUNXI_UART1_BASE 0x01c28400 +#define SUNXI_UART2_BASE 0x01c28800 +#define SUNXI_UART3_BASE 0x01c28c00 +#define SUNXI_UART4_BASE 0x01c29000 +#define SUNXI_UART5_BASE 0x01c29400 +#define SUNXI_UART6_BASE 0x01c29800 +#define SUNXI_UART7_BASE 0x01c29c00 +#define SUNXI_PS2_0_BASE 0x01c2a000 +#define SUNXI_PS2_1_BASE 0x01c2a400 + +#define SUNXI_TWI0_BASE 0x01c2ac00 +#define SUNXI_TWI1_BASE 0x01c2b000 +#define SUNXI_TWI2_BASE 0x01c2b400 + +#define SUNXI_CAN_BASE 0x01c2bc00 + +#define SUNXI_SCR_BASE 0x01c2c400 + +#ifndef CONFIG_MACH_SUN6I +#define SUNXI_GPS_BASE 0x01c30000 +#define SUNXI_MALI400_BASE 0x01c40000 +#define SUNXI_GMAC_BASE 0x01c50000 +#else +#define SUNXI_GMAC_BASE 0x01c30000 +#endif + +#define SUNXI_DRAM_COM_BASE 0x01c62000 +#define SUNXI_DRAM_CTL0_BASE 0x01c63000 +#define SUNXI_DRAM_CTL1_BASE 0x01c64000 +#define SUNXI_DRAM_PHY0_BASE 0x01c65000 +#define SUNXI_DRAM_PHY1_BASE 0x01c66000 + +/* module sram */ +#define SUNXI_SRAM_C_BASE 0x01d00000 + +#define SUNXI_DE_FE0_BASE 0x01e00000 +#define SUNXI_DE_FE1_BASE 0x01e20000 +#define SUNXI_DE_BE0_BASE 0x01e60000 +#define SUNXI_DE_BE1_BASE 0x01e40000 +#define SUNXI_MP_BASE 0x01e80000 +#define SUNXI_AVG_BASE 0x01ea0000 + +#define SUNXI_RTC_BASE 0x01f00000 +#define SUNXI_PRCM_BASE 0x01f01400 +#define SUN6I_CPUCFG_BASE 0x01f01c00 +#define SUNXI_R_UART_BASE 0x01f02800 +#define SUNXI_R_PIO_BASE 0x01f02c00 +#define SUN6I_P2WI_BASE 0x01f03400 +#define SUNXI_RSB_BASE 0x01f03400 + +/* CoreSight Debug Module */ +#define SUNXI_CSDM_BASE 0x3f500000 + +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ + +#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +/* SS bonding ids used for cpu identification */ +#define SUNXI_SS_BOND_ID_A31 4 +#define SUNXI_SS_BOND_ID_A31S 5 + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +int sunxi_get_ss_bonding_id(void); +int sunxi_get_sid(unsigned int *sid); +#endif /* __ASSEMBLY__ */ + +#endif /* _SUNXI_CPU_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h new file mode 100644 index 0000000000..a2a7839c6b --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Jerry Wang <wangflord@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_SUN9I_H +#define _SUNXI_CPU_SUN9I_H + +#define REGS_AHB0_BASE 0x01C00000 +#define REGS_AHB1_BASE 0x00800000 +#define REGS_AHB2_BASE 0x03000000 +#define REGS_APB0_BASE 0x06000000 +#define REGS_APB1_BASE 0x07000000 +#define REGS_RCPUS_BASE 0x08000000 + +#define SUNXI_SRAM_D_BASE 0x08100000 + +/* AHB0 Module */ +#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) +#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) + +#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000) +#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000) +#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000) +#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) +#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) + +#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) +#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) +#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) +#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) + +#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) +#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) +#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) + +/* AHB1 Module */ +#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) +#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) +#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) +#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) +#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) + +/* AHB2 Module */ +#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) +#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) +#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) +#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) +#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) + +#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) +#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) +#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) + +#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) +#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) +#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) +#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) + +#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) +#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) +#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) +#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) +/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ +#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) +#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) + +/* APB0 Module */ +#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) +#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) +#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) +#define SUNXI_R_PIO_BASE (0x08002C00) +#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) +#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) +#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) + +/* APB1 Module */ +#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) +#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) +#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) +#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) +#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) +#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) +#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) +#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) +#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) +#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) +#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) + +/* RCPUS Module */ +#define SUNXI_RPRCM_BASE (REGS_RCPUS_BASE + 0x1400) +#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) + +/* Misc. */ +#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +int sunxi_get_sid(unsigned int *sid); +#endif + +#endif /* _SUNXI_CPU_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 2ac8a879df..5e94253203 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -9,6 +9,107 @@ #ifndef _SUNXI_DISPLAY_H #define _SUNXI_DISPLAY_H +struct sunxi_de_fe_reg { + u32 enable; /* 0x000 */ + u32 frame_ctrl; /* 0x004 */ + u32 bypass; /* 0x008 */ + u32 algorithm_sel; /* 0x00c */ + u32 line_int_ctrl; /* 0x010 */ + u8 res0[0x0c]; /* 0x014 */ + u32 ch0_addr; /* 0x020 */ + u32 ch1_addr; /* 0x024 */ + u32 ch2_addr; /* 0x028 */ + u32 field_sequence; /* 0x02c */ + u32 ch0_offset; /* 0x030 */ + u32 ch1_offset; /* 0x034 */ + u32 ch2_offset; /* 0x038 */ + u8 res1[0x04]; /* 0x03c */ + u32 ch0_stride; /* 0x040 */ + u32 ch1_stride; /* 0x044 */ + u32 ch2_stride; /* 0x048 */ + u32 input_fmt; /* 0x04c */ + u32 ch3_addr; /* 0x050 */ + u32 ch4_addr; /* 0x054 */ + u32 ch5_addr; /* 0x058 */ + u32 output_fmt; /* 0x05c */ + u32 int_enable; /* 0x060 */ + u32 int_status; /* 0x064 */ + u32 status; /* 0x068 */ + u8 res2[0x04]; /* 0x06c */ + u32 csc_coef00; /* 0x070 */ + u32 csc_coef01; /* 0x074 */ + u32 csc_coef02; /* 0x078 */ + u32 csc_coef03; /* 0x07c */ + u32 csc_coef10; /* 0x080 */ + u32 csc_coef11; /* 0x084 */ + u32 csc_coef12; /* 0x088 */ + u32 csc_coef13; /* 0x08c */ + u32 csc_coef20; /* 0x090 */ + u32 csc_coef21; /* 0x094 */ + u32 csc_coef22; /* 0x098 */ + u32 csc_coef23; /* 0x09c */ + u32 deinterlace_ctrl; /* 0x0a0 */ + u32 deinterlace_diag; /* 0x0a4 */ + u32 deinterlace_tempdiff; /* 0x0a8 */ + u32 deinterlace_sawtooth; /* 0x0ac */ + u32 deinterlace_spatcomp; /* 0x0b0 */ + u32 deinterlace_burstlen; /* 0x0b4 */ + u32 deinterlace_preluma; /* 0x0b8 */ + u32 deinterlace_tile_addr; /* 0x0bc */ + u32 deinterlace_tile_stride; /* 0x0c0 */ + u8 res3[0x0c]; /* 0x0c4 */ + u32 wb_stride_enable; /* 0x0d0 */ + u32 ch3_stride; /* 0x0d4 */ + u32 ch4_stride; /* 0x0d8 */ + u32 ch5_stride; /* 0x0dc */ + u32 fe_3d_ctrl; /* 0x0e0 */ + u32 fe_3d_ch0_addr; /* 0x0e4 */ + u32 fe_3d_ch1_addr; /* 0x0e8 */ + u32 fe_3d_ch2_addr; /* 0x0ec */ + u32 fe_3d_ch0_offset; /* 0x0f0 */ + u32 fe_3d_ch1_offset; /* 0x0f4 */ + u32 fe_3d_ch2_offset; /* 0x0f8 */ + u8 res4[0x04]; /* 0x0fc */ + u32 ch0_insize; /* 0x100 */ + u32 ch0_outsize; /* 0x104 */ + u32 ch0_horzfact; /* 0x108 */ + u32 ch0_vertfact; /* 0x10c */ + u32 ch0_horzphase; /* 0x110 */ + u32 ch0_vertphase0; /* 0x114 */ + u32 ch0_vertphase1; /* 0x118 */ + u8 res5[0x04]; /* 0x11c */ + u32 ch0_horztapoffset0; /* 0x120 */ + u32 ch0_horztapoffset1; /* 0x124 */ + u32 ch0_verttapoffset; /* 0x128 */ + u8 res6[0xd4]; /* 0x12c */ + u32 ch1_insize; /* 0x200 */ + u32 ch1_outsize; /* 0x204 */ + u32 ch1_horzfact; /* 0x208 */ + u32 ch1_vertfact; /* 0x20c */ + u32 ch1_horzphase; /* 0x210 */ + u32 ch1_vertphase0; /* 0x214 */ + u32 ch1_vertphase1; /* 0x218 */ + u8 res7[0x04]; /* 0x21c */ + u32 ch1_horztapoffset0; /* 0x220 */ + u32 ch1_horztapoffset1; /* 0x224 */ + u32 ch1_verttapoffset; /* 0x228 */ + u8 res8[0x1d4]; /* 0x22c */ + u32 ch0_horzcoef0[32]; /* 0x400 */ + u32 ch0_horzcoef1[32]; /* 0x480 */ + u32 ch0_vertcoef[32]; /* 0x500 */ + u8 res9[0x80]; /* 0x580 */ + u32 ch1_horzcoef0[32]; /* 0x600 */ + u32 ch1_horzcoef1[32]; /* 0x680 */ + u32 ch1_vertcoef[32]; /* 0x700 */ + u8 res10[0x280]; /* 0x780 */ + u32 vpp_enable; /* 0xa00 */ + u32 vpp_dcti; /* 0xa04 */ + u32 vpp_lp1; /* 0xa08 */ + u32 vpp_lp2; /* 0xa0c */ + u32 vpp_wle; /* 0xa10 */ + u32 vpp_ble; /* 0xa14 */ +}; + struct sunxi_de_be_reg { u8 res0[0x800]; /* 0x000 */ u32 mode; /* 0x800 */ @@ -210,6 +311,20 @@ struct sunxi_tve_reg { }; /* + * DE-FE register constants. + */ +#define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0) +#define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16) +#define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16) +#define SUNXI_DE_FE_ENABLE_EN (1 << 0) +#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0) +#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1) +#define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16) +#define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1) +#define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151 +#define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002 + +/* * DE-BE register constants. */ #define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0) @@ -219,6 +334,7 @@ struct sunxi_tve_reg { #define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8) #define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5) #define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0) +#define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8) /* @@ -249,9 +365,7 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0 (0 << 28) -#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60 (1 << 28) -#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE120 (2 << 28) +#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) #define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h index 6c1ec5be86..40c385a5bc 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h @@ -76,7 +76,7 @@ struct dram_para { u32 cas; u32 zq; u32 odt_en; - u32 size; + u32 size; /* For compat with dram.c files from u-boot-sunxi, unused */ u32 tpr0; u32 tpr1; u32 tpr2; diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 537f145564..74833b51d1 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -43,10 +43,11 @@ struct sunxi_mmc { u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ u32 res1[26]; -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ + defined(CONFIG_MACH_SUN9I) u32 res2[64]; #endif - u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */ + u32 fifo; /* 0x100 / 0x200 FIFO access address */ }; #define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) @@ -123,5 +124,8 @@ struct sunxi_mmc { #define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) #define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) +#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) +#define SUNXI_MMC_COMMON_RESET (1 << 18) + struct mmc *sunxi_mmc_init(int sdc_no); #endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h index 8d2097336c..cb538cdc7d 100644 --- a/arch/arm/include/asm/arch-sunxi/usbc.h +++ b/arch/arm/include/asm/arch-sunxi/usbc.h @@ -11,6 +11,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +extern const struct musb_platform_ops sunxi_musb_ops; + void *sunxi_usbc_get_io_base(int index); int sunxi_usbc_request_resources(int index); int sunxi_usbc_free_resources(int index); diff --git a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h index 484559c6cd..6b7d600a9c 100644 --- a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h +++ b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h @@ -72,7 +72,7 @@ struct ddrphy { u32 gtr; /* General Timing Register */ u32 rsv[3]; /* Reserved */ } dx[9]; -} __packed; +}; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h index fa5e6ae0f2..4ae67c8adb 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -25,22 +25,29 @@ /* Memory Configuration */ #define SG_MEMCONF (SG_CTRL_BASE | 0x0400) -#define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0)) -#define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0)) -#define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0)) -#define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0)) -#define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0)) +#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0)) +#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0)) +#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0)) #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8) #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8) -#define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2)) -#define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2)) -#define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2)) -#define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2)) -#define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2)) +#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2)) +#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2)) +#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2)) #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) +#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16)) +#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) +#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) +#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) +#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) +#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) + #define SG_MEMCONF_SPARSEMEM (0x1 << 4) /* Pin Control */ @@ -101,6 +108,7 @@ #else #include <linux/types.h> +#include <linux/sizes.h> #include <asm/io.h> static inline void sg_set_pinsel(int n, int value) @@ -111,24 +119,24 @@ static inline void sg_set_pinsel(int n, int value) static inline u32 sg_memconf_val_ch0(unsigned long size, int num) { - int size_mb = (size >> 20) / num; + int size_mb = size / num; u32 ret; switch (size_mb) { - case 64: - ret = SG_MEMCONF_CH0_SIZE_64MB; + case SZ_64M: + ret = SG_MEMCONF_CH0_SZ_64M; break; - case 128: - ret = SG_MEMCONF_CH0_SIZE_128MB; + case SZ_128M: + ret = SG_MEMCONF_CH0_SZ_128M; break; - case 256: - ret = SG_MEMCONF_CH0_SIZE_256MB; + case SZ_256M: + ret = SG_MEMCONF_CH0_SZ_256M; break; - case 512: - ret = SG_MEMCONF_CH0_SIZE_512MB; + case SZ_512M: + ret = SG_MEMCONF_CH0_SZ_512M; break; - case 1024: - ret = SG_MEMCONF_CH0_SIZE_1024MB; + case SZ_1G: + ret = SG_MEMCONF_CH0_SZ_1G; break; default: BUG(); @@ -151,24 +159,24 @@ static inline u32 sg_memconf_val_ch0(unsigned long size, int num) static inline u32 sg_memconf_val_ch1(unsigned long size, int num) { - int size_mb = (size >> 20) / num; + int size_mb = size / num; u32 ret; switch (size_mb) { - case 64: - ret = SG_MEMCONF_CH1_SIZE_64MB; + case SZ_64M: + ret = SG_MEMCONF_CH1_SZ_64M; break; - case 128: - ret = SG_MEMCONF_CH1_SIZE_128MB; + case SZ_128M: + ret = SG_MEMCONF_CH1_SZ_128M; break; - case 256: - ret = SG_MEMCONF_CH1_SIZE_256MB; + case SZ_256M: + ret = SG_MEMCONF_CH1_SZ_256M; break; - case 512: - ret = SG_MEMCONF_CH1_SIZE_512MB; + case SZ_512M: + ret = SG_MEMCONF_CH1_SZ_512M; break; - case 1024: - ret = SG_MEMCONF_CH1_SIZE_1024MB; + case SZ_1G: + ret = SG_MEMCONF_CH1_SZ_1G; break; default: BUG(); @@ -188,6 +196,43 @@ static inline u32 sg_memconf_val_ch1(unsigned long size, int num) } return ret; } + +static inline u32 sg_memconf_val_ch2(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH2_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH2_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH2_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH2_SZ_512M; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH2_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH2_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} #endif /* __ASSEMBLY__ */ #endif /* ARCH_SG_REGS_H */ diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 2aede0c552..e2e0b7321a 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -21,6 +21,9 @@ #define ZYNQ_I2C_BASEADDR1 0xE0005000 #define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR1 0xE0007000 +#define ZYNQ_QSPI_BASEADDR 0xE000D000 +#define ZYNQ_SMC_BASEADDR 0xE000E000 +#define ZYNQ_NAND_BASEADDR 0xE1000000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 #define ZYNQ_EFUSE_BASEADDR 0xF800D000 #define ZYNQ_USB_BASEADDR0 0xE0002000 @@ -28,7 +31,9 @@ /* Bootmode setting values */ #define ZYNQ_BM_MASK 0x7 +#define ZYNQ_BM_QSPI 0x1 #define ZYNQ_BM_NOR 0x2 +#define ZYNQ_BM_NAND 0x4 #define ZYNQ_BM_SD 0x5 #define ZYNQ_BM_JTAG 0x0 diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 89c47f3bd3..9d50e2478f 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -20,7 +20,7 @@ extern void zynq_ddrc_init(void); extern unsigned int zynq_get_silicon_version(void); /* Driver extern functions */ -extern int zynq_sdhci_init(u32 regbase); +extern int zynq_sdhci_init(phys_addr_t regbase); extern int zynq_sdhci_of_init(const void *blob); extern void ps7_init(void); |
