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-rw-r--r--arch/arm/cpu/pxa/Makefile7
-rw-r--r--arch/arm/cpu/pxa/cpuinfo.c132
-rw-r--r--arch/arm/cpu/pxa/pxa2xx.c (renamed from arch/arm/cpu/pxa/cpu.c)119
-rw-r--r--arch/arm/cpu/pxa/start.S456
-rw-r--r--arch/arm/cpu/pxa/timer.c91
-rw-r--r--arch/arm/cpu/pxa/u-boot.lds6
-rw-r--r--arch/arm/cpu/pxa/usb.c12
7 files changed, 459 insertions, 364 deletions
diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
index e8b59a30c9..e088832560 100644
--- a/arch/arm/cpu/pxa/Makefile
+++ b/arch/arm/cpu/pxa/Makefile
@@ -27,7 +27,12 @@ LIB = $(obj)lib$(CPU).o
START = start.o
-COBJS += cpu.o
+COBJS-$(CONFIG_CPU_PXA25X) = pxa2xx.o
+COBJS-$(CONFIG_CPU_PXA27X) = pxa2xx.o
+
+COBJS-y += cpuinfo.o
+
+COBJS = $(COBJS-y)
COBJS += pxafb.o
COBJS += timer.o
COBJS += usb.o
diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c
new file mode 100644
index 0000000000..f1cdd408eb
--- /dev/null
+++ b/arch/arm/cpu/pxa/cpuinfo.c
@@ -0,0 +1,132 @@
+/*
+ * PXA CPU information display
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <linux/compiler.h>
+
+#define CPU_MASK_PXA_REVID 0x00f
+
+#define CPU_MASK_PXA_PRODID 0x3f0
+#define CPU_VALUE_PXA25X 0x100
+#define CPU_VALUE_PXA27X 0x110
+
+static uint32_t pxa_get_cpuid(void)
+{
+ uint32_t cpuid;
+ asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid));
+ return cpuid;
+}
+
+int cpu_is_pxa25x(void)
+{
+ uint32_t id = pxa_get_cpuid();
+ id &= CPU_MASK_PXA_PRODID;
+ return id == CPU_VALUE_PXA25X;
+}
+
+int cpu_is_pxa27x(void)
+{
+ uint32_t id = pxa_get_cpuid();
+ id &= CPU_MASK_PXA_PRODID;
+ return id == CPU_VALUE_PXA27X;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static const char *pxa25x_get_revision(void)
+{
+ static __maybe_unused const char * const revs_25x[] = { "A0" };
+ static __maybe_unused const char * const revs_26x[] = {
+ "A0", "B0", "B1"
+ };
+ static const char *unknown = "Unknown";
+ uint32_t id;
+
+ if (!cpu_is_pxa25x())
+ return unknown;
+
+ id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
+
+/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */
+#ifdef CONFIG_CPU_PXA26X
+ switch (id) {
+ case 3: return revs_26x[0];
+ case 5: return revs_26x[1];
+ case 6: return revs_26x[2];
+ }
+#else
+ if (id == 6)
+ return revs_25x[0];
+#endif
+ return unknown;
+}
+
+static const char *pxa27x_get_revision(void)
+{
+ static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" };
+ static const char *unknown = "Unknown";
+ uint32_t id;
+
+ if (!cpu_is_pxa27x())
+ return unknown;
+
+ id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
+
+ if ((id == 5) || (id == 6) || (id > 7))
+ return unknown;
+
+ /* Cap the special PXA270 C5 case. */
+ if (id == 7)
+ id = 5;
+
+ return rev[id];
+}
+
+static int print_cpuinfo_pxa2xx(void)
+{
+ if (cpu_is_pxa25x()) {
+ puts("Marvell PXA25x rev. ");
+ puts(pxa25x_get_revision());
+ } else if (cpu_is_pxa27x()) {
+ puts("Marvell PXA27x rev. ");
+ puts(pxa27x_get_revision());
+ } else
+ return -EINVAL;
+
+ puts("\n");
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ int ret;
+
+ puts("CPU: ");
+
+ ret = print_cpuinfo_pxa2xx();
+ if (!ret)
+ return ret;
+
+ return ret;
+}
+#endif
diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/pxa2xx.c
index df351c7fbc..09e8177f7b 100644
--- a/arch/arm/cpu/pxa/cpu.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -26,88 +26,52 @@
* MA 02111-1307 USA
*/
-/*
- * CPU specific code
- */
-
#include <asm/io.h>
#include <asm/system.h>
#include <command.h>
#include <common.h>
#include <asm/arch/pxa-regs.h>
-static void cache_flush(void);
+/* Flush I/D-cache */
+static void cache_flush(void)
+{
+ unsigned long i = 0;
-int cleanup_before_linux (void)
+ asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
+}
+
+int cleanup_before_linux(void)
{
/*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * just disable everything that can disturb booting linux
+ * This function is called just before we call Linux. It prepares
+ * the processor for Linux by just disabling everything that can
+ * disturb booting Linux.
*/
- disable_interrupts ();
-
- /* turn off I-cache */
+ disable_interrupts();
icache_disable();
dcache_disable();
-
- /* flush I-cache */
cache_flush();
- return (0);
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
- unsigned long i = 0;
-
- asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-#ifndef CONFIG_CPU_MONAHANS
-void set_GPIO_mode(int gpio_mode)
-{
- int gpio = gpio_mode & GPIO_MD_MASK_NR;
- int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
- int val;
-
- /* This below changes direction setting of GPIO "gpio" */
- val = readl(GPDR(gpio));
-
- if (gpio_mode & GPIO_MD_MASK_DIR)
- val |= GPIO_bit(gpio);
- else
- val &= ~GPIO_bit(gpio);
-
- writel(val, GPDR(gpio));
-
- /* This below updates only AF of GPIO "gpio" */
- val = readl(GAFR(gpio));
- val &= ~(0x3 << (((gpio) & 0xf) * 2));
- val |= fn << (((gpio) & 0xf) * 2);
- writel(val, GAFR(gpio));
+ return 0;
}
-#endif /* CONFIG_CPU_MONAHANS */
void pxa_wait_ticks(int ticks)
{
writel(0, OSCR);
while (readl(OSCR) < ticks)
- asm volatile("":::"memory");
+ asm volatile("" : : : "memory");
}
inline void writelrb(uint32_t val, uint32_t addr)
{
writel(val, addr);
- asm volatile("":::"memory");
+ asm volatile("" : : : "memory");
readl(addr);
- asm volatile("":::"memory");
+ asm volatile("" : : : "memory");
}
-void pxa_dram_init(void)
+void pxa2xx_dram_init(void)
{
uint32_t tmp;
int i;
@@ -201,7 +165,7 @@ void pxa_dram_init(void)
*/
for (i = 9; i >= 0; i--) {
writel(i, 0xa0000000);
- asm volatile("":::"memory");
+ asm volatile("" : : : "memory");
}
/*
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
@@ -234,21 +198,21 @@ void pxa_gpio_setup(void)
writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
#endif
writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
#endif
writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
#endif
@@ -258,7 +222,7 @@ void pxa_gpio_setup(void)
writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
#endif
@@ -270,7 +234,7 @@ void pxa_interrupt_setup(void)
{
writel(0, ICLR);
writel(0, ICMR);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X)
writel(0, ICLR2);
writel(0, ICMR2);
#endif
@@ -278,18 +242,14 @@ void pxa_interrupt_setup(void)
void pxa_clock_setup(void)
{
-#ifndef CONFIG_CPU_MONAHANS
writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR);
- asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2));
-#else
-/* Set CKENA/CKENB/ACCR for MH */
-#endif
+ asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2));
/* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC);
- while(!(readl(OSCC) & OSCC_OOK))
- asm volatile("":::"memory");
+ while (!(readl(OSCC) & OSCC_OOK))
+ asm volatile("" : : : "memory");
}
void pxa_wakeup(void)
@@ -302,17 +262,16 @@ void pxa_wakeup(void)
/* Wakeup */
if (rcsr & RCSR_SMR) {
writel(PSSR_PH, PSSR);
- pxa_dram_init();
+ pxa2xx_dram_init();
icache_disable();
dcache_disable();
- asm volatile("mov pc, %0"::"r"(readl(PSPR)));
+ asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
}
}
int arch_cpu_init(void)
{
pxa_gpio_setup();
-/* pxa_wait_ticks(0x8000); */
pxa_wakeup();
pxa_interrupt_setup();
pxa_clock_setup();
@@ -321,10 +280,22 @@ int arch_cpu_init(void)
void i2c_clk_enable(void)
{
- /* set the global I2C clock on */
-#ifdef CONFIG_CPU_MONAHANS
- writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
-#else
+ /* Set the global I2C clock on */
writel(readl(CKEN) | CKEN14_I2C, CKEN);
-#endif
+}
+
+void reset_cpu(ulong ignored) __attribute__((noreturn));
+
+void reset_cpu(ulong ignored)
+{
+ uint32_t tmp;
+
+ setbits_le32(OWER, OWER_WME);
+
+ tmp = readl(OSCR);
+ tmp += 0x1000;
+ writel(tmp, OSMR3);
+
+ for (;;)
+ ;
}
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 6191a73a54..ba0de8f1db 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -1,14 +1,20 @@
/*
- * armboot - Startup Code for XScale
+ * armboot - Startup Code for XScale CPU-core
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
+ * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
+ * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
+ * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
- * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
- * Copyright (c) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -32,14 +38,12 @@
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
-#include <asm/arch/pxa-regs.h>
-/* takes care the CP15 update has taken place */
-.macro CPWAIT reg
-mrc p15,0,\reg,c2,c0,0
-mov \reg,\reg
-sub pc,pc,#4
-.endm
+#ifdef CONFIG_CPU_PXA25X
+#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
+#error "Init SP address must be set to 0xfffff800 for PXA250"
+#endif
+#endif
.globl _start
_start: b reset
@@ -77,26 +81,38 @@ _data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
+_pad: .word 0x12345678 /* now 16*4=64 */
#endif /* CONFIG_SPL_BUILD */
+.global _end_vect
+_end_vect:
.balignl 16,0xdeadbeef
-
-
/*
+ *************************************************************************
+ *
* Startup Code (reset vector)
*
- * do important init only if we don't start from RAM!
- * - relocate armboot to RAM
- * - setup stack
- * - jump to second stage
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
*/
.globl _TEXT_BASE
_TEXT_BASE:
+#ifdef CONFIG_SPL_BUILD
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
.globl _bss_start_ofs
_bss_start_ofs:
@@ -120,9 +136,8 @@ IRQ_STACK_START:
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
-#endif /* CONFIG_USE_IRQ */
+#endif
-#ifndef CONFIG_SPL_BUILD
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@@ -141,95 +156,23 @@ reset:
orr r0,r0,#0xd3
msr cpsr,r0
- /*
- * Enable MMU to use DCache as DRAM
- */
- /* Domain access -- enable for all CPs */
- ldr r0, =0x0000ffff
- mcr p15, 0, r0, c3, c0, 0
-
- /* Point TTBR to MMU table */
- ldr r0, =mmu_table
- adr r2, _start
- orr r0, r2
- mcr p15, 0, r0, c2, c0, 0
-
-/* !!! Hereby, check if the code is running from SRAM !!! */
-/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
- * is linked to 0x0 too, so this makes things easier. */
- cmp r2, #0x5c000000
-
- ldreq r1, [r0]
- orreq r1, r2
- streq r1, [r0]
-
- /* Kick in MMU, ICache, DCache, BTB */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, #0x1b00
- bic r0, #0x0087
- orr r0, #0x1800
- orr r0, #0x0005
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- /* Unlock Icache, Dcache */
- mcr p15, 0, r0, c9, c1, 1
- mcr p15, 0, r0, c9, c2, 1
-
- /* Flush Icache, Dcache, BTB */
- mcr p15, 0, r0, c7, c7, 0
-
- /* Unlock I-TLB, D-TLB */
- mcr p15, 0, r0, c10, c4, 1
- mcr p15, 0, r0, c10, c8, 1
-
- /* Flush TLB */
- mcr p15, 0, r0, c8, c7, 0
- /* Allocate 4096 bytes of Dcache as RAM */
-
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4
-
- mov r4, #0x00
- mov r5, #0x00
- mov r2, #0x01
- mcr p15, 0, r0, c9, c2, 0
- CPWAIT r0
-
- /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
- mov r0, #128
- mov r1, #0xa0000000
-alloc:
- mcr p15, 0, r1, c7, c2, 5
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4
- strd r4, [r1], #8
- strd r4, [r1], #8
- strd r4, [r1], #8
- strd r4, [r1], #8
- subs r0, #0x01
- bne alloc
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4
- mov r2, #0x00
- mcr p15, 0, r2, c9, c2, 0
- CPWAIT r0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ bl cpu_init_crit
+#endif
- /* Jump to 0x0 ( + offset) if running from SRAM */
- adr r0, zerojmp
- bic r0, #0x5c000000
- mov pc, r0
-zerojmp:
+#ifdef CONFIG_CPU_PXA25X
+ bl lock_cache_for_stack
+#endif
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
+ ldr r0, =0x00000000
bl board_init_f
/*------------------------------------------------------------------------------*/
-
+#ifndef CONFIG_SPL_BUILD
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@@ -247,6 +190,11 @@ relocate_code:
stack_setup:
mov sp, r4
+/* Disable the Dcache RAM lock for stack now */
+#ifdef CONFIG_CPU_PXA25X
+ bl cpu_init_crit
+#endif
+
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
@@ -254,13 +202,11 @@ stack_setup:
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
- stmfd sp!, {r0-r12}
copy_loop:
- ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
- stmia r1!, {r3-r5, r7-r11} /* copy to target address [r1] */
+ ldmia r0!, {r9-r10} /* copy from source address [r0] */
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
- ldmfd sp!, {r0-r12}
#ifndef CONFIG_SPL_BUILD
/*
@@ -275,13 +221,13 @@ copy_loop:
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
+ cmp r7, #23 /* relative fixup? */
beq fixrel
- cmp r7, #2 /* absolute fixup? */
+ cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@@ -298,10 +244,10 @@ fixrel:
add r1, r1, r9
fixnext:
str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
-#endif /* #ifndef CONFIG_SPL_BUILD */
+#endif
clear_bss:
#ifndef CONFIG_SPL_BUILD
@@ -322,15 +268,16 @@ clbss_l:str r2, [r0] /* clear loop... */
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
-#ifdef CONFIG_ONENAND_IPL
- ldr r0, _start_oneboot_ofs
+#ifdef CONFIG_ONENAND_SPL
+ ldr r0, _onenand_boot_ofs
mov pc, r0
-_start_oneboot_ofs
- : .word start_oneboot
+_onenand_boot_ofs:
+ .word onenand_boot
#else
+jump_2_ram:
ldr r0, _board_init_r_ofs
- adr r1, _start
+ ldr r1, _TEXT_BASE
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
@@ -341,7 +288,7 @@ _start_oneboot_ofs
_board_init_r_ofs:
.word board_init_r - _start
-#endif /* CONFIG_ONENAND_IPL */
+#endif
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
@@ -349,43 +296,50 @@ _rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
-
-#else /* CONFIG_SPL_BUILD */
-
-/****************************************************************************/
-/* */
-/* the actual reset code for OneNAND IPL */
-/* */
-/****************************************************************************/
-
-#ifndef CONFIG_PXA27X
-#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
#endif
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
-reset:
- /* Set CPU to SVC32 mode */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0x13
- msr cpsr,r0
-
- /* Point stack at the end of SRAM and leave 32 words for abort-stack */
- ldr sp, =0x5c03ff80
-
- /* Start OneNAND IPL */
- ldr pc, =start_oneboot
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
+ mcr p15, 0, r0, c1, c0, 0
-#endif /* CONFIG_SPL_BUILD */
+ mov pc, lr /* back to my caller */
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
#ifndef CONFIG_SPL_BUILD
-/****************************************************************************/
-/* */
-/* Interrupt handling */
-/* */
-/****************************************************************************/
-
-/* IRQ stack frame */
-
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
@@ -409,37 +363,36 @@ reset:
#define S_R0 0
#define MODE_SVC 0x13
+#define I_BIT 0x80
- /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
.macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} /* Calling r0-r12 */
- add r8, sp, #S_PC
+ sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
+ stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
- ldr r2, IRQ_STACK_START_IN
- ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
- add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
+ ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
+ ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
+ add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
- stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
- mov r0, sp
+ stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
+ mov r0, sp @ save current stack into r0 (param register)
.endm
-
- /* use irq_save_user_regs / irq_restore_user_regs for */
- /* IRQ/FIQ handling */
-
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} /* Calling r0-r12 */
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ /* Calling SP, LR */
- str lr, [r8, #0] /* Save calling PC */
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
- str r6, [r8, #4] /* Save CPSR */
- str r0, [r8, #8] /* Save OLD_R0 */
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
@@ -452,16 +405,28 @@ reset:
.endm
.macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
+ ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
- str lr, [r13] @ save caller lr / spsr
- mrs lr, spsr
- str lr, [r13, #4]
+ str lr, [r13] @ save caller lr in position 0 of saved stack
+ mrs lr, spsr @ get the spsr
+ str lr, [r13, #4] @ save spsr in position 1 of saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
- msr spsr_c, r13
- mov lr, pc
- movs pc, lr
+ @ msr spsr_c, r13
+ msr spsr, r13 @ switch modes, make sure moves will execute
+ mov lr, pc @ capture return pc
+ movs pc, lr @ jump to next instruction & switch modes.
+ .endm
+
+ .macro get_bad_stack_swi
+ sub r13, r13, #4 @ space on current stack for scratch reg.
+ str r0, [r13] @ save R0's value.
+ ldr r0, IRQ_STACK_START_IN @ get data regions start
+ str lr, [r0] @ save caller lr in position 0 of saved stack
+ mrs r0, spsr @ get the spsr
+ str lr, [r0, #4] @ save spsr in position 1 of saved stack
+ ldr r0, [r13] @ restore r0
+ add r13, r13, #4 @ pop stack entry
.endm
.macro get_irq_stack @ setup IRQ stack
@@ -471,21 +436,17 @@ reset:
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
-#endif /* CONFIG_SPL_BUILD
-
-
-/****************************************************************************/
-/* */
-/* exception handlers */
-/* */
-/****************************************************************************/
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * exception handlers
+ */
#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
- ldr sp, _TEXT_BASE /* use 32 words abort stack */
+ ldr sp, _TEXT_BASE /* use 32 words about stack */
bl hang /* hang and never return */
-#else
+#else /* !CONFIG_SPL_BUILD */
.align 5
undefined_instruction:
get_bad_stack
@@ -494,7 +455,7 @@ undefined_instruction:
.align 5
software_interrupt:
- get_bad_stack
+ get_bad_stack_swi
bad_save_user_regs
bl do_software_interrupt
@@ -528,11 +489,12 @@ irq:
.align 5
fiq:
get_fiq_stack
- irq_save_user_regs /* someone ought to write a more */
- bl do_fiq /* effiction fiq_save_user_regs */
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
irq_restore_user_regs
-#else /* !CONFIG_USE_IRQ */
+#else
.align 5
irq:
@@ -545,63 +507,99 @@ fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
+
+#endif
+ .align 5
#endif /* CONFIG_SPL_BUILD */
-#endif /* CONFIG_USE_IRQ */
-/****************************************************************************/
-/* */
-/* Reset function: the PXA250 doesn't have a reset function, so we have to */
-/* perform a watchdog timeout for a soft reset. */
-/* */
-/****************************************************************************/
-/* Operating System Timer */
-.align 5
-.globl reset_cpu
- /* FIXME: this code is PXA250 specific. How is this handled on */
- /* other XScale processors? */
+/*
+ * Enable MMU to use DCache as DRAM.
+ *
+ * This is useful on PXA25x and PXA26x in early bootstages, where there is no
+ * other possible memory available to hold stack.
+ */
+#ifdef CONFIG_CPU_PXA25X
+.macro CPWAIT reg
+ mrc p15, 0, \reg, c2, c0, 0
+ mov \reg, \reg
+ sub pc, pc, #4
+.endm
+lock_cache_for_stack:
+ /* Domain access -- enable for all CPs */
+ ldr r0, =0x0000ffff
+ mcr p15, 0, r0, c3, c0, 0
-reset_cpu:
+ /* Point TTBR to MMU table */
+ ldr r0, =mmutable
+ mcr p15, 0, r0, c2, c0, 0
- /* We set OWE:WME (watchdog enable) and wait until timeout happens */
+ /* Kick in MMU, ICache, DCache, BTB */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, #0x1b00
+ bic r0, #0x0087
+ orr r0, #0x1800
+ orr r0, #0x0005
+ mcr p15, 0, r0, c1, c0, 0
+ CPWAIT r0
- ldr r0, =OWER
- ldr r1, [r0]
- orr r1, r1, #0x0001 /* bit0: WME */
- str r1, [r0]
+ /* Unlock Icache, Dcache */
+ mcr p15, 0, r0, c9, c1, 1
+ mcr p15, 0, r0, c9, c2, 1
- /* OS timer does only wrap every 1165 seconds, so we have to set */
- /* the match register as well. */
+ /* Flush Icache, Dcache, BTB */
+ mcr p15, 0, r0, c7, c7, 0
- ldr r0, =OSCR
- ldr r1, [r0] /* read OS timer */
- add r1, r1, #0x800 /* let OSMR3 match after */
- add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
- ldr r0, =OSMR3
- str r1, [r0]
+ /* Unlock I-TLB, D-TLB */
+ mcr p15, 0, r0, c10, c4, 1
+ mcr p15, 0, r0, c10, c8, 1
-reset_endless:
+ /* Flush TLB */
+ mcr p15, 0, r0, c8, c7, 0
- b reset_endless
+ /* Allocate 4096 bytes of Dcache as RAM */
-#ifndef CONFIG_SPL_BUILD
-.section .mmudata, "a"
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+
+ mov r4, #0x00
+ mov r5, #0x00
+ mov r2, #0x01
+ mcr p15, 0, r0, c9, c2, 0
+ CPWAIT r0
+
+ /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
+ mov r0, #128
+ ldr r1, =0xfffff000
+
+alloc:
+ mcr p15, 0, r1, c7, c2, 5
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ subs r0, #0x01
+ bne alloc
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+ mov r2, #0x00
+ mcr p15, 0, r2, c9, c2, 0
+ CPWAIT r0
+
+ mov pc, lr
+
+.section .mmutable, "a"
+mmutable:
.align 14
- .globl mmu_table
-mmu_table:
- /* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
+ /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
.set __base, 0
- .rept 0xa00
+ .rept 0xfff
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
- /* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
- .word (0xa00 << 20) | 0x1c1e
-
- .set __base, 0xa01
- .rept 0x1000 - 0xa01
- .word (__base << 20) | 0xc12
- .set __base, __base + 1
- .endr
-#endif /* CONFIG_SPL_BUILD */
+ /* 0xfff00000 : 1:1, cached mapping */
+ .word (0xfff << 20) | 0x1c1e
+#endif /* CONFIG_CPU_PXA25X */
diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c
index 2866745472..b7b0da98a4 100644
--- a/arch/arm/cpu/pxa/timer.c
+++ b/arch/arm/cpu/pxa/timer.c
@@ -1,11 +1,7 @@
/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
+ * Marvell PXA2xx/3xx timer driver
*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -31,55 +27,63 @@
#include <common.h>
#include <div64.h>
-#ifdef CONFIG_USE_IRQ
-#error: interrupts not implemented yet
-#endif
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+#define timestamp (gd->tbl)
+#define lastinc (gd->lastinc)
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define TIMER_FREQ_HZ 3250000
-#elif defined(CONFIG_PXA250)
-#define TIMER_FREQ_HZ 3686400
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define TIMER_FREQ_HZ 3250000
+#elif defined(CONFIG_CPU_PXA25X)
+#define TIMER_FREQ_HZ 3686400
#else
#error "Timer frequency unknown - please config PXA CPU type"
#endif
-static inline unsigned long long tick_to_time(unsigned long long tick)
+static unsigned long long tick_to_time(unsigned long long tick)
{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, TIMER_FREQ_HZ);
- return tick;
+ return tick * CONFIG_SYS_HZ / TIMER_FREQ_HZ;
}
-static inline unsigned long long us_to_tick(unsigned long long us)
+static unsigned long long us_to_tick(unsigned long long us)
{
- us = us * TIMER_FREQ_HZ + 999999;
- do_div(us, 1000000);
- return us;
+ return (us * TIMER_FREQ_HZ) / 1000000;
}
-int timer_init (void)
+int timer_init(void)
{
writel(0, OSCR);
-
return 0;
}
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
+unsigned long long get_ticks(void)
{
- udelay_masked (usec);
+ /* Current tick value */
+ uint32_t now = readl(OSCR);
+
+ if (now >= lastinc) {
+ /*
+ * Normal mode (non roll)
+ * Move stamp forward with absolute diff ticks
+ */
+ timestamp += (now - lastinc);
+ } else {
+ /* We have rollover of incrementer */
+ timestamp += (TIMER_LOAD_VAL - lastinc) + now;
+ }
+
+ lastinc = now;
+ return timestamp;
}
-ulong get_timer_masked (void)
+ulong get_timer(ulong base)
{
- return tick_to_time(get_ticks());
+ return tick_to_time(get_ticks()) - base;
}
-void udelay_masked (unsigned long usec)
+void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
@@ -89,25 +93,4 @@ void udelay_masked (unsigned long usec)
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
-
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return readl(OSCR);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
- tbclk = TIMER_FREQ_HZ;
- return tbclk;
}
diff --git a/arch/arm/cpu/pxa/u-boot.lds b/arch/arm/cpu/pxa/u-boot.lds
index e163369bc3..e86e7818e6 100644
--- a/arch/arm/cpu/pxa/u-boot.lds
+++ b/arch/arm/cpu/pxa/u-boot.lds
@@ -63,6 +63,12 @@ SECTIONS
*(.dynsym)
}
+ . = ALIGN(4096);
+
+ .mmutable : {
+ *(.mmutable)
+ }
+
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c
index 0311d5e997..83022e2e56 100644
--- a/arch/arm/cpu/pxa/usb.c
+++ b/arch/arm/cpu/pxa/usb.c
@@ -24,7 +24,7 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
@@ -37,7 +37,7 @@ int usb_cpu_init(void)
writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
udelay(100);
#endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
/* Enable USB host clock. */
writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
#endif
@@ -58,7 +58,7 @@ int usb_cpu_init(void)
#if defined(CONFIG_CPU_MONAHANS)
writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
#endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
@@ -78,7 +78,7 @@ int usb_cpu_stop(void)
#if defined(CONFIG_CPU_MONAHANS)
writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
#endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
@@ -88,7 +88,7 @@ int usb_cpu_stop(void)
writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
udelay(100);
#endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
/* Disable USB host clock. */
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
#endif
@@ -101,5 +101,5 @@ int usb_cpu_init_fail(void)
return usb_cpu_stop();
}
-# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
+# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
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